Enhanced Linearity in Intracranial Pressure Monitoring System Through Sample Isolation Bridge ROIC

Abstract

This study presents a sample isolation bridge readout integrated circuit (ROIC) specifically designed for intracranial pressure (ICP) monitoring systems. The ROIC consists of an instrumentation amplifier (IA) and a successive approximation register (SAR) analog-to-digital converter (ADC). Additionally, the output of the IA is isolated to protect against output spikes that could compromise the linearity and stability of the ROIC. Both traditional and proposed ROIC circuits are fabricated using 0.18 µm complementary metal-oxide-semiconductor (CMOS) technology. The peak signal-to-noise ratio (SNR) for the traditional ROIC is 40.9 dB, while the peak signal-to-noise and distortion ratio (SNDR) is measured at 40.1 dB. In contrast, the proposed ROIC, which incorporates the SAR ADC, achieves a peak SNR of 54.6 dB and a peak SNDR of 51.8 dB, demonstrating a significant improvement in linearity. The new ROIC consumes 39.5 µA of current from a 1.8 V power supply and occupies a chip core area of only 0.27 mm².

1. Introduction

Intracranial pressure (ICP) monitoring is a critical diagnostic tool for managing traumatic brain injury (TBI), subarachnoid hemorrhage (SAH), hydrocephalus, and other neurological conditions [1]. Current clinical standards define normal adult ICP as 5–15 mmHg, with pediatric ranges slightly lower (3.5–7.5 mmHg) [2,3]. Accurate ICP measurement is vital for timely intervention, yet existing methodologies face significant trade-offs in precision, invasiveness, and power efficiency [4,5,6,7,8,9,10].

Figure 1 provides a conceptual representation of a deep implant situated within the brain of a TBI patient, enabling precise and long-term monitoring of ICP. State-of-the-art ICP monitoring systems primarily employ three sensor types: strain gauges, fiber optic sensors, and piezoresistive Wheatstone bridge-based sensors [11]. Strain gauges, while cost-effective and widely used, suffer from temperature sensitivity and long-term drift, limiting their reliability in continuous monitoring. Fiber optic sensors offer high accuracy and immunity to electromagnetic interference but require complex fabrication and specialized readout systems, increasing cost and restricting miniaturization (see

Table 1. Comparative Analysis of ICP Monitoring Technologies.

Technology	Accuracy	Power Consumption	Size	Complexity	Long-Term Stability
Strain Gauges	Moderate	Low	Large	Low	Poor
Fiber Optic Sensors	High	Moderate	Medium	High	Excellent
Piezoresistive Sensors	High	High	Small	Moderate	Moderate

). Piezoresistive sensors, configured in Wheatstone bridges, strike a balance between size and precision, making them a preferred choice for implantable systems [12,13,14,15,16,17].

Figure 2 depicts a traditional bridge sensor readout system, referred to as the bridge-to-digital converter (BDC). The resistors R₁ and R₂, shown within the black dashed box, are piezoresistive sensors that are closely matched to two external resistors of 2.5 KΩ to minimize offset error and establish a Wheatstone bridge configuration. The resistance of the piezoresistive sensors varies with ICP, and this variation is combined with a matching resistor to generate a differential voltage signal based on the principle of voltage division. This signal is then processed by the instrumentation amplifier (IA) and digitized by the Analog-to-Digital converter (ADC), converting the ICP signal into an observable digital format [18,19,20,21].

To achieve energy-efficient amplification of bridge sensor signals, the IA must exhibit ultra-low noise, offset, and power consumption while maintaining precision [22]. Even with optimized IA and ADC performance, signal distortion persists at their interface due to loading effects and switching noise from ADC sampling networks [23]. Although chopper-stabilized capacitively coupled IAs (CCIAs) improve precision by blocking VCM through input capacitors [24], they introduce output ripple requiring auxiliary ripple reduction circuits, thereby increasing power, area, and design complexity [25]. These limitations have driven recent efforts to co-design IA with successive approximation register (SAR) ADCs, leveraging the latter’s inherent low-power advantages while addressing interface-level signal integrity challenges.

This work introduces a sample isolation-based readout integrated circuit (ROIC) that combines a cross-connection IA with an innovative SAR ADC architecture to address critical challenges in ICP monitoring systems. The proposed design achieves advancements through three interconnected innovations. First, the sample isolation technology decouples the IA output from the ADC’s sampling network, eliminating switching noise and harmonic distortion without relying on additional ripple reduction circuits. Second, the cross-connection IA enhances power efficiency and gains accuracy while minimizing input-referred noise, a crucial feature for low-power implantable applications. Third, the isolation structure leverages intrinsic device matching to mitigate coefficient variations, thereby removing the need for trimming circuits and reducing chip area. Together, these innovations enable a compact, energy-efficient solution that maintains signal integrity and precision, addressing the limitations of conventional Wheatstone bridge-based ROICs in ICP monitoring.

This paper is organized as follows. Section 2 introduces the proposed sampling isolation system scheme. Section 3 describes in detail the designed cross-connection IA and sampled-data isolation-based SAR ADC. Section 4 provides measurement results obtained from two different ROIC chips to validate the performance of the proposed structure. The conclusions are presented in Section 5.

2. System Design of the ROIC

The ROIC comprises an IA and a SAR ADC, where signal distortion frequently arises at the interface between these two circuits. Figure 3a illustrates the ROIC utilizing a conventional SAR ADC. The sampling frequency, denoted as Clk_s, of the SAR ADC is configured to be either two or five times the analog input frequency, f_IN. Typically, IAs are not engineered to drive ADC inputs, primarily due to their insufficient linearity, which is essential for high-resolution ADC performance. Linearity, or total harmonic distortion (THD), is often the most significant limiting factor, rendering IAs incapable of directly driving the ADC. When complex waveforms are digitized, any distortion introduced can obscure the original signals, leading to corrupted data. Additionally, significant peaks are generated at the Va node [26,27,28].

Alternatively, these large residual peaks can be eliminated by using an active low-pass filter, which also helps to reduce out-of-band noise and improve signal-to-noise ratio (SNR), although this is not its primary function. However, this approach also adds complexity to the circuit design, requiring a trade-off between the greater isolation caused by this current injection and the degradation in build-up time performance caused by a low-pass filter formed in this way [29,30].

Another strategy involves incorporating a single-pole RC filter between the IA and the SAR ADC. This configuration allows the RC network to restrict the bandwidth of the incoming signal, thereby minimizing the noise transmitted from the amplifier and the preceding circuitry to the ADC. Nonetheless, excessive bandwidth limitation can lead to increased settling times and signal distortion. Consequently, the output voltage from the preamplifier retains high quality while also achieving lower power consumption in comparison to a scenario in which the IA is directly interfaced with the SAR ADC. The RC filter effectively reduces the amount of out-of-band noise that flows into the ADC input and aids in dampening transients from the switched capacitors at the ADC input. Therefore, the integration of an RC filter with the IA-SAR ADC interface necessitates a careful balance between noise suppression, settling time constraints, and power efficiency, as demonstrated in the subsequent analysis of component trade-offs [31,32].

Figure 3b shows the ROIC using a conventional SAR ADC with an RC filter. Capacitor C_FILT helps to mitigate the step change in amplifier output voltage caused by this current step, but the amplifier is still subject to its interference and needs to be built up in time before the end of the acquisition cycle. Resistor R_FILT isolates the driver from C_FILT and reduces its effect on stability when driving large capacitors.

Some factors need to be considered regarding the choice of R_FILT and C_FILT values. C_FILT acts as a charge bucket for the input charge backlash, minimizing the voltage step and thus improving the build-up time. Too large may affect amplifier stability and may drop the LPF roll-off frequency too low to allow signals to pass through, and too small results in too much charge backlash at the ADC input to build up in time. R_FILT provides isolation between the amplifier output and C_FILT to ensure stability. Too large may make the build-up time constant too long. It may also result in an elevated THD when accounting for the ADC input nonlinear impedance. The C_FILT is too small, and the amplifier may become unstable, or its forward path buildup may be compromised.

We propose an application of an ROIC based on a sampling isolation technique as shown in Figure 3c. The input signal shown is connected to the bootstrapped switch in the SAR ADC through the sample isolation module, and the SAR ADC is connected to the output of the IA through the sample isolation module. The sample isolation technique effectively isolates DC and low-frequency noise between the instrumentation amplifier and the ADC. The isolation circuitry reduces the impact of noise on the entire signal link, thus improving the signal integrity and measurement accuracy of the system. The use of isolation techniques such as optical or magnetic coupling reduces the noise and interference introduced by the ground loop. This helps to improve the noise performance of the system, especially in the case of high-precision measurements and low noise requirements. Isolated sampling switches allow signals to be transmitted between different power domains or grounds, which improves system design flexibility and avoids the possibility of noise interference from multiple sources.

Figure 3c uses a sample isolation module instead of an RC filter, so the issue of how quickly the ADC input charge is stabilized in the injection transient is considered. The RC filter causes some degree of attenuation of the signal, including a reduction in signal amplitude and an increase in phase shift. This may be less desirable in some high-fidelity and high-precision applications. RC filters are susceptible to PCB layout and external electromagnetic interference, especially in high-frequency applications. Parasitic inductance and capacitance may affect the desired performance of the filter.

Sample isolation techniques are suitable for applications that require high accuracy, high immunity to interference, and the need to transmit signals between different power domains or grounds. Despite the higher cost and complexity, it may be necessary for certain mission-critical and safety-critical systems. RC filters are more suitable for cost-sensitive, simple-to-implement applications with moderate bandwidth requirements. It provides a cost-effective noise suppression solution and is a common tool in many economical measurement and data acquisition systems.

3. ROIC Implementation Details

A basic circuit diagram for the suggested ROIC is presented in Figure 3. This diagram includes an IA utilizing a cross-connection approach along with a sampled-data isolation-based SAR ADC. This section will provide an in-depth discussion of the implementation of these components.

3.1. Cross-Connection Instrumentation Amplifier Scheme

The current feedback instrumentation amplifiers (CFIAs), three-opamp configuration, and capacitive coupling topology are commonly employed in the implementation of instrumentation amplifiers (IAs) [33,34,35]. Illustrated in Figure 4 is the structure of an IA. To effectively transmit the input voltage, the IA must possess a high input impedance. While the three-opamp topology offers excellent linearity and high input impedance, it suffers from low power efficiency due to the requirement for three low-noise amplifiers. The CFIA, on the other hand, achieves a high input impedance; however, its gain accuracy is restricted by the mismatch in transconductances between the input and feedback elements, and its power efficiency is affected by the two transconductors involved [36,37,38].

In capacitively coupled topology, low-frequency signals cannot be transmitted due to the capacitor’s DC-isolating effect, resulting in a limited low-frequency response of CCIAs. Signals may be partially or completely lost in DC or low-frequency signal measurements. The input impedance of a capacitively coupled system varies with frequency, which tends to introduce loop instability. The frequency-dependent impedance of the capacitive coupling network further limits the available signal bandwidth of CCIA, as demonstrated by the 200 kHz range implemented in this work, which is more advantageous than the signal bandwidth of CCIA architecture.

Capacitively coupled circuits are susceptible to noise at both the high- and low-frequency ends. The capacitive network at the input may generate noise and distortion. The amplifier has a limited ability to handle the exact swing of the input signal. Capacitors take time to charge, and the charging time of the capacitors may cause signal delay. The charging effect of the capacitors may significantly affect the output signal when the input signal changes rapidly or when the signal changes frequently. The transient response of the signal may become slower and is not suitable for highly dynamic signal processing. Additional compensation circuitry may be required, increasing the complexity of the design. The capacitance value of the coupling capacitor and the performance of the amplifier can vary with temperature [39,40].

This is a disadvantage in some applications where high stability is required. DC drift and signal instability may lead to measurement errors. Additional measures are required to compensate for the effects caused by temperature and drift. The input network of a capacitively coupled amplifier may lead to non-linear signal distortion, especially at large input signal levels. It may also result in degradation of the linearity and accuracy of the output signal, so it is not suitable for applications requiring precise measurements and linear output.

In recent years, research has actively focused on IA structures that exhibit strong power efficiency to address the aforementioned issues. The traditional three-opamp IA has several advantages, such as common mode signal rejection, high input impedance, and precise gain. However, it is inadequate when a fully differential output signal is necessary. As advances in accuracy propel the performance of components within fully differential signal chains, one of the primary advantages is improved noise rejection, which can be influenced by signal routing. When this noise is picked up at the output, it is likely to cause common errors, which will then be further diminished within the signal chain. Moreover, it is possible to convert differential signals into single-ended signals while using signal ranges that share the same power supply. Consequently, the signal-to-noise ratio (SNR) is improved with fully differential signaling. Various methods have been explored to implement fully differential amplifiers using standard components, although each approach presents its own set of challenges [41,42], as analyzed in the following section.

One method involves employing an operational amplifier to power the reference pin while configuring the input in positive mode and positioning the negative input at the midpoint between two identical resistors that link the outputs. This setup utilizes the internal amplifier’s output as the positive signal and the output of the operational amplifier as the negative signal. Given that the outputs originate from different amplifiers, any discrepancies in dynamic performance between these devices can significantly impact the overall functionality of the circuit. Furthermore, the equality of the two resistors leads to a shift in the output common mode (CM) in tandem with the output signal, which can cause distortion. When designing this circuit, it is crucial to account for stability in selecting amplifiers, and it may be necessary to include a feedback capacitor in the operational amplifier, which restricts the circuit’s overall bandwidth. Ultimately, the gain range of the circuit relies on the capabilities of the internal amplifier, rendering a gain of less than 1 unachievable.

One alternative method involves linking two amplifiers in parallel. This setup offers an improved matching of the drive circuit and enhanced frequency response compared to earlier configurations. Nevertheless, it cannot achieve a gain lower than 2. Additionally, the circuit necessitates gain resistors that are precisely matched to accommodate a purely differential signal. Any disparity among these resistors leads to a variation in the output common-mode level, similar to the previous arrangement.

Both approaches have their limitations concerning the potential gain and the need for matching components. We have developed a fully differential output that ensures accurate gain or attenuation through a single gain resistor by cross-connecting the internal amplifiers, as illustrated in Figure 5. By linking the two reference pins, users can modify the output-sharing configuration according to their requirements.

A schematic of the designed IA is shown in Figure 5, and a schematic of the IA opamp containing the transconductance block is shown in Figure 6. The gain of the IA is defined as follows:

$${\displaystyle \frac{V_{OUT}}{V_{IN}}}=2\times \left({\displaystyle \frac{R_1}{R_2}}-{\displaystyle \frac{R_1}{R_3}}\right)\times {\displaystyle \frac{R_4}{R}}$$

(1)

In contrast to NMOS, PMOS technology exhibits reduced flicker noise due to its significantly lower likelihood of capturing and releasing carriers. Consequently, we have selected PMOS as the input device for the amplifier, necessitating an increase in the dimensions of the buffer’s input components to minimize noise levels. To mitigate noise, the PMOS input transistor in Gm1 is designed with a substantial size of 256 µm/220 nm [43]. The input-referred noise power spectral density (PSD) of the readout, not accounting for the noise from the Wheatstone bridge, can be expressed by Equation (3).

$$V_{inoise}=\sqrt{8kT\left({\displaystyle \frac{\gamma }{4g_{m1}}}+{\displaystyle \frac{R^2}{R_4}}\right)}\approx \sqrt{{\displaystyle \frac{2kT\gamma }{g_{m1}}}}$$

(2)

In 0.18-µm CMOS technology, transistors operating at 1.8 V have a $\gamma$ value of approximately 0.5. Given that $\gamma$ divided by 4 times $g_{m1}$ is much greater than the ratio of R₂ to R₄, the noise impact from R₄ is minimal in this readout circuit.

As illustrated in Figure 6, six amplifiers of cross connection IA are implemented using a basic telescopic cascode topology to minimize overall power consumption. It operates with a current of 5 µA and delivers an open loop gain exceeding 60 dB, featuring an output swing of ±600 mV while powered by a 1.8 V supply.

This proposed cross connection IA scheme offers a high degree of design flexibility, enabling customizable configuration of gain at each amplifier stage to meet the specific needs of the application.

3.2. Sample-Data Isolation Based SAR ADC

Figure 7 depicts the architecture and timing sequence of the 10-bit SAR ADC. This design features a dynamic comparator with two stages, coupled with a set of bootstrapped switches, a dual split-capacitor digital-to-analog converter (CDAC), and SAR logic. In a manner similar to a traditional monotonic SAR ADC, the ADC samples the input signal from the top plates of the capacitor arrays, while the bottom plates are linked to a reference voltage, VCM, or ground via the switch control of the DAC.

The capacitor array in a standard 10-bit SAR ADC necessitates $2^9$ capacitance units [44,45,46,47]. As shown in Figure 7, this capacitor array is categorized into two sections, parted by a bridge capacitor, which is configured as a single unit capacitor cell. A Metal-Insulator-Metal (MIM) capacitor is employed, featuring a unit capacitance of 25.12 fF.

The two sections are referred to as the Lower side (L-side) and Higher side (H-side), as illustrated in Figure 7. On the L-side, base capacitors are arranged with a capacitance ratio of 1:2:4, while on the H-side, they are arranged with a ratio of 1:2:4:8:16:32:64. Utilizing this capacitor array configuration can lead to significant power savings.

Figure 8 illustrates the schematic of the proposed bootstrapped switch. It consists of five key modules: (1) a charge-discharge module, (2) a bootstrapped module, (3) a sampling switch module, (4) a virtual switch module, and (5) a sampling isolation module.

Conventional bootstrapped switches have several limitations, such as high power consumption, switching speed limitations, insufficient drive capability, etc., which will become more obvious when high linearity is required for sampling switches in high-precision ADCs. The proposed scheme addresses these challenges by incorporating an additional transistor M₁₀ to prevent unwanted charge leakage and thus protect the switching transistors. A pair of voltage followers are used to isolate the sampling switch from the front-stage low-power analog amplifier. In the sampling switch module, transistor M₂ employs a linear bias cancellation technique to effectively reduce the parasitic capacitance and the required sampling capacitance. Besides that, this method also helps to alleviate the body effect. The sampling isolation module further enhances the circuit by isolating the ADC input from the charge injection effects on the output of the front-stage low-power analog amplifier, thereby improving the linearity of the entire sampling switching circuit.

A two-stage dynamic comparator, comprising a preamplifier and a latch, sees widespread application in SAR ADCs. Illustrated in Figure 9 is the schematic of a fully dynamic two-stage comparator employed in both the initial and subsequent stages to streamline the design process while optimizing the respective transistor sizes for varying levels of accuracy and speed. Given the minimal voltage difference at the comparator’s input, a preamplifier is essential to ensure the latch switches appropriately. During the reset phase, when Clks is low and ClksB is high, the tail current transistor M₅ is disabled, allowing M₁ and M₂ to pull the nodes VP and VN to VDD, respectively. Concurrently, the comparator outputs, OP and ON, are reset to ground. As Clks rises during the regeneration phase, M₅ is activated, and the input differential pairs M₃ and M₄ begin to charge the nodes VP and VN at a rate dictated by the input signal difference. As soon as either node approaches the threshold voltage of the latch stage’s input transistor, latch regeneration triggers, driving one output high while the other is lowered. With the rising output voltage, a positive feedback mechanism is initiated, ultimately yielding inter-rail outputs. Since the circuit draws power solely during regeneration, its average power consumption remains minimal.

The suggested ADC incorporates dynamic SAR logic, illustrated in Figure 10. Unlike the traditional method that employs flip-flops, this dynamic logic approach minimizes the number of transistors and nodes, resulting in improved speed and reduced power consumption. In this study, a basic regenerative feedback mechanism maintains the outputs P and N, guaranteeing output reliability, illustrated in Figure 11.

During the sampling phase, M₁₀ and M₁₁ reset both outputs (P and N) to a low state. Subsequently, signal D is elevated to a high level while CLK is grounded. At the same time, signals P and N capture the outputs of the comparator, ON and OP, due to the regenerative feedback provided by M₁₂ and M₁₃. As soon as the falling edge of VALID is reached, signal Q is charged to VDD, signifying the completion of this operation, which transitions into signal D for the subsequent dynamic logic. To ensure that signals ON and OP remain latched, even if the comparator outputs alter later, M₁₄ and M₁₅ are deployed.

4. Measurement Results

The micrograph of the die for the test chip is depicted in Figure 12. Realized in 0.18 µm CMOS technology, the suggested ROIC covers a core area of 0.27 mm². The printed circuit board (PCB) has been crafted to assess the functionality of the proposed IC, while the test board, along with the measurement setup, is illustrated in Figure 13.

The performance of the ROIC has been evaluated through experimental methods. Calibration data processing has been conducted using MATLAB (version R2024a, available at https://www.mathworks.com).

The ROIC’s performance is assessed when the output from the sensor is a 10 mV_pp differential sine wave. The equipment employed to assess the differential nonlinearity (DNL) and integral nonlinearity (INL) of the proposed ROIC is illustrated in Figure 14. The observed peak DNL and INL values are −0.84/+0.53 LSB and −0.85/+1.4 LSB, respectively. The DNL and INL errors are mainly caused by the random mismatch between the 25.12 fF unit capacitors. The fast Fourier transform (FFT) results of the output bitstream from the ROIC, based on 2¹² samples, are presented in Figure 15. In Figure 15a, the power spectral density (PSD) of the ROIC, measured with a standard SAR ADC, features a signal-to-noise ratio (SNR) of 40.9 dB and a signal-to-noise and distortion ratio (SNDR) of 40.1 dB. Meanwhile, Figure 15b depicts the measured PSD of the ROIC with a sampled-data isolation-based SAR ADC, which achieves an SNR of 54.6 dB and an SNDR of 51.8 dB. Figure 16 illustrates the measured SNDR in relation to varying input amplitudes. The highest recorded SNDR is 51.8 dB, and the dynamic range (DR) is no less than 50 dB.

The ROIC power breakdown results, calculated by simulation, are shown in Figure 17. The IA is still the main source of system power consumption, accounting for 94.74%, despite the low-power design technique. The power consumption of the SAR ADC is only 5.26% of Figure 17. The capacitor array and bootstrapped switch power accounts for only 11% of the total Figure 17 due to the power of the MSB sampling segmented capacitor array and hybrid switching procedure. Since more dynamic logic units are used in the SAR logic, it is still the secondary source of power in the system at 39.4%. Although the comparator uses a two-stage dynamic low-power comparator architecture, it is still the main source of power in the SAR ADC system, accounting for 49.6%. The proposed technique also paves the way for efficient medium-resolution ROIC at high sampling rates.

Table 2. Performance of the ROIC versus the state of the art.

Parameter	This Work	[37]	[40]	[41]	[42]
Architecture	IA+SAR	CFIA+DTΔΣM	CCIA+CTΔΣM	IA+SAR	RC+CTΔΣM
Process (nm)	180	700	180	350	350
Supply (V)	1.8	5	1.8	3.3	5
Power (mW)	0.071	1.35	2.16	0.201	4.3
Area (mm2)	1.35	6	0.73	2	/
BW (kHz)	200	0.004	1	200	2
SNR/SNDR (dB)	54.6/51.8	91.2 */-	-/88 *	-/50	80/-
FoMSNR (dB)	149.1(@32×)	125.9 *(@100×)	-	-	136.7(@32×)
FoMSNDR (dB)	146.3(@32×)	-	144.7 *(@100×)	139.9(@178×)	-

* Estimated value.

summarizes and compares the performance metrics of the proposed ROIC design against alternative ROIC configurations documented in recent literature. Despite inherent variations in signal bandwidth specifications and target applications across these systems, this study focuses on ROIC architectures that incorporate distinct structural combinations, carefully selected to represent both conventional and emerging design paradigms. To establish a standardized framework for cross-configuration analysis, we employ two widely recognized figures of merit: FoM_SNR and FoM_SNDR.

$$Fo{M}_{SNR}=SN{R}_{dB}+10log\left({\displaystyle \frac{BW}{Power}}\right)$$

(3)

$$Fo{M}_{SNDR}=SND{R}_{dB}+10log\left({\displaystyle \frac{BW}{Power}}\right)$$

(4)

The determined FoM_SNR and FoM_SNDR values were found to be 149.1 dB and 146.3 dB, respectively. As the gain setting for the preamplifier rises, designing a high-resolution circuit poses greater challenges. In reference [40], the reported FoM_SNR values show a close resemblance to those presented in this research. We clarified that the signal-to-noise ratio reported in [40] is derived from the FoM_SNDR and AC measurements. These estimates pertain to a preamplifier gain of 100 and a conversion time of 200 ms. Furthermore, the FoM_SNDR attained through this study exceeds those of [37,40,41,42].

Research [40] demonstrates a commendable FoM_SNDR of 144.7 dB, associated with high power consumption. However, in this analysis, the peak SNDR surpasses that of [40] by 1.3 dB. Achieving a high-resolution circuit necessitates a more extensive focus on mitigating various forms of noise, including thermal noise and 1/f noise. To specifically address 1/f noise, it is essential to utilize transistors with significantly larger dimensions. However, utilizing these larger transistors leads to an increase in parasitic capacitors, which in turn slows down circuit performance; thus, higher currents become necessary to restore circuit speed. As a result, developing low-power designs proves to be challenging. Our methodology can effectively manage signal bandwidths considerably broader than those in [40], and the IA gain settings are found to be quite reasonable. The forest modulation values produced by the proposed ROIC circuit appear promising when high SNDR and signal bandwidth are both taken into account.

The ROIC developed in [41] features a bandwidth comparable to that presented in this paper, achieving an SNDR of 50 dB and a FoM_SNDR of 137.8 dB with an IA gain of 178 (equivalent to 45 dB). In contrast, our design demonstrates superior SNDR and FoM_SNDR compared to those in [37,40,41,42], even though it operates with a significantly reduced gain of 32.

5. Conclusions

This paper presents a proposed ROIC that integrates a cross-connection IA with a sampled-data isolation-based SAR ADC. This configuration enables high-resolution performance while effectively mitigating signal distortion that could arise at the interface between the IA and the SAR ADC. The sampled-data isolation SAR ADC markedly lowers the loading capacitance and switching noise at the output of the IA in comparison to traditional SAR ADCs. The developed ROIC is capable of achieving a peak SNR of 54.6 dB and a peak SNDR of 51.8 dB, for a signal bandwidth of 300 Hz, with a total power consumption of merely 71 µW. Fabricated using a 0.18 µm CMOS process, the ROIC chip occupies an area of 1.35 mm². This energy-efficient bridge readout IC is expected to find applications in intracranial pressure monitoring.