Inner-Loop Controllers for Grid-Forming Converters

Abstract

This paper presents a detailed discrete-time implementation of an inner-loop voltage controller with a current limiter for grid-forming converters with an LC filter connected to the grid. The proposed approach utilizes a state feedback control law that depends on the states of both the converter and the internal model controller. Additionally, a resonant controller is designed to accurately track the fundamental frequency of the grid voltage. The stability of the proposed controller is analyzed for both virtual impedance and virtual admittance implementations. To validate the controller’s effectiveness, simulation results are provided using a Hardware-in-the-Loop (HIL) setup, alongside a comparison of different virtual impedance implementations.

1. Introduction

Microgrids can be defined as a group of interconnected loads and distributed energy resources (DERs) with clearly defined electrical boundaries that operate as a single controllable entity relative to the grid. They can be connected to and disconnected from the grid to enable operation in grid-connected or islanded modes. At the interface between the microgrid and the main distribution network lies the Point of Common Coupling (PCC). The connection and disconnection commands are typically issued by the Microgrid Central Controller (MGCC). There are different alternatives for implementing microgrid control systems, but the most common is the centralized approach, where the MGCC commands the PCC circuit breaker, dispatches the DERs, and manages controllable loads [1]. An example of a microgrid is shown in Figure 1.

In this case, the Utility Company exchanges information with the microgrid through the MGCC. The MGCC is responsible for dispatching the DERs within the microgrid, considering criteria such as power quality and economic or environmental factors. Additionally, it manages the transitions between grid-connected and islanded modes. In islanded mode, the MGCC provides the set-points for the DERs to restore the microgrid’s voltage and frequency to their nominal values. This can be understood as secondary control. Since the MGCC communicates with the DERs and controllable loads via a low-bandwidth communication channel, in islanded mode, at least one DER must control the microgrid’s voltage and frequency in response to sudden load changes. When a DER is responsible for controlling the microgrid’s voltage and frequency, a mechanism for sharing active and reactive power among them is required. Traditional synchronous generators have an inherent power-sharing mechanism. However, inverter-based DERs must be properly controlled to incorporate this functionality, which can be understood as primary control. DERs such as wind and solar power are integrated into the grid via converters, whose behavior is primarily dictated by their primary control mechanisms, in contrast to the classical synchronous machines [1]. Two primary approaches for controlling inverter-based distributed energy resources are the grid-following and grid-forming modes [2,3,4].

1.1. Grid-Following Converters

Most inverters used in photovoltaic (PV) systems and wind turbines currently operate in grid-following mode (Figure 2). This mode employs an inner current loop to ensure that the grid-side currents track their references and a synchronization algorithm to estimate the angular position $\mathsf{\theta }$ and frequency $\mathsf{\omega }$ of the voltage at the point of connection (PoC) [5]. Typically, the current references are generated to ensure the desired exchange of active and reactive power with the grid. For example, the active power reference $p^{*}$ may originate from the DC bus voltage outer loop, while also incorporating frequency support actions. The reactive power reference $q^{*}$, conversely, can be derived from grid-supporting functionalities, such as voltage-reactive power characteristics or from an external signal provided by the Microgrid Control System (MGCS) [6].

While grid-following converters are currently prevalent in the integration of diverse inverter-based resources into the grid, a growing trend favors grid-forming converters due to their potential to enhance grid stability and resilience. The subsequent sections of this paper will detail a systematic design methodology for the inner-loop controller, as well as provide a comparative analysis of virtual impedance and virtual admittance implementations.

1.2. Grid-Forming Converters

Grid-forming inverters, by contrast, are designed with an inner control loop to synthesize either voltage or current at the DER PoC (Figure 3). The voltage reference e is determined by a primary controller and may also incorporate virtual impedance. As a result, the inverter can be modeled as an ideal voltage or current source behind an impedance [7] or admittance [8], respectively. Controllers for grid-forming inverters can be implemented in both synchronous and stationary reference frames, allowing for versatile design and analysis. Stability assessments and controller designs are performed in either the continuous-time or discrete-time domains. With the advent of cost-effective, high-performance microcontrollers and Digital Signal Processors (DSPs), discrete-time implementation has become predominant.

1.3. Inner-Loop Controllers

The need for standards in microgrid control is related to the new grid codes that are expected to appear in the next future. In this sense, the ISA-95 standard [9] deals with the integration enterprise and control systems. Each level has the duty of the command level and provides supervisory control over lower-level systems. In this sense, it is necessary to ensure that the command and reference signals from one level to the lower levels will have a low impact on the system’s stability and robustness performance. Thus, the bandwidth must be decreased when increasing the control level [10].

In order to adapt ISA-95 to the control of a microgrid, zero to three levels can be adopted as follows [11]:

• Level 3 (tertiary control): This energy production level controls the power flow between the microgrid and the grid.
• Level 2 (secondary control): This ensures that the electrical levels into the microgrid are inside the required values. In addition, it can include a synchronization control loop to seamlessly connect or disconnect the microgrid to the distribution system.
• Level 1 (primary control): The Droop control method is often used in this level to emulate physical behaviors that makes the system stable and more damped. It can include a virtual impedance control loop to emulate physical output impedance.
• Level 0 (inner control loops): Regulation issues of each module are integrated in this level. Current and voltage, feedback and feedforward, and linear and nonlinear control loops can be performed to regulate the output voltage and to control the current, while maintaining the system stable.

Various control methodologies are employed for inner-loop current regulation in inverters [12,13,14,15,16], including resonant controllers [17], Proportional–Integral (PI) controllers [18], repetitive controllers [19], dead-beat controllers [20], and Model Predictive Control (MPC) [21]. While dead-beat and MPC strategies are inherently discrete-time in nature, resonant, repetitive, and PI controllers can be designed in both continuous and discrete domains. Given the DSP-based implementation of control algorithms, adopting a discrete-time representation of the plant model is often advantageous.

1.4. Virtual Impedance

Virtual inductors have been used in inverter-based distributed energy resources to emulate the stator output impedance of conventional synchronous generators [6]. This is because high-frequency PWM (Pulse-Width Modulation) inverters typically require a small output filter to attenuate high-frequency harmonics and do not exhibit significant impedance at the nominal grid frequency. As a result, the feeder impedance becomes crucial for reactive power sharing among parallel DERs. To address this limitation, virtual impedance can be employed, allowing the inverter’s output impedance to be made resistive, capacitive, or inductive, as desired.

Since legacy power systems operate with inductive feeders, which have a strong relationship between active power frequency and reactive power voltage, it is reasonable to expect a trend toward the adoption of predominantly inductive virtual impedance. Furthermore, using virtual impedance in inverter-based DERs reduces the parameter sensitivity of microgrids to feeder impedance variations. Different virtual impedance implementations can be characterized, including through the Thevenin equivalent (or Theorem—Figure 4) or the Norton equivalent (Figure 5) and the relation between them [8].

Recent research has explored enhancements to inner-loop controllers for grid-forming inverters by leveraging virtual impedance and admittance concepts. In the context of current limiting, research on grid-forming inverters emphasizes the use of virtual impedance [7]. Advanced strategies, such as adaptive transient virtual impedance control [22], have been proposed for both balanced [23] and unbalanced faults [24]. Similarly, the emulation of inertia and grid impedance as a means of assessing and improving the stability of grid-forming converters has been explored, emphasizing the critical interaction between inverters and the grid [25]. On the other hand, virtual admittance has been used for designing recent grid-forming converters’ inner controllers aimed at current limiting [26]. The virtual resistance is adjusted to limit instantaneous overcurrent, while the virtual inductance is increased during the short circuit to maintain sinusoidal short-circuit currents [27]. An enhanced design that incorporates hybrid synchronization and virtual admittance loops to optimize system performance and robustness has also been introduced [28]. These advancements underscore the significance of virtual impedance and admittance-based approaches in addressing the challenges of stability and fault management in power grids dominated by renewable energy sources. Nevertheless, no direct comparison is made between virtual impedance and admittance.

The integration of machine learning techniques into controller design for power electronic converters has garnered significant attention due to their rapid feedforward capabilities, compatibility with black-box models, and proficiency in function approximation. To address the stability challenges arising from the operational scenario-dependent small-signal dynamics of grid-following converters, the Easy Transfer Reinforcement Learning (ETRL) method, as presented in [29], leverages transfer learning and deep reinforcement learning to adapt a multi-objective controller designed for one converter to others with varying system parameters. Furthermore, a Physics-Informed Deep Transfer Reinforcement Learning (PIDTRL) approach for power balance control and triple phase shift modulation in Input-Series Output-Parallel Dual-Active Bridge (ISOP-DAB) converter-based auxiliary power modules for electric aircraft is proposed in [30]. This approach demonstrates the capability to adaptively determine optimal modulation variable combinations in stochastic and uncertain environments, circumventing the need for precise model information. Experimental results validate the effectiveness of the PIDTRL-based algorithm, showcasing its potential to enhance controller adaptability, minimize experimental data requirements, and ensure stable converter operation across diverse conditions. While transfer learning exhibits promising potential, its application in power electronics control remains relatively nascent, necessitating further exploration and addressing the demand for increased computational processing capacity.

The main contributions of this paper are twofold: first, to present a novel and detailed discrete-time implementation of an inner-loop voltage controller with an integrated current limiter for grid-forming converters equipped with an LC filter connected to the grid; second, to provide a comprehensive comparison between virtual impedance and virtual admittance implementations. The stability of the proposed controller, incorporating virtual impedance, is thoroughly analyzed. For the virtual admittance implementation, a similar current controller is employed to ensure a fair performance comparison.

The remainder of the paper is structured as follows. Section 2 describes the methodology for developing the proposed inner-loop voltage controller and its variations based on virtual impedance and virtual admittance. Section 3 presents the results obtained from the implementation of the proposed controller. Finally, Section 4 concludes the paper and provides a discussion of the results.

2. Materials and Methods

This section outlines the methodology for developing the proposed inner-loop voltage controller, which incorporates a current limiter and is designed for use with an LC filter connected to the grid. The stability of the proposed controller is thoroughly analyzed, taking into account the integration of virtual impedance. For the implementation of virtual admittance, a comparable current controller is utilized to facilitate a performance comparison between the two approaches.

2.1. Proposed Inner-Loop Voltage Controller with Current Limiter

The proposed inner-loop voltage controller with a current limiter is designed to achieve four primary objectives:

• Minimize the output voltage tracking error;
• Limit the inverter current during transients and short circuits;
• Implement the desired inverter output impedance characteristics;
• Attenuate the resonance frequency of the inverter’s LC filter.

The circuit of a single-phase inverter is presented in Figure 6.

In a digital control system, electrical variables are sampled using analog-to-digital converters, and the control calculations are executed by a microcontroller. The control signals are then compared with a triangular carrier to generate the PWM signals, introducing a one-sample time delay into the system [6]. Considering the single-phase circuit on Figure 6, a discrete-time state–space model with a sampling time of $T_s$, including the one-sample delay resulting from the digital implementation, is given by (1), and is rewritten in the compact form in (2). The switching effects of the PWM and its nonlinearity are neglected, so the control action $u_k$ is assumed to represent the voltage synthesized by the converter.

$$\left[\begin{array}{c}{i_L}_{k+1}\\ {v_c}_{k+1}\\ {u_d}_{k+1}\end{array}\right]=\left[\begin{array}{ccc}1& -{\displaystyle \frac{T_s}{L}}& {\displaystyle \frac{T_s}{L}}\\ {\displaystyle \frac{T_s}{C}}& 1& 0\\ 0& 0& 0\end{array}\right]\left[\begin{array}{c}{i_L}_k\\ {v_c}_k\\ {u_d}_k\end{array}\right]+\left[\begin{array}{c}0\\ 0\\ 1\end{array}\right]u_k+\left[\begin{array}{c}0\\ -{\displaystyle \frac{T_s}{C}}\\ 0\end{array}\right]i_{ok}$$

(1)

$${\mathbf{x}}_{k+1}={\mathbf{G}}_i{\mathbf{x}}_k+{\mathbf{h}}_i{u}_k+{\mathbf{f}}_i{i}_{ok}$$

(2)

2.1.1. Current Limiter Design

For the current limiter design, the current condition is represented by a load resistance $R_L$. The discrete-time model presented in (1) and (2) is then rewritten in (3) and (4), with the block diagram of the current loop controller shown in Figure 7.

$$\left[\begin{array}{c}{i_L}_{k+1}\\ {v_c}_{k+1}\\ {u_d}_{k+1}\end{array}\right]=\left[\begin{array}{ccc}1& -{\displaystyle \frac{T_s}{L}}& {\displaystyle \frac{T_s}{L}}\\ {\displaystyle \frac{T_s}{C}}& 1-{\displaystyle \frac{T_s}{R_{L}C}}& 0\\ 0& 0& 0\end{array}\right]\left[\begin{array}{c}{i_L}_k\\ {v_c}_k\\ {u_d}_k\end{array}\right]+\left[\begin{array}{c}0\\ 0\\ 1\end{array}\right]u_k$$

(3)

$${\mathbf{x}}_{k+1}={\mathbf{G}}_{ic}{\mathbf{x}}_k+{\mathbf{h}}_i{u}_k$$

(4)

Under short-circuit conditions, the plant model order is reduced since the capacitor voltage $v_c$ in parallel with the resistance $R_L$ approaches zero. This simplified discrete-time model is presented in (5) and is rewritten in the compact form in (6).

$$\left[\begin{array}{c}{i_L}_{k+1}\\ {u_d}_{k+1}\end{array}\right]=\left[\begin{array}{cc}1& {\displaystyle \frac{T_s}{L}}\\ 0& 0\end{array}\right]\left[\begin{array}{c}{i_L}_k\\ {u_d}_k\end{array}\right]+\left[\begin{array}{c}0\\ 1\end{array}\right]u_k$$

(5)

$${\mathbf{x}}_{sck+1}={\mathbf{G}}_{isc}{\mathbf{x}}_{sck}+{\mathbf{h}}_{isc}{u}_k$$

(6)

To implement a state feedback controller, the state feedback gain ${\mathbf{k}}_i$ must be determined. This can be achieved using the Discrete Linear Quadratic Regulator (DLQR). The DLQR is an optimal control design method that minimizes the cost function J. The optimal gains are obtained by recursively solving the Algebraic Riccati Equation, which guarantees system stability under nominal conditions, provided the matrices $\mathbf{Q}$ and $\mathbf{R}$ are positive and the system is controllable. Increasing $\mathbf{Q}$ results in a faster response, while increasing $\mathbf{R}$ reduces the control effort. The cost function is minimized as shown in (7).

$$u_k=-{\mathbf{k}}_i{\mathbf{x}}_{sck}+k_r{i}_{refk}$$

(7)

The cost function is minimized with the gains given by (8), which are obtained from the solution of the discrete Riccati equation in (9).

$$\mathbf{k}={\left(r+{\mathbf{B}}^T\mathbf{PB}\right)}^{-1}{\mathbf{B}}^T\mathbf{PA}$$

(8)

$${\mathbf{P}}_{k+1}=\mathbf{Q}+{\mathbf{A}}^T\mathbf{PA}-{\mathbf{A}}^T{\mathbf{P}}_k\mathbf{B}{\left(r+{\mathbf{B}}^T{\mathbf{P}}_k{\mathbf{B}}^T\right)}^{-1}{\mathbf{B}}^T{\mathbf{P}}_k\mathbf{A}$$

(9)

where ${\mathbf{P}}_0=0$ and $\mathbf{A}$ and $\mathbf{B}$ are the matrices of the state–space model of the plant with a resonant controller. Specialized routines, such as the DLQR function in Matlab, can provide the gain ${\mathbf{k}}_i$ based on the knowledge of the matrices ${\mathbf{G}}_{\mathbf{isc}}$ and ${\mathbf{h}}_{\mathbf{isc}}$ (6), as well as the choice of the weighting matrices $\mathbf{Q}$ and $\mathbf{R}$.

Considering the parameters of the project presented in

Table 1. Parameters of the controller design.

Parameter	Description	Value
S	rated power of the inverter	33 kVA
V	rated voltage of the inverter	220 VRMS
L	inductance of the output filter	0.25 m
C	capacitance of the output filter	$100\mathsf{\mu }\mathrm{F}$
${\mathrm{T}}_s$	sampling rate	$50\mathsf{\mu }\mathrm{s}$

, $\mathbf{Q}=\mathrm{diag}\left(\left[\begin{array}{cc}1000& 1\end{array}\right]\right)$ and $\mathbf{R}=1$ as the weighting matrices of the DLQR, it is observed that the current gain converges to 5, while the one-sample delay gain converges to 1 (${\mathbf{k}}_i={\left[\begin{array}{cc}5& 1\end{array}\right]}^{\mathrm{T}}$).

When the model that includes the capacitor, represented by the matrices ${\mathbf{G}}_{\mathbf{ic}}$ and ${\mathbf{h}}_{\mathbf{i}}$ (4), is used, and instead of a short circuit, a resistor representing three times the rated power of the inverter is considered, the current and one-sample delay gains remain close to those obtained previously. Finally, the gain $k_r$ is adjusted such that the rated current error becomes zero under rated power conditions of the inverter ($k_r=8$).

2.1.2. Voltage Controller Design

Considering the single-phase circuit shown in Figure 4, a discrete-time state–space model with a sampling time of $T_s$, including the one-sample delay resulting from the digital implementation for the output voltage controller, is given by (10) and is rewritten in the compact form in (11).

$$\left[\begin{array}{c}{i_L}_{k+1}\\ {v_c}_{k+1}\\ {u_d}_{k+1}\end{array}\right]=\left[\begin{array}{ccc}1& -{\displaystyle \frac{T_s}{L}}& {\displaystyle \frac{T_s}{L}}\\ {\displaystyle \frac{T_s}{C}}& 1& 0\\ -k_{i1}& 0& -k_{i2}\end{array}\right]\left[\begin{array}{c}{i_L}_k\\ {v_c}_k\\ {u_d}_k\end{array}\right]+\left[\begin{array}{c}0\\ 0\\ k_r\end{array}\right]i_{refk}+\left[\begin{array}{c}0\\ -{\displaystyle \frac{T_s}{C}}\\ 0\end{array}\right]i_{ok}$$

(10)

$$y_k=\left[\begin{array}{ccc}0& 1& 0\end{array}\right]\left[\begin{array}{c}{i_L}_k\\ {v_c}_k\\ {u_d}_k\end{array}\right]$$

$$\begin{array}{cc}\hfill {\mathbf{x}}_{k+1}& ={\mathbf{G}}_v{\mathbf{x}}_k+{\mathbf{h}}_v{i}_{refk}+{\mathbf{f}}_v{i}_{ok}\hfill \\ \hfill y_k& ={\mathbf{c}}_v{\mathbf{x}}_k\hfill \end{array}$$

(11)

where ${\mathbf{G}}_v={\mathbf{G}}_i-{\mathbf{h}}_i{\mathbf{k}}_i$ and ${\mathbf{k}}_i={\left[\begin{array}{ccc}{\mathbf{k}}_{i1}& 0& {\mathbf{k}}_{i2}\end{array}\right]}^{\mathrm{T}}$.

The resonant controller is designed to track the fundamental frequency of the grid voltage, and its discrete-time representation can be expressed by Equation (12).

$$x_{ck+1}=\mathbf{R}{x}_{ck}+\mathbf{T}{e}_k$$

(12)

where $x_c$ is the controller state, $e_k$ is the tracking error, and the matrices $\mathbf{R}$ and $\mathbf{T}$ are given by (13) and (14).

$$\begin{array}{cc}\hfill \mathbf{R}& =\left[\begin{array}{cc}0& 1\\ -e^{-a{T}_s}& 2e^{-2a{T}_s}cos\left(\omega T_s\right)\end{array}\right]\hfill \end{array}$$

(13)

$$\begin{array}{cc}\hfill \mathbf{T}& =\left[\begin{array}{c}0\\ 1\end{array}\right]\hfill \end{array}$$

(14)

From (11) and (12), the augmented system can be expressed in its compact form as in (15).

$${\mathsf{\rho }}_{k+1}={\mathbf{G}}_a{\mathsf{\rho }}_k+{\mathbf{h}}_a{i}_{refk}+{\mathbf{f}}_{1a}{i}_{ok}+{\mathbf{f}}_{2a}{v}_{refk}$$

(15)

where

$$\begin{array}{cc}\hfill {\mathsf{\rho }}_k& =\left[\begin{array}{c}{\mathbf{x}}_k\\ {\mathbf{x}}_{ck}\end{array}\right]\hfill \end{array}$$

(16)

$$\begin{array}{ccc}& \hfill {\mathbf{G}}_a& =\left[\begin{array}{cc}{\mathbf{G}}_v& {\mathbf{0}}_{3x2}\\ -\mathbf{T}{\mathbf{c}}_v& \mathbf{R}\end{array}\right]\hfill \end{array}$$

(17)

$$\begin{array}{cc}\hfill {\mathbf{h}}_a& =\left[\begin{array}{c}{\mathbf{h}}_v\\ {\mathbf{0}}_{2x1}\end{array}\right]\hfill \end{array}$$

(18)

$$\begin{array}{cc}\hfill {\mathbf{f}}_{1a}& =\left[\begin{array}{c}{\mathbf{f}}_v\\ {\mathbf{0}}_{2x1}\end{array}\right]\hfill \end{array}$$

(19)

$$\begin{array}{cc}\hfill {\mathbf{f}}_{2a}& =\left[\begin{array}{c}{\mathbf{0}}_{3x1}\\ \mathbf{T}\end{array}\right]\hfill \end{array}$$

(20)

The block driagram of the voltage loop controller is presented in Figure 8.

If the pair (${\mathbf{G}}_a$,${\mathbf{h}}_a$) is controllable, then with (21), it is possible to define the closed-loop performance by the adequate selection of the feedback gains.

$$i_{refk}=-\left[\begin{array}{cc}{\mathbf{k}}_1& {\mathbf{k}}_2\end{array}\right]{\mathsf{\rho }}_k=-{\mathbf{k}}_1{\mathbf{x}}_k-{\mathbf{k}}_2{\mathbf{x}}_{ck}$$

(21)

To implement a state feedback controller, the state feedback gains ${\mathbf{k}}_1$ and ${\mathbf{k}}_2$ need to be determined. For this, the DLQR can once again be used. The cost function for this regulator is given by Equation (22).

$$J={\displaystyle \frac{1}{2}}\sum _{k=0}^{\infty }\left[{\mathsf{\rho }}_k^T{\mathbf{Q}\mathsf{\rho }}_k^T+i_{refk}r{i}_{refk}\right]$$

(22)

where $\mathbf{Q}$ is a positive semidefinite matrix and r is a positive scalar. The full block diagram of the proposed inner-loop voltage controller with a current limiter is presented in Figure 9.

Considering the parameters of the project presented in Table 1, $\mathbf{Q}={\mathbf{I}}_{5\times 5}$ and $\mathbf{R}=1$ as the weighting matrices of DLQR, ${\mathbf{k}}_i={\left[\begin{array}{ccc}5& 0& 1\end{array}\right]}^{\mathrm{T}}$, $k_r=8$, and $k_w=8$, the gains obtained are ${\mathbf{k}}_1={\left[\begin{array}{ccc}0.1085& 0.1149& 0.0106\end{array}\right]}^{\mathrm{T}}$ and ${\mathbf{k}}_2={\left[\begin{array}{cc}0.0251& -0.0259\end{array}\right]}^{\mathrm{T}}$.

The Bode diagram that relates the reference $v_{ref}$ and the output voltage $v_c$ is presented in Figure 10. The Bode diagram that relates the input current $I_o$ and the output voltage $v_c$ is presented in Figure 11.

2.1.3. Thevenin Equivalent for Virtual Impedance Implementation

For the Thevenin equivalent of the virtual impedance implementation, the block diagram in Figure 9 is considered. Since the continuous-time virtual impedance is non-causal, a pole must be introduced to make it causal. Any discretization method for solving ordinary differential equations can be applied; however, to simplify the state–space model, Euler’s discretization method is chosen. By applying Euler’s method with a sampling period $T_s$, the discrete-time representation is obtained in (23) and (24) and is represented in state–space form in (25) and (26).

$$\begin{array}{cc}\hfill x_{vk+1}& =(1-a_v{T}_s)x_{vk}+a_v{T}_s{i}_{Lk}\hfill \end{array}$$

(23)

$$\begin{array}{cc}\hfill v_{Lk}& =\left(R_v-a_v{L}_v\right)x_{vk}+a_v{L}_v{i}_{Lk}\hfill \end{array}$$

(24)

$$\begin{array}{cc}\hfill x_{vk+1}& =g_{vi}{x}_{vk}+h_{vi}{i}_{ok}\hfill \end{array}$$

(25)

$$\begin{array}{cc}\hfill v_{Lk}& =c_{vi}{x}_{vk}+d_{vi}{i}_{ok}\hfill \end{array}$$

(26)

2.1.4. Norton Equivalent for Virtual Admittance Implementation

For the Norton equivalent virtual admittance implementation shown in Figure 5, a current controller similar to the one proposed in this paper is used to facilitate a comparison between the Thevenin and Norton equivalent implementations. The corresponding block diagram is illustrated in Figure 12.

It is important to note that the implementation of the Norton equivalent model employs a causal transfer function, represented as an admittance. Current limitation during a short circuit can be achieved either through a conventional limiter or by employing a more advanced adaptive virtual impedance, as proposed in [27]. Using Euler’s method with a sampling period of $T_s$, the discrete-time representation is obtained as shown in (27) and (28).

$$\begin{array}{cc}\hfill x_{vk+1}& =\left(1-{\displaystyle \frac{T_s{R}_v}{L_v}}\right)x_k+{\displaystyle \frac{T_s}{L_v}}\left(E-v_c\right)\hfill \end{array}$$

(27)

$$\begin{array}{cc}\hfill i_{ref}& =x_k\hfill \end{array}$$

(28)

2.1.5. Virtual Impedance × Virtual Admittance

For comparison purposes, Figure 13 presents the virtual impedance and virtual admittance plotted at the same bode diagram. It can be observed that the magnitude and phase of the inverter with virtual impedance and admittance are similar below and around the grid nominal frequency, which in this case is 60 Hz.

Alternatively, in the high-frequency range, the phase of the virtual impedance resulting from the Thevenin equivalent decreases at a higher rate compared to the Norton equivalent implementation. This is due to the fact that the Norton equivalent implementation of the inner-loop virtual impedance has a lower order. Consequently, fewer instabilities are expected in this frequency range when connecting multiple inverter-based DERs within the same network.

3. Results

In the fields of power electronics and applied control, Test-Driven Development (TDD) has significant potential for systematically characterizing the performance of grid-tied inverter control blocks and verifying their compliance with predefined metrics. TDD, also referred to as Test-Driven Design, is a software development approach in which tests are written before the application or device under test (DUT) is designed, rather than performing validation afterward, as in traditional methods [31]. This methodology enables an iterative development process, where software is incrementally refined based on test outcomes.

Among software development methodologies, TDD can be particularly beneficial when designing and testing controllers for grid-tied converters. The fundamental principle of TDD is to execute a series of automated tests, each corresponding to a specific scenario. These scenarios are predefined by the designer and executed through supervisory software that drives the simulation. The implementations presented in this chapter have been developed using the Typhoon Test Integrated Development Environment (IDE), a framework that integrates pytest for executing tests written in Python (https://www.typhoon-hil.com/, accessed on 15 December 2024). Additionally, multiple application programming interfaces (APIs) facilitate faster and more efficient testing. Typhoon Test IDE also integrates with the Allure Framework reporting tool, providing comprehensive and interactive reports. Each scenario is systematically simulated, and the results can be collected and compared. Examples of test scenarios include structural and parametric variations in the system under simulation. Readers can refer to [6] for a comprehensive discussion of the TDD published by the authors.

To evaluate and compare the performance of the different internal controllers described in the previous subsections, a case study must be defined: a microgrid consisting of two identical DERs that share a linear resistive load, as presented in Figure 14. The Microgrid Central Controller (MGCC) sends active and reactive power set-points to the DERs. Each DER incorporates inner current loops, virtual impedance, and Droop control as primary control strategies [6]. For comparison purposes, results were obtained operating with virtual inductance (Figure 15) and virtual admittance (Figure 16). It is observed that both strategies result in similar waveforms; however, the Norton equivalent with virtual admittance shows a higher output current measurement during the 0.05 s short circuit.

4. Discussion and Conclusions

This study investigates the small-signal stability of grid-forming converters with LC filters, employing both virtual impedance (Thevenin equivalent) and virtual admittance (Norton equivalent) for voltage control and current limiting. While virtual impedance effectively stabilizes voltage during transients by emulating adjustable reactive characteristics, its steep phase drop in the high-frequency range can exacerbate instability risks in multi-inverter microgrids.

Small-signal analysis reveals that the Norton equivalent, implementing virtual admittance, demonstrates superior high-frequency phase stability compared to the Thevenin equivalent (Figure 13). This translates to enhanced resilience in scenarios involving multiple DERs, where interactions and potential resonances are heightened. Under steady-state conditions, both virtual impedance and virtual admittance control strategies demonstrate comparable performance. However, during transient short-circuit events, a discernible difference emerges (Figure 15 and Figure 16). Specifically, implementations utilizing a Norton equivalent model exhibit a tendency for increased output current. This phenomenon aligns with the fundamental principle that virtual impedance primarily modulates current output, whereas virtual admittance primarily influences voltage dynamics.

This paper introduces a flexible framework that enables the implementation of both virtual impedance and virtual admittance techniques. The optimal selection between these methods is determined by the application’s specific needs, with a focus on ensuring high-frequency stability and robust fault tolerance. Future research should investigate the impact of varying LC filter parameters on the stability margins of these control strategies to provide valuable insights for practical implementations.