Statistical Sequential Path Delay Variation Model with Lognormal Distribution for Low-Voltage Circuit

Abstract

To solve the timing uncertainty in low-voltage circuits, this paper proposes an analytical sequential path delay model based on the lognormal distribution. Unlike previous works that primarily focus on combinational logic, our model provides a complete framework for sequential elements. It decouples inter-stage correlations within flip-flops through a linear delay transformation. The model’s key innovation is a one-shot characterization approach that dramatically reduces simulation time compared to traditional Monte Carlo methods. All experiments on the TSMC 28 nm process show high accuracy, with average errors below 6% against MC. Our model demonstrates significant prediction accuracy improvements of up to 10.2X over prior art, establishing a highly efficient and accurate solution for variation-aware sequential timing analysis.

1. Introduction

The demand for ultra-low-power circuits has increased significantly in recent years. Operating with a supply voltage below the transistor’s threshold voltage offers great potential for energy savings and has thus received special attention. However, this approach introduces a major challenge. In the subthreshold region, the drive current changes exponentially with the threshold voltage (Vth). Consequently, circuits become highly sensitive to process variations. This sensitivity can lead to cell delay changes of up to 300% [1], posing significant challenges to circuit reliability.

Statistical Static Timing Analysis (SSTA) is a powerful method for accurately estimating circuit delay variations caused by on-chip process fluctuations. The most fundamental SSTA technique is the Monte Carlo (MC) simulation. MC simulation is highly accurate because it does not require simplifying assumptions about parameter distributions or gate delay models. Its precision is also independent of the number of variables or circuit size. For these reasons, MC simulation is considered the “gold standard” for timing sign-off. However, its significant computational cost makes it too time consuming for iterative timing closure.

A key aspect of SSTA is the choice of statistical distribution to model gate delay. While various distributions, such as skew-normal and gamma, have been used to model the non-Gaussian nature of delay, the lognormal distribution is often favored in analytical models. This preference is rooted in its physical basis, as the total delay can be seen as a product of multiple independent random factors, which, by the central limit theorem in the log domain, leads to a lognormal distribution. It also offers significant analytical convenience for tasks like variance propagation. For a simple illustration, consider a delay D proportional to 1/μ and L², where mobility μ and channel length L have small, independent normal variations around their nominal values. The resulting delay D will be a product of these random variables, making its distribution skewed and well approximated by a lognormal distribution. In this work, we leverage this well-established lognormal model to develop an analytical framework for the challenging subthreshold region.

To reduce the high cost of MC simulation, several faster methods have been proposed, such as Latin hypercube sampling [2,3] and Quasi-MC sampling [4,5]. However, as technology scales and the number of process variables increases, the accuracy of these sampling-based methods diminishes. Other approaches focus on improving the delay model itself. For instance, V. Khandelwal et al. developed a second-order delay model to capture the nonlinear relationship between delay and process parameters [6,7,8,9]. Similarly, M. Vijaykumar and V. Vasudevan proposed a skew-normal delay model [10], and H. Yan et al. used an adaptive polynomial method for wide-voltage circuits [11]. Concurrently, recent algorithmic approaches continue to address skewed distributions by employing techniques like Gaussian Mixture Models (GMMs) to more accurately model non-Gaussian effects [12]. While these methods improve simulation speed and maintain accuracy, they are primarily mathematical models and offer limited circuit-level design insights.

In contrast to purely mathematical approaches, design-oriented SSTA models are derived from fundamental device physics. This approach was explored by J. Shiomi et al., who modeled the correlation between adjacent gates with a constant factor [13,14]. M. Alioto et al. proposed an analytical model based on the Fanout-of-4 (FO4) inverter metric [15], which was later refined by Y. Cui et al. [16]. P. Cao et al. further advanced this area by describing the path delay as a linear combination of correlated gate delays in the near-threshold region [17]. A key advantage of these methods is their ability to estimate delay variation with minimal simulation. However, a significant limitation is that they have primarily focused on combinational logic, neglecting sequential cells.

The statistical modeling of sequential cells remains an open challenge. S. Fisher et al. proposed a delay model for sequential cells but did not consider the impact of the clock path on the propagation delay (Tcq) [18]. Other researchers have used machine learning and analytical methods to study the correlation between setup and hold times [19,20], the correlation between propagation delay and clock slope, or the interdependencies among setup, hold, and propagation delay [21,22]. The application of advanced machine learning, particularly Graph Neural Networks (GNNs), continues to be an active area of research for SSTA, with recent work focusing on balancing accuracy and runtime for non-Gaussian analysis [23]. While this body of work effectively reduces timing pessimism, it focuses on the correlation between timing parameters rather than the statistical characteristics of the delays themselves. Consequently, these models have not been extended to full sequential path analysis.

This paper addresses this gap by deriving analytical statistical delay models for both sequential cells and full sequential paths in the subthreshold region. The main contributions of this work are summarized as follows:

(1)

Stack Structure Model: We propose a statistical delay model for stack structures that considers multi-transistor threshold voltage variations, decomposing their combined effect on gate delay.

(2)

Flip-Flop Model: We model the flip-flop’s non-step input delay as a linear combination of the step delays of the current and previous gates. This approach effectively decouples the correlation between adjacent gates within the flip-flop.

(3)

Efficient Path Model: We propose a method to compute sequential path delay variance based on the PVT-independent nature of relative delay sensitivity. This allows the model to be extended to multiple PVT corners using only a single nominal SPICE simulation, significantly reducing characterization time.

The remainder of this paper is organized as follows: Section 2 describes the master-slave flip-flop structure and defines its key timing parameters. Section 3 and Section 4 derive the analytical statistical delay models for the flip-flop and the full sequential path, respectively, and present experimental results. Finally, Section 5 provides a summary of our findings.

2. Preliminaries

A master-slave flip-flop is the most commonly used flip-flop in circuits. As shown in Figure 1, in order to verify the reliability of the flip-flop, STA checks two types of timing constraints: setup time and hold time. After correctly capturing the logical value, there is a delay from the clock to the output, during which the captured value propagates to the flip-flop output, as shown in Figure 2.

The setup time is the minimum time that the input D must remain stable before the clock rising edge. For the master-slave flip-flop, the input must be propagated through I1 and I2 before the clock rising edge comes, so as to ensure that the voltage at both ends is equal when I8 is turned on; otherwise, the cross-coupled inverters I2 and I8 will stay at an incorrect value. Thus, the expression of setup time of the flip-flop is:

$$T_{setup}=T_{I1}+T_{I2}$$

(1)

The hold time is the minimum time that the input D must remain stable after the clock rising edge. The hold time is actually to ensure the data on the D pin cannot affect the data sampled by the flip-flop after the clock rising edge. Thus, I1 must be closed when the rising edge of the clock is approaching. However, since the delay of D pin to I1 and CLK to I1 are different, the data at the D pin must remain unchanged until the CLK signal reaches I1. Therefore, the expression of hold time of the flip-flop is:

$$T_{hold}=T_{I5}+T_{I6}$$

(2)

The propagation delay Tcq is the delay from the start of the clock rising edge to the output Qn of the flip-flop. The expression of Tcq can be written as:

$$T_{cq}=T_{I5}+T_{I6}+T_{I3}+T_{I4}$$

(3)

3. Statistical Delay of Flip-Flop

The proposed flip-flop is composed of a stack structure and inverter. This section first introduces the analytical models of a stack structure and inverter. Then, the statistical delay model of the flip-flop in subthreshold region is modeled under the given distribution of process variation, and the expressions of cell step delay statistics are derived. Furthermore, delay variance and maximum and minimum delays are used to describe the effect of process variation on delay.

3.1. Delay Model for Inverter

In the subthreshold region, the leakage current of NMOS is expressed as (4), where λ is the drain-induced barrier lowering (DIBL) coefficient, m is the subthreshold slope factor, Vt is the thermal voltage, µ_n is the carrier mobility, C_ox is the oxide capacitance for unit area, and V_thn is the threshold voltage of NMOS.

$$I_{sub}=I_0\cdot {\displaystyle \frac{W}{L}}\cdot e^{{\displaystyle \frac{V_{gs}-V_{thn}}{m\cdot Vt}}}\cdot e^{{\displaystyle \frac{\lambda \cdot V_{ds}}{m\cdot Vt}}}\cdot \left(1-e^{{\displaystyle \frac{-V_{ds}}{Vt}}}\right)$$

(4)

Here,

$$I_0={\mu }_n\cdot C_{ox}\cdot {\displaystyle \frac{W}{L}}\cdot \left(m-1\right)\cdot V{t}^2$$

(5)

When the step input jumps from 0 to 1, the NMOS of the inverter is discharging, and the NMOS can be equivalent to a resistance R. The equivalent circuit is shown in Figure 3, and the current through R is shown as (4).

Cell propagation delay refers to the time difference between the output voltage reaching 50%Vdd and the input voltage reaching 50%Vdd, so the expression of the resistance R and propagation delay is as follows:

$$R={\displaystyle \frac{1}{\raisebox{1ex}{$Vdd$}\!\left/ \!\raisebox{-1ex}{$2$}\right.}}\cdot {\displaystyle {\int }_{\frac{Vdd}{2}}^{Vdd}\frac{V}{I_{sub}}}dV$$

(6)

$$T_{step}=\ln 2\cdot R\cdot C_L$$

(7)

Substituting I_sub from (4) in (6), the expression of R and T_step can be written as (8) and (9):

$$R={\displaystyle \frac{2m\cdot Vt}{I_0\cdot \frac{W}{L}\cdot e^{\frac{Vdd}{m\cdot Vt}}\cdot {\lambda }^2\cdot Vdd}}\cdot \left({\displaystyle \frac{0.5\lambda \cdot Vdd+m\cdot Vt}{e^{\frac{0.5\lambda \cdot Vdd}{m\cdot Vt}}}}-{\displaystyle \frac{\lambda \cdot Vdd+m\cdot V}{e^{\frac{\lambda \cdot Vdd}{m\cdot Vt}}}}\right)\cdot e^{{\displaystyle \frac{V_{th}}{m\cdot Vt}}}$$

(8)

$$T_{step}=\ln 2\cdot {\displaystyle \frac{2\cdot mVt}{I_0\cdot \frac{W}{L}\cdot e^{\frac{Vdd}{m\cdot Vt}}\cdot {\lambda }^2\cdot Vdd}}.\left({\displaystyle \frac{0.5\lambda \cdot Vdd+m\cdot Vt}{e^{\frac{0.5\lambda \cdot Vdd}{m\cdot Vt}}}}-{\displaystyle \frac{\lambda \cdot Vdd+m\cdot V}{e^{\frac{\lambda \cdot Vdd}{m\cdot Vt}}}}\right)\cdot e^{{\displaystyle \frac{V_{th}}{m\cdot Vt}}}\cdot C_L$$

(9)

The statistical variation of the threshold voltage (Vth) is a critical design consideration. It is a well-established practice to model Vth as a normal distribution [24]. Adopting this established model, Vth~N(µ, σ), we analyze the cell delay, which consequently follows the lognormal distribution shown in (10).

$$T_{step}~LN\left({\displaystyle \frac{\mu }{m\cdot Vt}}+\ln B,{\displaystyle \frac{\sigma }{m\cdot Vt}}\right)$$

(10)

Here,

$$B=\ln 2\cdot {\displaystyle \frac{2\cdot m\cdot Vt}{I_0\cdot \frac{W}{L}\cdot e^{\frac{Vdd}{m\cdot Vt}}\cdot {\lambda }^2\cdot Vdd}}\cdot \left({\displaystyle \frac{0.5\lambda \cdot Vdd+m\cdot Vt}{e^{\frac{0.5\lambda \cdot Vdd}{m\cdot Vt}}}}-{\displaystyle \frac{\lambda \cdot Vdd+m\cdot Vt}{e^{\frac{\lambda \cdot Vdd}{m\cdot Vt}}}}\right)\cdot C_L$$

(11)

The maximum/ minimum delay can be computed by (12):

$$T{d}_{\max /\min }=e^{{\mu }_{Td}\pm 3{\sigma }_{Td}}$$

(12)

where μ_Td and σ_Td refer to the expected value and standard deviation of inverter delay, respectively, shown as (13) and (14).

$${\mu }_{Td}={\displaystyle \frac{\mu }{m\cdot Vt}}+\ln B$$

(13)

$${\sigma }_{Td}={\displaystyle \frac{\sigma }{m\cdot Vt}}$$

(14)

3.2. Delay Model for Gate with Stack Structure

In a stacked structure, transistors are connected in series to charge and discharge with the same current. The most typical stack structure is a pull-down structure with a NAND gate and a pull-up structure with a NOR gate, as shown in Figure 4a,b. Figure 4c refers a stack inverter which is often used in the flip-flop. Thus, the statistical timing model of stack inverter can be derived by the NAND gate for rise transition and the NOR gate for fall transition. The leakage current of M_U and M_L of stacks for NMOS are shown as (15)–(17), where γ is the body effect coefficient, and V_thU and V_thL are the threshold voltages of M_U and M_L.

$$I_{M_U}=A\cdot W_U\cdot e^{{\displaystyle \frac{V_g-V_X-\left(V_{thU}+\gamma \cdot V_X-\lambda \cdot \left(V-V_X\right)\right)}{m\cdot Vt}}}\cdot \left(1-e^{-{\displaystyle \frac{V-V_X}{Vt}}}\right)$$

(15)

$$I_{M_L}=A\cdot W_L\cdot e^{{\displaystyle \frac{V_g-\left(V_{thL}+\lambda \cdot V_X\right)}{m\cdot Vt}}}\cdot \left(1-e^{-{\displaystyle \frac{V_X}{Vt}}}\right)$$

(16)

$$A={\mu }_n\cdot C_{ox}\cdot \left(\left(m-1\right)/L\right)\cdot V{t}^2$$

(17)

Considering that I_MU = I_ML, V_g = Vdd, $1-e^{-{\displaystyle \raisebox{1ex}{$V_x$}\!\left/ \!\raisebox{-1ex}{$V_t$}\right.}}\approx 1$, and λV_X ≈ 0, the following can be derived:

$$W_U\cdot e^{{\displaystyle \frac{Vdd-V_X-\left(V_{thU}+\gamma \cdot V_X-\lambda \cdot V\right)}{m\cdot Vt}}}=W_L\cdot e^{{\displaystyle \frac{Vdd-V_{thL}}{m\cdot Vt}}}\cdot \left(1-e^{-{\displaystyle \frac{V_X}{Vt}}}\right)$$

(18)

Finally, V_X is derived:

$$V_X=Vt\cdot \ln \left({\displaystyle \frac{W_L\cdot {\mathrm{e}}^{\frac{V_{thL}-V_{thL}}{m\cdot Vt}}\cdot e^{\frac{\lambda \cdot V}{m\cdot Vt}}+W_L}{W_L}}\right)$$

(19)

Substituting VX in (15), the expression of R in stack structure can be written as:

$$\begin{array}{c}R={\displaystyle \frac{3Vdd}{4}}\cdot {\displaystyle \frac{1}{A\cdot W_L\cdot e^{\frac{Vdd}{m\cdot Vt}}}}\cdot e^{{\displaystyle \frac{V_{thL}}{m\cdot Vt}}}+\hfill \\ {\displaystyle \frac{2m\cdot Vt}{A\cdot W_U\cdot {\lambda }^2\cdot Vdd\cdot e^{\frac{Vdd}{m\cdot Vt}}}}\cdot \left({\displaystyle \frac{0.5\lambda \cdot Vdd+m\cdot Vt}{e^{\frac{0.5\lambda \cdot Vdd}{m\cdot Vt}}}}-{\displaystyle \frac{\lambda \cdot Vdd+m\cdot V}{e^{\frac{\lambda \cdot Vdd}{m\cdot Vt}}}}\right)\cdot e^{{\displaystyle \frac{V_{thU}}{m\cdot Vt}}}\hfill \end{array}$$

(20)

Substituting R in (7), the propagation delay is shown as:

$$T_{step}=B_1\cdot e^{{\displaystyle \frac{V_{thL}}{m\cdot Vt}}}+B_2\cdot e^{{\displaystyle \frac{V_{thU}}{m\cdot Vt}}}$$

(21)

where

$$B_1=\ln 2\cdot {\displaystyle \frac{3Vdd}{4}}\cdot {\displaystyle \frac{1}{A\cdot W_L\cdot e^{\frac{Vdd}{m\cdot Vt}}}}\cdot C_L$$

(22)

$$B_2=\ln 2\cdot {\displaystyle \frac{2m\cdot Vt}{A\cdot W_U\cdot {\lambda }^2\cdot Vdd\cdot e^{\frac{Vdd}{m\cdot Vt}}}}\cdot \left({\displaystyle \frac{0.5\lambda \cdot Vdd+m\cdot Vt}{e^{\frac{0.5\lambda \cdot Vdd}{m\cdot Vt}}}}-{\displaystyle \frac{\lambda \cdot Vdd+m\cdot Vt}{e^{\frac{\lambda \cdot Vdd}{m\cdot Vt}}}}\right)\cdot e^{{\displaystyle \frac{V_{thU}}{m\cdot Vt}}}\cdot C_L$$

(23)

Since the threshold voltage V_thL and V_thU approximately follows the normal distribution, which can be abbreviated as V_thL~N(µ₁, σ₁), V_thU~N(µ₂, σ₂), then

$$B_1\cdot e^{{\displaystyle \frac{V_{thL}}{m\cdot Vt}}}\sim LN\left({\displaystyle \frac{{\mu }_1}{m\cdot t}}+\ln B_1,{\displaystyle \frac{{\sigma }_1}{m\cdot Vt}}\right)$$

(24)

$$B_2\cdot e^{{\displaystyle \frac{V_{thL}}{m\cdot Vt}}}\sim LN\left({\displaystyle \frac{{\mu }_2}{m\cdot Vt}}+\ln B_2,{\displaystyle \frac{{\sigma }_2}{m\cdot Vt}}\right)$$

(25)

According to the properties of lognormal distribution, the variance and mean of the cell delay can be obtained as:

$$D\left(T_{step}\right)=\ln \left({\displaystyle \frac{e^{2{\mu }_1+{\sigma }_1^2}\left(e^{{\sigma }_1^2}-1\right)+e^{2{\mu }_2+{\sigma }_2^2}\left(e^{{\sigma }_2^2}-1\right)}{{\left(e^{{\mu }_1+0.5{\sigma }_1^2}+e^{{\mu }_1+0.5{\sigma }_1^2}\right)}^2}}+1\right)$$

(26)

$$E\left(T_{step}\right)=\ln \left(e^{{\mu }_1+0.5{\sigma }_1^2}+e^{{\mu }_1+0.5{\sigma }_1^2}\right)-{\displaystyle \frac{D\left(T_{step}\right)}{2}}$$

(27)

It is worth noting that our model assumes the threshold voltages of the stacked transistors are independent. In reality, a weak spatial correlation may exist. Incorporating this correlation would add a covariance term to the variance calculation, significantly increasing model complexity. We adopt the independence assumption as a practical simplification, a common practice in analytical modeling to maintain tractability. The strong agreement between our results and Monte Carlo simulations, as shown below, suggests this simplification is reasonable for the structures under study.

The maximum and minimum delay values under different voltages for stacked gates including NAND, NOR, stacked inverters for rise/fall transitions can be obtained by (12), and the results are shown in

Table 1. Maximum and minimum delays of NAND gate.

	Maximum Delay		Minimum Delay
Voltage (V)	[22,25]	This Work	[22,25]	This Work
0.3	26.2%	5.4%	29.8%	8.9%
0.27	19.8%	0.1%	21.7%	1.6%
0.25	12.7%	6.2%	18.1%	6.2%
Average	19.5%	3.9%	23.2%	5.5%
Improvement	5.0X	1.0X	4.2X	1.0X

,

Table 2. Maximum and minimum delays of NOR gate.

	Maximum Delay		Minimum Delay
Voltage (V)	[22,25]	This Work	[22,25]	This Work
0.3	16.6%	0.9%	31.8%	8.3%
0.27	15.4%	1.00%	23.2%	3.5%
0.25	12.8%	3.8%	18.7%	9.7%
Average	14.9%	1.9%	24.5%	7.1%
Improvement	7.8X	1.0X	3.4X	1.0X

,

Table 3. Maximum and minimum delays of stack inverter for rise transition.

	Maximum Delay		Minimum Delay
Voltage (V)	[22,25]	This Work	[22,25]	This Work
0.3	41.6%	5.8%	20.1%	8.0%
0.27	34.8%	0.3%	10.0%	3.5%
0.25	26.2%	6.4%	9.8%	3.9%
Average	34.2%	4.1%	13.3%	5.1%
Improvement	8.3X	1.0X	2.6X	1.0X

and

Table 4. Maximum and minimum delays of stack inverter for fall transition.

	Maximum Delay		Minimum Delay
Voltage (V)	[22,25]	This Work	[22,25]	This Work
0.3	13.9%	1.5%	31.7%	8.1%
0.27	15.6%	0.8%	24.6%	1.6%
0.25	12.7%	3.3%	19.5%	8.6%
Average	14.1%	1.8%	25.3%	6.1%
Improvement	7.8X	1.0X	4.1X	1.0X

, respectively. It can be found that the accuracy of the maximum (minimum) delay of model [22,25] degrades distinctly to 5.0X (4.2X) for the NAND gate, 7.8X (3.4X) for the NOR gate, 3X (2.6X) for the stacked inverter with rise transition, and 7.8X (4.1X) for the stacked inverter with fall transition. This demonstrates that it is much more advantageous to consider both transistor threshold variations than to consider only one transistor threshold voltage variation.

3.3. Delay Model for Flip-Flop

In this section, we derive the statistical delay model for a flip-flop, which consists of multiple logic stages. To provide a clear overview of the derivation process, the overall workflow is illustrated in Figure 5.

When the input voltage is a rising edge, the expression of the input signal V_in(t) is shown as follows, where T represents the rising transition time:

$$V_{in}(t)=\left\{\begin{array}{l}Vdd\cdot {\displaystyle \frac{t}{T}},0\le t\le T\hfill \\ Vdd,t>T\hfill \end{array}\right.$$

(28)

When the input transition time T is considered, the expression for the subthreshold current can be expressed as follows:

$$I_{sub}=\left\{\begin{array}{l}{I}_0\cdot {\displaystyle \frac{W}{L}}\cdot e^{{\displaystyle \frac{\frac{Vdd\cdot t}{T}-V_{th}}{m\cdot Vt}}},0<T<\tau \hfill \\ I_0\cdot {\displaystyle \frac{W}{L}}\cdot e^{{\displaystyle \frac{Vdd-V_{th}}{m\cdot Vt}}},t>T\hfill \end{array}\right.$$

(29)

According to the definition of delay and the capacitance charge and discharge formula, the following expression can be obtained:

$${\displaystyle \frac{Vdd}{2}}\cdot C_L={\displaystyle {\int }_0^{Td+\frac{T}{2}}{I}_{ds}}\cdot dt$$

(30)

By substituting Equation (29) into Equation (30), (31) can be obtained. After solving the integral, the propagation delay Td_i is shown as (32).

$${\displaystyle \frac{Vdd}{2}}\cdot C_L={\displaystyle {\int }_0^T{I}_0\cdot \frac{W}{L}\cdot e^{\frac{\frac{Vdd\cdot t}{T}-V_{th}}{m\cdot Vt}}\cdot dt}+{\displaystyle {\int }_T^{T{d}_i+\frac{T}{2}}{I}_0\cdot \frac{W}{L}\cdot e^{\frac{Vdd-V_{th}}{m\cdot Vt}}\cdot dt}$$

(31)

$$T{d}_i={\displaystyle \frac{Vdd\cdot C_L}{2I_0\frac{W}{L}}}\cdot e^{{\displaystyle \frac{V_{th}-Vdd}{m\cdot Vt}}}+\left({\displaystyle \frac{1}{2}}-e^{{\displaystyle \frac{-Vdd}{m\cdot Vt}}}\cdot {\displaystyle \frac{m\cdot Vt}{Vdd}}\cdot \left(e^{{\displaystyle \frac{Vdd}{m\cdot Vt}}}-1\right)\right)\cdot T$$

(32)

From the observation of (32), it can be seen that the first half of Td_i is independent of the transition time T and can be represented by Td_i⁰, and the second half is related to the transition time and can be represented by Td_i^T. Thus, Td_i can be written as the linear combination of Td_i⁰ and Td_i^T, which is shown as (33).

$$T{d}_i=T{d}_i^0+T{d}_i^T$$

(33)

Here,

$$\left\{\begin{array}{l}T{d}_i^0={\displaystyle \frac{Vdd\cdot C_L}{2I_0\frac{W}{L}}}\cdot e^{{\displaystyle \frac{V_{th}-Vdd}{m\cdot Vt}}}\hfill \\ T{d}_i^T=\left({\displaystyle \frac{1}{2}}-e^{{\displaystyle \frac{-Vdd}{m\cdot Vt}}}\cdot {\displaystyle \frac{m\cdot Vt}{Vdd}}\cdot \left(e^{{\displaystyle \frac{Vdd}{m\cdot Vt}}}-1\right)\right)\cdot T\hfill \end{array}\right.$$

(34)

It can be obtained that Td_i is a linear combination of step delay $T{d}_i^0$ and input transition time T, as shown in the following equation:

$$T{d}_i=T{d}_i^0+{\beta }_1\cdot T$$

(35)

Figure 5 shows the relationship between the input and output voltages of two adjacent gates with time. V_out,i−1 is the output of the previous gate and the input of current gate, V_out,i is the output of current gate, T_i−1 is the input transition time of previous gate, and T_i is the input transition time of current gate.

According to the capacitance charge and discharge formula and the definition of input transition time, following expression can be obtained.

$$Vdd\cdot C_L={\displaystyle {\int }_0^{T_i}{I}_0}\cdot {\displaystyle \frac{W}{L}}\cdot e^{{\displaystyle \frac{Vdd-\frac{t}{T_{i-1}}\cdot Vdd-V_{th}}{m\cdot Vt}}}\cdot e^{{\displaystyle \frac{\lambda \cdot V_{ds}}{m\cdot Vt}}}\cdot \left(1-e^{-{\displaystyle \frac{V_{ds}}{Vt}}}\right)\cdot dt$$

(36)

The step delay of the previous gate can be related to the propagation delay of the current gate.

$$T{d}_i=T{d}_i^0+{\beta }_i\cdot T{d}_{i-1}^0$$

(37)

Here $T{d}_i^0$ is the step delay of the current gate, $T{d}_{i-1}^0$ is the step delay of the previous gate, and T_di is the propagation delay of the previous gate. They can be obtained through one-time nominal SPICE simulation. Therefore, the scale factor β_i can be derived directly by Equation (38).

$${\beta }_i={\displaystyle \frac{T{d}_i-T{d}_i^0}{T{d}_{i-1}^0}}$$

(38)

The propagation delay for each stage is shown as follows:

$$\left\{\begin{array}{l}T{d}_1=T{d}_1^0\hfill \\ T{d}_2=T{d}_2^0+{\beta }_2\cdot T{d}_1^0\hfill \\ ...\hfill \\ T{d}_{i-1}=T{d}_{i-1}^0+{\beta }_{i-1}\cdot T{d}_{i-2}^0\hfill \\ T{d}_i=T{d}_i^0+{\beta }_i\cdot T{d}_{i-1}^0\hfill \end{array}\right.$$

(39)

Thus, the expression of path delay can be written as:

$$\begin{array}{c}Tp=T{d}_1+T{d}_2+...+T{d}_{i-1}+T{d}_i\\ =T{d}_i^0+{\displaystyle \sum _{j=2}^{j=i}\left(1+{\beta }_i\right)}\cdot T{d}_{j-1}^0\end{array}$$

(40)

Since each step delay distribution is independent, the delay variance of the path can be obtained as:

$$D\left(Tp\right)=D\left(T{d}_i^0\right)+{\displaystyle \sum _{j=2}^{j=i}{\left(1+{\beta }_i\right)}^2}\cdot D\left(T{d}_{j-1}^0\right)$$

(41)

According to the calculation methods of setup time, hold time, and propagation delay Tcq, as shown in Figure 6, the variance expression of setup time, hold time, and Tcq can be obtained as (42), (43), and (44).

$$D\left(T_{setup}\right)=D\left(T{d}_{I2}^0\right)+{\left(1+{\beta }_{I2}\right)}^2\cdot D\left(T{d}_{I1}^0\right)$$

(42)

$$D\left(T_{hold}\right)=D\left(T{d}_{I6}^0\right)+{\left(1+{\beta }_{I6}\right)}^2\cdot D\left(T{d}_{I6}^0\right)$$

(43)

$$\begin{array}{cc}D\left(T_{cq}\right)\hfill & =D\left(T{d}_{I4}\right)+\left(1+{\beta }_{I4}\right)\cdot D\left(T{d}_{I3}\right)\hfill \\ & +\left(1+{\beta }_{I6}\right)\cdot D\left(T{d}_{I6}\right)+\left(1+{\beta }_{I5}\right)\cdot D\left(T{d}_{I5}\right)\hfill \end{array}$$

(44)

Table 5. Error in standard deviation and maximum and minimum delays with respect to 10k runs of MC simulation of hold time under different voltages.

Voltage (V)	Standard Deviation	Maximum Delay	Minimum Delay
0.3	6.9%	6.8%	6.8%
0.27	4.1%	5.9%	6.3%
0.25	8.3%	3.5%	2.0%
Average	6.4%	5.4%	5.0%

,

Table 6. Error in standard deviation and maximum and minimum delays with respect to 10k runs of MC simulation of setup time under different voltages.

	Standard Deviation		Maximum Delay		Minimum Delay
Voltage (V)	[22,25]	This Work	[22,25]	This Work	[22,25]	This Work
0.3	55.0%	1.0%	27.0%	1.9%	24.6%	2.3%
0.27	41.8%	2.6%	22.8%	0.3%	22.2%	4.7%
0.25	28.2%	5.5%	15.5%	4.4%	17.0%	0.2%
Average	41.6%	3.0%	21.8%	2.2%	21.2%	7.2%

and

Table 7. Error in standard deviation and maximum and minimum delays with respect to 10k runs of MC simulation of propagation delay under different voltages.

	Standard Deviation		Maximum Delay		Minimum Delay
Voltage (V)	[22,25]	This Work	[22,25]	This Work	[22,25]	This Work
0.3	44.0%	4.1%	13.5%	2.2%	14.1%	0.3%
0.27	38.3%	5.9%	12.2%	2.1%	13.3%	0.5%
0.25	20.9%	2.3%	5.0%	5.5%	7.0%	3.3%
Average	34.4%	4.1%	10.2%	3.3%	11.5%	1.3%

present the error percent of the hold time, setup time, and propagation delay under different voltages. The inter-stage correlation is considered during the calculation of delay. The hold time is calculated in a similar way to that of [25]. For hold time, the error of standard deviation, maximum delay, and minimum delay are all within 7%. For setup time, the error of standard deviation, maximum delay, and minimum delay are all within 6%. For propagation delay, the error of standard deviation, maximum delay, and minimum delay are all within 5%. Compared with the threshold voltage variation of only one transistor considered in [22,25], the accuracy of the proposed method is much improved.

4. Statistical Delay Model of Sequential Path

The sequential path is composed of the combined logic path and flip-flop, as shown in Figure 7. In the previous section, we have modeled the statistical delay model of the flip-flop. In this section, we combine the statistical delay model of the flip-flop and the combination logic circuit to obtain the statistical delay model of the sequential path.

4.1. Relative Sensitivity of Step Delay

In this paper, the relative step delay relative sensitivity X_cell [15] is used to eliminate the influence of PVT on the computational complexity of step delay variance. Relative step delay sensitivity refers to the ratio of step delay sensitivity of different gates to that of reference gate which is inverter in this experiment, and its expression is shown in (45). The relationship between X_cell of each gate and PVT is shown in Figure 8. It can be seen from the simulation results that the X_cell basically remains unchanged under different PVT values.

$$X_{cell}={\displaystyle \frac{{\left(D^{1/2}/E\right)}_{T{d}_{cell}^0}}{{\left(D^{1/2}/E\right)}_{T{d}_{ref}^0}}}$$

(45)

4.2. Gate Step Delay Variance

The gate step delay variance can be expressed as:

$$\begin{array}{cc}D\left(T{d}_i^0\right)\hfill & =\left({\displaystyle \frac{D\left(T{d}_i^0\right)}{E^2\left(T{d}_i^0\right)}}\right)\cdot E^2\left(T{d}_i^0\right)\hfill \\ & =X_{cell,i}^2\cdot \left({\displaystyle \frac{D\left(T{d}_{ref}^0\right)}{E^2\left(T{d}_{ref}^0\right)}}\right)\cdot \left({\left(T{d}_i^0\right)}^2\cdot e^{0.5D\left({\displaystyle \frac{Vt{h}_i}{m\cdot Vt}}\right)}\right)\hfill \end{array}$$

(46)

X_cell is independent of PVT, the lookup table of X_cell can be obtained only by MC simulation of each cell under a set of PVT conditions, and the nominal delay of the cell and the variance of the threshold voltage can be obtained in a short simulation time.

4.3. Sequential Path Delay Variation Model

According to [26], the expression of output voltage V_out in Figure 9 can be obtained.

$$V_{out}=\left\{\begin{array}{l}{\displaystyle \frac{-m\cdot Vt}{\lambda }}\cdot \ln \left({\displaystyle \frac{K\cdot \lambda \cdot T}{Vdd\cdot C_L}}\cdot \left(e^{{\displaystyle \frac{Vdd}{m\cdot Vt\cdot T}}\cdot t}-1\right)+e^{{\displaystyle \frac{-\lambda \cdot Vdd}{m\cdot Vt}}}\right),0<t<T\hfill \\ {\displaystyle \frac{-m\cdot Vt}{\lambda }}\cdot \ln \left(e^{{\displaystyle \frac{-\lambda \cdot V_{out,T}}{m\cdot Vt}}}+{\displaystyle \frac{K\cdot \lambda \cdot e^{\frac{Vdd}{m\cdot Vt}}}{m\cdot Vt\cdot C_L}}\left(t-T\right)\right),T<t<t_{3Vt}\hfill \\ Vt\cdot \ln \left(1+\left(e^3-1\right)\cdot e^{-{\displaystyle \frac{K\cdot e^{Vdd/(m\cdot Vt)}}{Vt\cdot C_L}}}\cdot \left(t-t_{3Vt}\right)\right),t>t_{3Vt}\hfill \end{array}\right.$$

(47)

$$K=I_{0n}\cdot {\displaystyle \frac{W_n}{L}}\cdot e^{-{\displaystyle \frac{Vth}{\mathrm{m}\cdot Vt}}}$$

(48)

According to the definition of delay, that is, the time difference between the output voltage reaching 50%Vdd and the input voltage reaching 50%Vdd, as shown in (49), the calculation of delay is divided into two cases according to the case of input: (1) Under the condition of fast input, the time point of V_out = 0.5Vdd is located in region 1, as shown in Figure 8a. (2) Under the condition of slow input, the time point of V_out = 0.5Vdd is located in region 2, as shown in Figure 8b. By combining (47) and (49), the expression of delay under fast and slow inputs can be obtained, as shown in (50) and (51).

$$Td=t{|}_{V_{out}=0.5Vdd}-t{|}_{V_{in}=0.5Vdd}$$

(49)

$$\begin{array}{cc}T{d}_f\hfill & ={\displaystyle \frac{C_L\cdot m\cdot Vt}{K\cdot \lambda \cdot e^{\frac{Vdd}{m\cdot Vt}}}}\left(e^{-{\displaystyle \frac{\lambda \cdot Vdd}{2m\cdot Vt}}}-e^{-{\displaystyle \frac{\lambda \cdot Vdd}{m\cdot Vt}}}\right)+\left({\displaystyle \frac{1}{2}}-{\displaystyle \frac{m\cdot Vt}{Vdd}}\right)\cdot T\hfill \\ & =T{d}^0+\left({\displaystyle \frac{1}{2}}-{\displaystyle \frac{m\cdot Vt}{Vdd}}\right)\cdot T\hfill \end{array}$$

(50)

$$T{d}_s=\left({\displaystyle \frac{m\cdot Vt}{Vdd}}\cdot \ln \left({\displaystyle \frac{Vdd\cdot C_L}{K\cdot \lambda \cdot T}}\left(e^{-{\displaystyle \frac{\lambda \cdot Vdd}{2m\cdot Vt}}}-e^{-{\displaystyle \frac{\lambda \cdot Vdd}{m\cdot Vt}}}\right)\right)-{\displaystyle \frac{1}{2}}\right)\cdot T$$

(51)

The main sources of delay variation of the cell include (1) the variations of threshold voltage and (2) variations caused by input transition time T. These two variations come from different transistors. According to the independence principle of random variables, the delay variation of the cell can be obtained, as shown in Equation (52).

$$D\left(T{d}_{total}\right)=D\left(T{d}_{Vth}\right)+D\left(T{d}_{slew}\right)$$

(52)

Thus, under the condition of fast input, there are two variances, which are caused by the threshold voltage variation and input transition time variation, represented as D(Td_f,vth) and D(Td_f,slew), respectively. This is also true under the slow input condition, and the variances are expressed as D(Td_s,vth) and D(Td_s,slew). The expressions are shown as (53)~(56).

$$D\left(T{d}_{f,Vth}\right)=\left({\displaystyle \frac{C_L\cdot m\cdot Vt}{I_0\cdot \frac{W}{L}\cdot \lambda \cdot e^{\frac{Vdd}{m\cdot Vt}}}}\left(e^{-{\displaystyle \frac{\lambda \cdot Vdd}{2m\cdot Vt}}}-e^{-{\displaystyle \frac{\lambda \cdot Vdd}{m\cdot Vt}}}\right)\right)\cdot D\left(e^{{\displaystyle \frac{Vth}{m\cdot Vt}}}\right)$$

(53)

$$D\left(T{d}_{s,Vth}\right)={\left({\displaystyle \frac{T}{Vdd}}\right)}^2\cdot D\left(Vth\right)$$

(54)

$$D\left(T{d}_{f,slew}\right)={\left({\displaystyle \frac{1}{2}}-{\displaystyle \frac{m\cdot Vt}{Vdd}}\right)}^2\cdot D\left(T\right)$$

(55)

$$D\left(T{d}_{s,slew}\right)={\left(-{\displaystyle \frac{m\cdot Vt}{Vdd}}+{\displaystyle \frac{T{d}_s}{T}}\right)}^2\cdot D\left(T\right)$$

(56)

According to the input slew of current gate and previous gate, the delay variation can be divided into “fast and slow”, “fast and fast”, “slow and fast”, and “slow and slow” for analysis. For the case that both current gate and previous gate are slow inputs, it is only possible to occur when two cells are very large driving cells to drive very small cells, which will not occur in the actual circuit, so we only analyze the first three cases.

(1)

Fast and slow:

$$D\left(T{d}_i\right)={\left({\displaystyle \frac{T_{i-1}}{Vdd}}\right)}^2\cdot D{\left(Vth\right)}_i+{\xi }_i^2\cdot D\left(T{d}_{i-1}^0\right)$$

(57)

$${\xi }_i=-{\displaystyle \frac{m\cdot Vt}{Vdd}}\cdot {\displaystyle \frac{T_{i-1}}{T{d}_{i-1}^0}}+{\displaystyle \frac{T{d}_i}{T{d}_{i-1}^0}}$$

(58)

$$D\left(T{p}_i\right)=D\left(T{p}_{i-1}\right)+{\left({\displaystyle \frac{T_{i-1}}{Vdd}}\right)}^2\cdot D\left(Vt{h}_i\right)+\left({\xi }_i^2+2{\xi }_i\right)\cdot D\left(T{d}_{i-1}^0\right)$$

(59)

(2)

Fast and fast:

$$D\left(T{d}_i\right)=D\left(T{d}_i^0\right)+{\xi }_i^2\cdot D\left(T{d}_{i-1}^0\right)$$

(60)

$$D\left(T{p}_i\right)=D\left(T{p}_{i-1}\right)+D\left(T{d}_i^0\right)+\left({\xi }_i^2+2{\xi }_i\right)\cdot D\left(T{d}_{i-1}\right)$$

(61)

(3)

Slow and fast:

$$D\left(T{d}_i\right)=D\left(T{d}_i^0\right)+{\xi }_i^2\cdot D\left(T{d}_{i-2}^0\right)$$

(62)

$$D\left(T{p}_i\right)=D\left(T{p}_{i-1}\right)+D\left(T{d}_i^0\right)+\left(2\left(1+{\xi }_{i-1}\right){\xi }_i+{\xi }_i^2\right)\cdot D\left(T{d}_{i-2}^0\right)$$

(63)

Since the sequential logical path is composed of a flip-flop and a combination logical path, the statistical delay model of the sequential path can be obtained by combining the statistical timing model of the flip-flop and the combination logical path, as shown in (64).

$$D\left(T{p}_{i,total}\right)=D\left(T_{cq}\right)+D\left(T{p}_i\right)$$

(64)

The path delay approximately follows a lognormal distribution, assuming that the distribution satisfies Tp~LN (µ_Tp, σ_Tp²), and the geometric mean of the lognormal distribution obtained by one-time SPICE simulation of the Tp is shown in the following equation:

$$T{p}_{nominal}=e^{{\mu }_{tp}}$$

(65)

Then, the expression of µ_Tp is:

$${\mu }_{Tp}=\ln \left(T{p}_{nominal}\right)$$

(66)

According to the nature of lognormal distribution, its variance is calculated as:

$$D\left(Tp\right)=\left(e^{{\sigma }_{Tp}^2}-1\right)\cdot e^{2{\mu }_{Tp}+{\sigma }_{Tp}^2}$$

(67)

To facilitate the solution of the distribution parameters µ_Tp and σ_Tp, coefficient K can be defined as:

$$K={\displaystyle \frac{D\left(Tp\right)}{T{p_{nominal}}^2}}=\left(e^{{\sigma }_{Tp}^2}-1\right)\cdot e^{{\sigma }_{Tp}^2}$$

(68)

It can be obtained by solving (67):

$${\sigma }_{Tp}=\sqrt{\mathit{ln}\left({\displaystyle \frac{1}{2}}+\sqrt{K+{\displaystyle \frac{1}{4}}}\right)}$$

(69)

Substituting (66) and (69) into (70) gives the maximum and minimum delays of the timing path.

$$T{p}_{max/min}=e^{u_{tp}\pm 3{\sigma }_{tp}}$$

(70)

5. Experiments and Discussion

In order to verify the accuracy of the proposed statistical delay model, this section verifies the model proposed in the previous sections on the ISCAS’89 benchmark circuit, and the supply voltage given operates in the subthreshold region. The whole experiment takes the MC simulation results as the gold standard and compares them with other methods.

5.1. Experimental Setup

In this section, the proposed statistical timing model for sequential path was validated by using the process of TSMC28nm in the subthreshold region. The digital circuit flow is adopted to verify the proposed model by analyzing multiple benchmark circuits in ISCAS’89. The RTL of the benchmark circuit is converted into a gate level netlist by synthesis, and then the path netlist is extracted by Prime Time. The critical paths selected for validation from these benchmarks feature diverse logic depths, various cell types, and realistic fan-out conditions, ensuring a comprehensive test of our model’s performance on complex sequential paths. First, the timing modeling of the inverter and stack structure is carried out, and the propagation delay statistical value of the flip-flop are obtained by using the inter-correlation between stages. Then, the lookup table of the relative delay sensitivity X_cell0 of the combinational logical cell is obtained by analytical method, and the statistical delay of the combination logic path are further obtained by inter-stage correlation. Finally, the statistical delay model of the sequential path is obtained by combining the previous two steps.

5.2. Experimental Result and Analysis

In this section, the model proposed in this paper is verified and analyzed through three variation values: path delay standard deviation and path maximum and minimum delays.

As shown in

Table 8. Details of ISCAS’89 benchmark circuits and selected paths.

Circuit	Gate Count	Flip-Flop Count	Path Length
s27	10	3	5
s1196	529	18	20
s13207	7951	638	16
s15850	9772	534	23
s1423	657	74	56

,

Table 9. Standard deviation and maximum and minimum delay errors of time sequence path delay under different processes.

Process	Standard Deviation	Maximum Delay	Minimum Delay
FF	4.7%	7.7%	6.9%
TT	1.7%	4.8%	7.7%
SS	5.6%	3.5%	7.9%
Average	4%	5.3%	7.5%

and

Table 10. Standard deviation and maximum and minimum delay errors of time sequence path delay under different voltages.

Voltage (V)	Standard Deviation	Maximum Delay	Minimum Delay
0.3	1.7%	4.8%	7.7%
0.27	2.9%	5.0%	8.6%
0.25	5.7%	4.5%	10.2%
Average	3.4%	4.7%	8.8%

, the statistical delay value of one path is verified under different processes, voltages, and temperatures. Under the process corners FF, TT, and SS, the mean error of the standard deviation of the path is 4%, the mean error of the maximum delay value is 5.3%, and the mean error of the minimum delay value is 7.5%. Under 0.3 V, 0.27 V, and 0.25 V supply voltages, the mean error of standard deviation is 3.4%, the mean error of maximum delay value is 4.7%, and the mean error of minimum delay value is 8.8%. At −25 °C, 25 °C, and 75 °C, the mean error of standard deviation is 1.4%, the mean error of maximum delay is 5.2%, and the mean error of minimum delay is 8.1%.

In addition to process and voltage variations, the model’s performance was also evaluated across a range of operating temperatures. As presented in

Table 11. Standard deviation and maximum and minimum delay errors of time sequence path delay under different temperatures.

Temperature (°C)	Standard Deviation	Maximum Delay	Minimum Delay
−25 °C	1.6%	6.7%	12.3%
25 °C	1.7%	4.8%	7.7%
75 °C	1.1%	4.1%	4.3%
Average	1.4%	5.2%	8.1%

, the model maintains high accuracy at -25 °C, 25 °C, and 75 °C, with an average error of only 1.4% for standard deviation, demonstrating its thermal robustness.

In order to further verify the accuracy of the model, five circuits are selected from ISCAS’89 benchmark, namely s27, s1196, s13207, s15850, and s1423. Among them, s1423 has the largest number of cells, which is 56. The comparison error results of three metrics with respect to 10,000 runs of MC simulation are listed in

Table 12. Error in standard deviation and maximum/minimum delays with respect to 10k runs of MC simulation for the practical paths of iscas’89 benchmark in 0.3 V supply voltage and 25 °C TT corner.

Circuit	Stage	Standard Deviation			Maximum Delay			Minimum Delay
		[15]	[18]	This Work	[15]	[18]	This Work	[15]	[18]	This Work
s27	5	42.46%	46.78%	2.10%	35.11%	34.27%	4.52%	29.97%	31.65%	9%
s1196	20	43.64%	43.64%	5.42%	22.38%	22.38%	5.84%	15.29%	15.29%	4.83%
s13207	16	26.93%	49.63%	7.08%	24.12%	24.06%	6.36%	16.46%	16.55%	5.34%
s15850	23	39.53%	74.76%	7.72%	15.96%	15.95%	5.67%	6.61%	6.62%	4.95%
s1423	56	4.97%	52.55%	3.83%	22.21%	22.09%	5.74%	14.09%	14.26%	5.48%
Average	--	31.51%	53.47%	5.23%	23.96%	23.75%	5.62%	16.48%	16.87%	5.92%
Improvement (X)	--	6.0X	10.2X	1.0X	4.3X	4.2X	1.0X	2.7X	2.8X	1.0X

.

The percentage error for each metric is calculated using the following formulas, where Predicted refers to the value from our model, and MC refers to the value from Monte Carlo simulation:

$$Erro{r}_{std}=\left|\left({\sigma }_{Predicted}-{\sigma }_{MC}\right)/{\sigma }_{MC}\hspace{0.33em}\right|\times 100\%$$

(71)

$$Erro{r}_{max}=\left|\left(Dela{y}_{max\_Predicted}-Dela{y}_{max\_MC}\right)/Dela{y}_{max\_MC}\hspace{0.33em}\right|\times 100\%$$

(72)

$$Erro{r}_{min}=\left|\left(Dela{y}_{min\_Predicted}-Dela{y}_{min\_MC}\right)/Dela{y}_{min\_MC}\hspace{0.33em}\right|\times 100\%$$

(73)

From the table, the average errors are 5.23%, 5.62%, and 5.92% for standard deviation, maximum delay, and minimum delay, respectively. Compared with other two methods, it can be found that the standard deviation, maximum delay, and minimum delay prediction achieve up to 6.0X (10.2X), 4.3X (4.2X), and 2.7X (2.8X) precision improvements, respectively. This indicates that our proposed model is much more accurate than the method in [15], which does not consider the inter-stage correlation, and the method in [18], which does not consider the influence of the clock path on the propagation delay T_cq.

Beyond its high accuracy, our model’s primary advantage is its computational efficiency. This efficiency arises from a fundamental methodological difference with Monte Carlo simulations. MC analysis is computationally expensive, as it relies on thousands of repetitive circuit simulations to achieve statistical convergence.

In contrast, our analytical model requires only a single nominal SPICE simulation to extract key parameters. The statistical moments are then computed directly via analytical expressions, a step with negligible computational cost. Essentially, our method replaces thousands of transient simulations with one nominal simulation and a simple calculation.

This approach provides a highly favorable time–accuracy trade-off. By maintaining high fidelity to the MC results while drastically reducing runtime, our model enables the rapid, iterative timing analysis essential for modern design cycles, a task where MC simulation is prohibitively slow.

The practical impact of this efficiency in industrial scenarios is significant. By providing fast and accurate statistical timing feedback, our model can be integrated into standard CAD flows to enable early, variation-aware design optimization. This can help reduce the number of costly design iterations and shorten the overall time to market. Furthermore, its high speed makes it a candidate for reducing the reliance on lengthy MC simulations during the final timing sign-off, potentially saving days of computation on large designs.

6. Conclusions

This paper presented an analytical statistical model for sequential path delay variation in low-voltage circuits, based on the lognormal distribution. We introduced a novel method to characterize the delay of complex structures, including stacked transistors and flip-flops, by decomposing the impact of multi-threshold voltage variations and resolving inter-stage correlations through a linear delay model. The use of relative delay sensitivity further enhances the model’s efficiency, allowing for rapid characterization across multiple PVT corners from a single nominal simulation.

Compared to purely mathematical or machine learning-based approaches, our analytical model offers distinct advantages in terms of interpretability and design insight. While ML models may achieve high accuracy after extensive training, our physics-based model provides a clear, transparent relationship between process parameters and timing variations without requiring a large dataset. This makes it particularly valuable for early-stage design exploration and optimization. A qualitative comparison summarizing these trade-offs against other state-of-the-art methods is provided in

Table 13. Qualitative comparison of different SSTA methods.

Feature	Monte Carlo	Fisher’s Model [18]	ML-Based Model	This Work
Accuracy	Gold Standard	Moderate	High	High
Speed	Very Low	High	High	Very High
Interpretability	Low	High	Very Low	High
Data	None	None	Very High	None
Focus	General	Sequential Cells	General	Sequential Paths

.

While the proposed framework demonstrates high accuracy and efficiency, several avenues for future research are identified to further enhance its robustness and applicability. The model’s scalability to advanced nodes like FinFETs is a promising direction; although this would require adapting the underlying device equations, the core methodology of linear decomposition and variance propagation remains applicable. The framework could also be extended to incorporate time-dependent aging effects, such as NBTI and HCI, by modeling their impact as a long-term shift in the threshold voltage distribution. Furthermore, a comprehensive evaluation using additional industrial metrics, such as Mean Absolute Error (MAE) and 95th-percentile delay, would further validate its practical utility for timing sign-off. Finally, while the model shows excellent agreement with extensive SPICE simulations, validation against silicon measurements from a test chip is the ultimate goal to confirm its real-world performance. Addressing these aspects will be the focus of our future investigations.