A Low-Jitter Delay Synchronization System Applied to Ti:sapphire Femtosecond Laser Amplifier

Abstract

Femtosecond lasers have evolved continuously over the past three decades, enabling the transition of research from fundamental studies in atomic and molecular physics to the realm of practical applications. In femtosecond laser amplifiers, to ensure strict synchronization between the seed laser pulse and the pump laser, enabling their precise overlap during the amplification process and avoiding a decline in pulse amplification efficiency and the generation of undesired phase noise, this study designed a synchronous timing signal generation system based on the combination of FPGA and analog delay. This system was investigated from three aspects: delay pulse width adjustment within a certain range, precise delay resolution, and external trigger jitter compensation. By using a FPGA digital counter to achieve coarse-delay control over a wide range and combining it with the method of passive precise fine delay, the system can generate synchronous delay signals with a large delay range, high precision, and multiple channels. Regarding the problem of asynchronous phase between the external trigger and the internal clock, a jitter compensation circuit was proposed, consisting of an active gated integrator and an output comparator, which compensates for the uncertainty of trigger timing through analog delay. The verification of this study shows that the system operates stably under an external trigger with a repetition frequency of 80 MHz. The output delay range is from 10 ns to 100 $\mu$s, the coarse-delay resolution is 10 ns, the fine-delay adjustment step is 1.25 ns, and the pulse jitter is reduced from a maximum of 10 ns to the hundred-picosecond level. This meets the requirements of femtosecond laser amplifiers for synchronous trigger signals and offers essential technical support and fundamental assurance for the high-power and high-efficiency amplification of Ti:sapphire ultrashort laser pulses.

1. Introduction

A delay pulse generator is a device capable of generating pulsed signals with precise time delays, and it has a wide range of applications in numerous fields. In dual-comb spectroscopy techniques, such as cavity-enhanced dual-comb spectroscopy and wide-band dual-comb spectroscopy, precise control of the repetition frequencies and phases of two optical frequency combs is necessary to ensure the generation of stable and resolvable beat-frequency signals [1]. The synchronization system can achieve accurate synchronization and dynamic regulation of the two optical frequency combs, thus enhancing the resolution and reliability of dual-comb spectral measurements [2]. In optogenetics experiments, the delay pulse generator is used to control the timing of light stimulation, enabling precise regulation of neuron activities for studying neural signal transduction and the functions of neural networks [3]. In laser physics experiments, for example, in multi-beam laser synchronization experiments, the delay pulse generator can accurately control the emission time of each laser pulse. This allows for the time synchronization between different lasers or the setting of specific time delays to investigate the process of laser–matter interaction [4]. In a Ti:sapphire femtosecond laser amplification device, the main amplifier mostly adopts a multi-pass structure, which can be either a single-stage design or composed of multiple stages [5]. Regardless of which stage of the amplifier the seed pulse is injected into, it must maintain a synchronized state with the pump laser pulse with a frequency of up to nearly 100 MHz. Generally, controlling the time jitter within 50 ns can meet the requirements [6]. However, if precise control of the output pulse energy of the main amplifier is to be achieved through time-delay means, the time jitter needs to be minimized, preferably below 10 ns. In addition, when the repetition frequency of the injected seed laser pulse differs from that of the pump pulse, the seed pulse needs to be selected to make their repetition frequencies the same. Commonly used components for this selection are Pockels cells or shutter switches, which are used in scenarios with lower frequencies [7]. Since the response time of the shutter switch is on the order of milliseconds, controlling the time jitter between its trigger signal and the seed pulse within 10 $\mu$s can meet the requirements. For a Pockels cell, the high-voltage pulse applied to the electro-optic crystal is controlled to achieve pulse selection of the laser pulses. Here, high-precision synchronization between the high-voltage pulse signal and the mode-locked laser pulse must be ensured, with the time jitter between them being less than 1 ns [8]. Thus, the precision of the synchronization timing directly influences the magnitude and stability of the final output pulse energy. The time delay between the pump pulse and the seed pulse must be precisely controlled to ensure that the pump light excites the Ti:sapphire medium within the effective time of the seed-light pulse. The degree of overlap between the pump pulse and the seed pulse should be as high as possible. Sufficient overlap helps improve the energy-transfer efficiency and increase the peak power of the output pulse so as to achieve the best amplification effect [9].

Currently, there are relevant technical approaches in the field of pulse delay technology. For example, digital counters or phase interpolators are used to divide the frequency or adjust the phase of the clock signal to achieve nanosecond-level delay. However, the minimum step resolution is limited by the clock frequency, and the digital jitter accumulation effect is significant. The delay-line technology is based on the propagation delay of electromagnetic waves in transmission lines. Delay adjustment is achieved by switching microstrip lines or coaxial cables of different lengths through switches [10]. The delay range of this technical solution is limited (≤10 ns). The analog characteristics of coaxial cables are greatly affected by temperature, and they are large in size and difficult to integrate. The optical-domain delay technology is similar in principle to the delay-line technology. It utilizes the transmission delay of light in optical fibers or optical waveguides, and different lengths of optical paths are switched through mechanical or electro-optical optical switches. Its delay resolution is relatively low, and the response speed of optical devices limits high-frequency applications [11]. The adoption of a high-repetition-rate femtosecond laser source can significantly enhance the generation efficiency of attosecond pulses. In the delay synchronization of this system, the divided-frequency output is set to 10 kHz. This setting is a result of comprehensive consideration of factors such as the driving feasibility of the Pockels cell, system stability, and single-pulse energy requirements, aiming to strike a balance among device performance, operational stability, and output energy. However, the above-mentioned technical solutions do not integrate the trigger frequency-division function inherently, making it challenging to meet the trigger frequency-division requirements of the pump pulses for the Ti:sapphire femtosecond laser amplifier [12]. In addition, the output delay pulses have large jitter, and no compensation treatment is carried out for the jitter [13].

At present, there has been no in-depth research on the development of a high-precision delay synchronization system among the internal amplification units of Ti:sapphire femtosecond lasers. In this paper, aimed at the key factors affecting the generation of femtosecond lasers, by reviewing and summarizing the development history of the pulse delay technology field, an analysis and research on the delay pulse width and trigger jitter problems are carried out. A delay synchronization system with a “digital coarse-tuning + analog fine-tuning” hybrid architecture delay technology and analog delay compensation for triggering is proposed to meet the requirements of Ti:sapphire femtosecond laser timing synchronization. The main contributions of this paper are as follows:

(1)

The synchronization timing requirements of the Ti:sapphire femtosecond laser amplifier are complex. The performance of the synchronization pulse directly determines the success of the entire laser pulse amplifier. Therefore, we propose a pulse synchronization system applied to the Ti:sapphire femtosecond laser amplifier.

(2)

We propose a hybrid delay scheme of digital coarse-tuning combined with analog fine-tuning. This can achieve nanosecond-magnitude time fine-tuning while maintaining a large-range delay capability, meeting the stringent requirements of the Ti:sapphire femtosecond laser amplifier for high precision.

(3)

Regarding the problem of uncertain phase errors in the externally triggered repetition frequency and internal clock jitter, we propose to design a jitter compensation circuit to compensate for the uncertainty of the trigger timing through analog delay, which greatly improves the stability of the delayed pulse.

In the second chapter of this paper, the overall design of the high-precision and low-jitter femtosecond laser delay synchronization system, the hybrid delay scheme of “digital coarse-tuning + analog fine-tuning”, and the analysis of analog delay compensation for a trigger jitter is elaborated in detail. The third chapter describes the complete machine of the delay synchronization system, as well as the test environment and results. The fourth chapter analyzes and organizes the experimental results. The fifth chapter summarizes the research of this paper and provides an outlook for the future.

2. Materials and Methods

2.1. The Overall Design of the High-Precision and Low-Jitter Femtosecond Laser Delay Synchronization System

As shown in Figure 1, the high-precision and low-jitter femtosecond laser delay synchronization system mainly consists of a system host computer, an FPGA master control module, a time reference module, a gated integrator module, a precision-delay module, and an output conditioning module [14]. The FPGA master control module is used to implement some medium-speed logic interfaces in the system, including SPI, a counter for coarse delay of the system, and a state machine. The time reference module is used to generate the system’s main 100 MHz clock and can selectively lock the main clock to an internal oscillator or an external clock source. The jitter compensation module, including a gated integration module and a comparison output module, is used to collect the jitter error between the rising edge of the trigger signal and the rising edge of the system clock. It converts the uncertain time quantity into a definite voltage quantity and reduces the uncertainty caused by timing jitter by compensating the analog voltage quantity during comparison output. The precision fine-delay circuit is used to achieve precision fine delay with a resolution on the picosecond scale. The output conditioning module includes a logic gate circuit for output enable, a differential driver, and an amplitude offset adjustment circuit to condition the delayed pulse signal. A high stability mode locked laser pulse is generated by an external mode locked laser of the system, which is converted into a femtosecond laser electrical pulse sequence by a high-speed photodetector and used as a stable external frequency trigger signal [15]. The 100 MHz generated by the time reference module serves as the clock reference for each module of the entire system. The trigger jitter measurement module measures the phase difference between the rising edge of the trigger signal and the rising edge of the 100 MHz time-base by charging a capacitor, and then starts the coarse delay. After the coarse delay ends, the precision delay is initiated. The time of the coarse delay and the precision delay can be set through the host computer [16]. The precision delay is achieved by charging and discharging a capacitor. The delayed signal passes through a voltage comparison module. When the voltage during discharge is equal to the jitter voltage of the collected phase difference, the level of the comparator is inverted and the system generates a delayed signal. Subsequently, the output conditioning module generates multi-channel delayed pulses with adjustable amplitude and polarity.

2.2. Design of the System’s Coarse-Delay and Precision-Delay Modules

2.2.1. Design of the Course-Delay Module

The system delay function is divided into a coarse-delay module and a precision fine-delay module according to the delay resolution. As shown in Figure 2, the coarse delay is implemented through a FPGA. The system clock is counted by an internal counter of the system. The initial value of the counter and the coarse-delay range are designed. The bit-width of the counter is calculated according to the delay requirements. Every time a system clock passes, the value of the counter is incremented. When the count reaches the preset value, the counting process ends, achieving the system coarse delay module [17]. The system clock of the FPGA is provided by the clock generated by an analog phase-locked loop (PLL) circuit. The phase-locked loop (PLL) circuit consists of a phase–frequency detector (PFD), a loop filter, and a voltage-controlled oscillator (VCO). It uses an externally input reference signal or an internally selectable oven-controlled crystal oscillator (OCXO) to control the frequency and phase of the internal oscillating signal of the loop, achieving the automatic tracking of the output signal frequency to the input signal frequency [18]. The “phase-locking” characteristic of the phase-locked loop means that it can keep the phase difference between the phase of the output signal and that of the external reference signal fixed. The externally connected reference signal provides a definite phase reference for the PLL. In different application scenarios, either the signal generator or the OCXO can be selected as the reference source to serve as the input signal of the phase detector [19]. Among them, OCXO (Oven-Controlled Crystal Oscillator) is a high-precision crystal oscillator. It uses a temperature-controlled circuit to keep the operating temperature of the quartz crystal within a specific range, minimizing the impact of ambient temperature changes on the oscillation frequency to the greatest extent.

The phase detector is used to compare the frequency and phase of the input 10 MHz reference frequency with the feedback frequency, convert the phase difference into a voltage signal, and transmit it to the charge pump to generate a voltage signal. After passing through the loop filter, it enters the voltage-controlled oscillator to generate a 100 MHz time-reference signal for the system. This time reference signal also serves as the FPGA clock signal. A dedicated counter is configured within the FPGA. Using this 100 MHz as the clock, the counter counts. One clock cycle is 10 ns, so the coarse-delay resolution is 10 ns. Each time the counter captures a rising edge of the 100 MHz clock, it performs an increment operation. When the count accumulates to the preset coarse-delay value, it triggers the inversion of the output clock level, thus achieving the system’s coarse-delay operation [20]. Since the synchronization pulse trigger frequency that the Ti:sapphire femtosecond laser amplification system needs to output is 10 kHz, limited by the relationship between frequency and period, the longest delay time of the system is 100 $\mu$s. With the system clock frequency being 100 MHz, the bit-width of the counter needs to meet the following:

$$M\ge {log}_2\left({\mathrm{Delay}}_{\max }/T\right)$$

(1)

In Equation (1), ${\mathrm{Delay}}_{\max }$ is the maximum delay time of 100 $\mu$s and clock cycle T is 10 ns. It can be obtained that the minimum bit-width M of the counter is 13 bits. Here, we adopt a 15-bit counter. To improve the efficiency of coarse delay, the counter is split into three 5-bit counters, and registers are defined for serial operation.

2.2.2. Design of the Precision-Delay Module

As shown in Figure 3, the precision-delay module consists of a high-precision 12-bit DAC (LTC2635), a high-speed differential receiver, a D-flip-flop with clear and preset functions, a constant-current source circuit, a high-precision low-temperature-drift charging capacitor, etc. DAC, namely Digital-to-Analog Converter, is an electronic device or circuit that converts digital signals into analog signals (continuous voltage or current). In this system, it is used to set the precise delay time required by the synchronization system [21]. The constant-current source circuit provides a fixed current for the charging and discharging processes. The high-speed differential receiver is used to receive the 100 MHz clock signal and the precision delay enables the signal. These two signals are then re-clock-synchronized by the D-flip-flop and output, causing the constant-current source circuit to discharge the charging capacitor C1 [22]. The voltage is then compared with the trigger jitter voltage through a voltage comparison circuit. When the discharged voltage is equal to the trigger jitter voltage, the comparator inverts and the delay signal is output.

The precision-delay module achieves time delays within 10 ns. The core of the precision delay lies in the linear relationship between the voltage across the charging capacitor C1 and time [23].

$${\displaystyle \frac{I}{C}}={\displaystyle \frac{\mathrm{d}u}{\mathrm{d}t}}$$

(2)

In Equation (2), I represents the charge–discharge current, C represents the capacitance value of capacitor C1, and the right-hand side of the equation represents the charge–discharge rate.

In theory, precise delay utilizes the concept of time-to-voltage conversion. By means of the linear mapping relationship between time-domain signals and voltage signals, it indirectly measures and regulates time with high precision by quantifying time intervals into measurable voltage amplitudes. The charging and discharging current of the constant-current source is 10 mA, and the high-precision capacitor C1 is 100 pF. Thus, the charging and discharging rate is 100 mV/ns. A 12-bit high-precision DAC is adopted, with a reference voltage of 4.096 V. The resolution of the DAC is 1 mV, corresponding to 10 ps. A voltage-resistance scaling matching network with R1:R2 = 4:1 is designed, which means that 1 mV corresponds to a time variation of 2.5 ps. The host computer sets a 500 mV level change as the precise delay step, achieving a 1.25 ns fine-tuning.

2.3. Design of the Jitter Compensation Module

The jitter compensation module consists of a gated integrator and an output comparison circuit. As shown in Figure 4, since the external trigger signal EXT_TRIG and the system’s 100 MHz clock exist asynchronously, with a phase difference between the two clocks ranging from 0 to 360°, there is random jitter between the phase-controlled trigger and the system output. The FPGA allows the synchronization system to receive the trigger signal; that is, the trigger enables EXT_TRIG, through combinational logic gates. The data must be stable within a certain period of time before the effective edge of the clock arrives; otherwise, the flip-flop cannot latch on to the data. Therefore, a fixed delay time t1 is required to establish the trigger. The charging rate of the current source circuit is calibrated by setting the value of the DAC. Before the external trigger signal arrives, the current source charges the sampling capacitor at 10 mA. However, due to the presence of the clamping circuit, the level of the sampling capacitor is clamped at a fixed value. When the trigger signal is captured, the clamping level rises, and the output level of the gated switch jumps, causing the emitter-coupled high-speed switch to turn off. The level of the sampling capacitor then rises at a rate of 100 mV/ns. The trigger jitter time is calculated through the voltage difference across the sampling capacitor. The maximum jitter time is 10 ns; that is, the sampling voltage within a single delay cycle is within a range of 1 V. Thus, the acquisition of the phase difference between the trigger source and the system’s 100 MHz clock is achieved, completing the trigger jitter measurement.

The comparison output module consists of a mirror-image constant-current source and a pair of high-speed turn-off PNP-type transistors. As shown in Figure 5, in the mirror-image constant-current source circuit, Q2 and Q3 are two transistors with the same parameters.

Among them, Q2 operates in the amplification region. After the base and emitter of Q3 are short-circuited, the collector–base junction then becomes equivalent to a diode. This connection method can make use of the unidirectional conductivity of the diode to perform rectification and clamping functions in the circuit.The current I2 is output from the collector of Q2. Their base voltages U1 are the same, and the emitter voltage of Q2 is U2.

The magnitude of the current $I_2$ of the mirror-image constant-current source is expressed as Equation (3);

$$\begin{array}{cc}\hfill U_1=& {\displaystyle \frac{VCC-U_{\mathrm{be}}}{R_5+R_7}}·R_7\hfill \\ \hfill U_2=& U_1+U_{\mathrm{be}}\hfill \\ \hfill I_2=& {\displaystyle \frac{VCC-U_2}{R_4}}\hfill \end{array}$$

(3)

The output comparison timing is shown in Figure 6. Before the enable signal of the precise delay signal arrives, the voltage of ${\mathrm{V}}_{\mathrm{fds}}$ is greater than that of ${\mathrm{V}}_{\mathrm{jitter}}$. This causes Q4 to be in the off state, operating in the cut-off region, while Q5 is in the on state, operating in the amplification region. In this case, the current of the constant-current source I2 passes through the collector of Q4 to create a voltage difference across R8, making the voltage of R8 higher than that of R9, thus outputting a differential low level signal. When the voltage of ${\mathrm{V}}_{\mathrm{fds}}$ drops to the same level as ${\mathrm{V}}_{\mathrm{jitter}}$ after being discharged by the constant-current source I1, Q4 turns on and operates in the amplification region, while Q5 turns off and operates in the cut-off region. At this time, the constant-current source I2 passes through the collector of Q4 to create a voltage difference across R9, making the voltage of R9 higher than that of R8, and outputting a differential high-level signal. Consequently, the voltage-to-comparative function is achieved. The output signal of the voltage comparison module flips to control the drive circuit, which serves as the final output signal. This realizes the compensation for the uncertainty of the timing through analog delay.

3. Experiment and Result Analysis

3.1. System Performance Testing

We conducted simulation verification on each module of the above-mentioned design scheme. After completing the hardware circuit design and surface mount debugging, we obtained the physical object of the delay synchronization system. We used the Tektronix AFG31000, Beaverton, OR, USA signal generator as the repetitive frequency trigger signal of the system, setting the frequency to 80 MHz and the amplitude to 4 Vpp. The delay output signal was tested using a Tektronix MSO46 oscilloscope (with a bandwidth of 1.5 GHz, a sampling rate of 6.25 GS/s, and a single-sampling interval of 0.16 ns). The main indicators evaluated of the system included coarse-delay and precise-delay functions, and delay jitter.

3.2. System Delay Function Testing

The coarse-delay and fine-delay functions of the system were tested separately. The coarse delay was generated by the internal counter of the FPGA. After setting the delay times to 10 ns, 100 ns, 150 ns, and 200 ns, respectively, and conducting 50 repeated tests, the average values of the actual output data were fitted to verify the accuracy of the coarse delay, as shown in Figure 7.

In the test to verify the resolution of the coarse delay, with the delay range set from 20 ns to 120 ns and a step of 10 ns each time, a curve of the error between the actual value of the coarse delay and its relative theoretical value was obtained. In Equation (4), the ${\mathrm{t}}_{\mathrm{set}}$ is the independent variable, the ${\mathrm{t}}_{\mathrm{actual}}$ is the dependent variable, and ${\mathrm{t}}_{\mathrm{relative}\mathrm{error}}$ is the difference between the actual value of the coarse delay and the set value.

$$t_{\mathrm{relative}\mathrm{error}}=t_{\mathrm{actual}}-t_{\mathrm{set}}$$

(4)

If precise regulation of the energy of the main amplifier’s output pulse via time-delay methods is required, time jitter must be minimized to within 10 ns. In the pulse-selection scenario, the response time of shutter-based selection is in the millisecond range, while the gating time of Pockels-cell-based selection is in the microsecond range.

As shown in Figure 8, actual measurements indicate that the error between the coarse-delay value and the theoretical setting remains consistently below 1 ns. This error magnitude has negligible impact on the accuracy of pulse selection and fully meets the requirement that the repetition frequencies of the seed pulse after selection and the pump pulse are identical.

The coarse-delay resolution is 10 ns. Thus, to verify the precise-delay function, the verification should be conducted on a time scale less than 10 ns. The delay interval from 40 ns to 50 ns is divided into eight sub-steps, allowing the time interval corresponding to each single sub-step to be precisely adjusted to 1.25 ns. Each delayed pulse is output continuously for 100 times. In this way, the precise fine-delay function is verified. The mean-value-taken and fitted waveform is shown in Figure 9. The precision fine-delay function of the system is normal.

3.3. System Output Jitter Stability Testing

The jitter of the system output waveform is an important technical indicator for judging the performance of the delay synchronization system. The delay time was set to 30 ns for the output jitter test. The oscilloscope was set to the persistence mode, triggered by the falling edge. The delay was continuously output for 10 min. Through the experimental test, the probability density distribution diagram of the pulse phase jitter was obtained, as shown in Figure 10.

Obtain the distribution data of the pulse phase jitter deviation landing points, as shown in

Table 1. Distribution table of pulse phase jitter deviation.

Jitter Range (T)	Interval Spacing (t)	Interval Midpoint (x)	Number of Distributions (f)
T1	1.75–1.80 ns	1.775	5
T2	1.80–1.85 ns	1.825	41
T3	1.85–1.90 ns	1.875	251
T4	1.90–1.95 ns	1.925	520
T5	1.95–2.00 ns	1.975	495
T6	2.00–2.05 ns	2.025	249
T7	2.05–2.10 ns	2.075	90
T8	2.10–2.15 ns	2.125	26
T9	2.15–2.20 ns	2.175	12
T10	2.20–2.25 ns	2.225	0

. The discreteness of the above-mentioned pulse jitter was analyzed and evaluated. Its probability density function was calculated, and a statistical test was carried out. By calculating the average jitter level of the pulses, the mean value of the pulse jitter data was found to be 1.94 ns; that is, the inherent delay of the delay synchronization system is 1.94 ns. The standard deviation reflects the degree of dispersion of the pulse jitter data. The smaller the standard deviation, the more concentrated the data are around the mean value, and the more stable the jitter is; conversely, the more dispersed the jitter is. The calculated standard deviation is 0.113 ns, which is on the order of hundreds of picoseconds, indicating that most of the pulse jitter data are distributed within the range of the mean value ± 0.113 ns.

In the calculation formulas for the mean and standard deviation, x represents the mid point of different jitter intervals, f represents the number of distributions in the corresponding interval, $\sigma$ represents the standard deviation, and u represents the distribution mean. In Equation (5), x and f are independent variables, while u and $\sigma$ are dependent variables. The mean, distribution variance, and standard deviation of the pulse jitter data are calculated according to the weighted-average formula.

$$\begin{array}{cc}\hfill u& ={\displaystyle \frac{{\sum }_{i=1}^n{x}_i{f}_i}{{\sum }_{i=1}^n{f}_i}}\hfill \\ \hfill {\sigma }^2& ={\displaystyle \frac{{\sum }_{i=1}^n{f}_i{\left(x_i-u\right)}^2}{{\sum }_{i=1}^n{f}_i}}\hfill \end{array}$$

(5)

Based on the properties of the Gaussian distribution, by comparing the probability of pulse jitter in different intervals, approximately 93.54% of the data fall within the interval of the mean value ± 1 times the standard deviation, 99.29% of the data fall within the interval of the mean value ± 2 times the standard deviation, and all data fall within the interval of ±2 times the standard deviation. From

Table 2. Actual coverage rates of pulse jitter Gaussian distribution intervals.

Discrete Intervals	Interval Spacing	Standard Value	Actual Value	Whether It Meets
$[u-\alpha ,u+\alpha ]$	[1.827, 2.053]	68.27%	93.54%	meets
$[u-2\alpha ,u+2\alpha ]$	[1.714, 2.166]	95.45%	99.29%	meets
$[u-3\alpha ,u+3\alpha ]$	[1.601, 2.279]	99.73%	100.00%	meets

, the actual coverage rate of the pulse jitter Gaussian-distribution interval indicates that compared with the requirements for this type of signal in industry standards, both the mean value and the standard deviation of the pulse jitter obtained by this system are within the allowable range and conform to the Gaussian distribution.

Experiments show that the jitter compensation circuit composed of the gated integration module and the comparator output circuit operates normally. The system innovatively designs the jitter compensation circuit, reducing the trigger jitter time from a maximum of 10 ns to the order of hundreds of picoseconds, which greatly improves the stability of the delay synchronization system.

As shown in

Table 3. Comparison of the delay synchronization system with existing products.

Name	Range	Resolution	Delay Accuracy	Jitter	Frequency Division
Delay synchronization system	10 ns → 100 $\mu$s	2.5 ps	<1 ns	<113 ps	Yes
Model 765	300 ps → (period-300 ps)	10 ps	±(0.1% + 30 ps)	<10 ps	No
MC100EP196	2.4 ns → 12.4 ns	10 ps	<2 ns	<1 ns	No
Model 577	0 s → 1000 s	250 ps	1 ns + (0.0001 × delay setting)	<250 ps	No

, this delay synchronization system is compared with existing products on the market in terms of delay range, resolution, trigger jitter, etc. Regarding the delay range, as this system needs to set a 10 kHz output, and the delay adjustment has to be synchronized based on the period of the trigger signal. If the delay time exceeds this period, it will lead to a timing conflict between subsequent trigger signals and previous delay controls. Thus, the theoretically maximum delay time is strictly limited to the period of the trigger signal, a constraint determined by the inherent physical relationship between frequency and period. In comparison, for similar products without an integrated trigger frequency-division function, their delay adjustment is not constrained by the period of a specific output frequency. The delay resolution of existing commercial products can reach the order of 10 ps, while our delay synchronization system has achieved a higher resolution of 2.5 ps. Specifically, the MC100EP196 employs an architecture of programmable gate circuits and a multiplexer matrix. Its technical principle is founded on the propagation delay differences in signals in different physical transmission paths. It achieves timing regulation through the physical properties of path lengths, and its resolution ceiling is limited by the manufacturing accuracy and consistency of the physical paths. In contrast, our system adopts a delay architecture of “digital coarse delay+analog fine delay”. An analog adjustment circuit constructed by a high-precision digital-to-analog converter and a precision resistor network enables precise fine-delay control at the 2.5 ps order. Its core advantage lies in the fact that the continuously adjustable characteristics in the analog domain compensate for the resolution bottleneck of the discrete digital adjustment. In addition, while the analog fine-delay circuit achieves an ultra-high resolution of 2.5 ps, which is higher than the 10 ps order, it inevitably introduces thermal noise and shot noise from analog devices. This leads to an increase in jitter and a decrease in accuracy. Under the current technical approach, this represents a balanced solution that aims to meet high-resolution requirements while also considering low-jitter performance. Trigger frequency-division plays a crucial role in the entire Ti:sapphire femtosecond laser, and this function is the key to the timing synchronization of multiple modules. If other frequency-division methods are used, such as the frequency-division of the Q-switch electronic module, it selects 10 kHz pulses from an 80 MHz pulse sequence. The Q-switch electronic module requires a radio-frequency (RF) signal as the trigger source, and this RF signal is obtained by processing the 10 kHz signal output from the synchronization circuit after frequency-division. Without the 10 kHz driving signal generated by the frequency-division of the synchronization circuit, the Q-switch cannot operate normally. Although a 10 kHz signal can be provided by a signal generator, this signal is not synchronized with the 80 MHz signal of the oscillator. This will cause the pulses generated by the Q-switch to experience timing disorders shortly, rendering it impossible to select the correct pulses. Therefore, in the Ti:sapphire femtosecond laser system, the delay synchronization system with an integrated trigger frequency-division function is an indispensable key subsystem.

4. Conclusions

In this study, we designed a synchronous timing signal generation scheme that combines FPGA and analog delay. This scheme encompasses three aspects: controlling the coarse delay over a wide range through a FPGA digital counter, implementing analog passive precise fine delay, and achieving high-stability of the trigger signal using a jitter-compensation module centered around a gated integrator. Compared with existing delay systems, this system can perform high-precision delay on external trigger signals when receiving a pump signal with a specific frequency of up to 80 MHz. The output pulse delay ranges from 10 ns to 100 $\mu$s, the coarse-delay resolution is 10 ns, the fine-delay adjustment step is 1.25 ns, and the delay jitter is reduced from a maximum of the 10 ns magnitude to the hundred-picosecond magnitude. This meets the requirements of femtosecond laser amplifiers for synchronous trigger signals.

At present, in the field of pulse delay technology, there are relevant technical routes such as digital counter technology, delay-line technology, and optical-domain delay technology. However, the research and development of a high-precision delay synchronization system for the internal amplification units of Ti:sapphire femtosecond lasers have not been carried out in-depth. Therefore, by reviewing and summarizing the development process of the pulse delay technology field, this paper proposes a hybrid architecture delay technology and a delay synchronization system that uses an analog delay compensated triggering method, aiming to meet the application requirements of Ti:sapphire femtosecond laser timing synchronization.

Although excellent results have been achieved in the research on the high-precision delay synchronization system for Ti:sapphire femtosecond lasers, in the future, more channels of synchronous control could be integrated to expand to the collaborative working scenarios of multi-dimensional laser systems. Additionally, machine learning algorithms could be introduced to optimize the jitter compensation strategy, further reducing the residual jitter in high-frequency scenarios. Since the system integrates multiple channels, the thermal noise of circuit components in each channel will superimpose and cross-talk with each other. Next, we will continue to attempt to optimize the research content and explore delay synchronization technology more deeply from the above-mentioned perspectives.