A 13.44-Bit Low-Power SAR ADC for Brain–Computer Interface Applications

Abstract

This paper presents a successive approximation register analog-to-digital converter (SAR ADC) specifically optimized for brain–computer interface (BCI) applications. Designed and post-layout-simulated using 180 nm CMOS technology, the proposed SAR ADC achieves a 13.44-bit effective number of bits (ENOB) and 27.9 μW of power consumption at a supply voltage of 1.8 V, enabled by a piecewise monotonic switching scheme and dynamic logic architecture. The ADC supports a high input range of ±500 mV, making it suitable for neural signal acquisition. Through an optimized capacitive digital-to-analog converter (CDAC) array and a high-speed dynamic comparator, the ADC demonstrates a signal-to-noise-and-distortion ratio (SINAD) of 81.94 dB and a spurious-free dynamic range (SFDR) of 91.69 dBc at a sampling rate of 320 kS/s. Experimental results validate the design’s superior performance in terms of low-power operation, high resolution, and moderate sampling rate, positioning it as a competitive solution for high-density integration and precision neural signal processing in next-generation BCI systems.

1. Introduction

As a cutting-edge neural engineering technology, brain–computer interface (BCI) systems have demonstrated revolutionary potential across medical rehabilitation, motor function restoration, and neuroscience research. Figure 1 illustrates representative electrophysiological signal modalities including electrocorticography (ECoG), action potentials (APs), electroencephalography (EEG), electrocardiograms (ECG), and local field potentials (LFPs) [1]. EEG-based systems not only decode neural patterns for device control, but also provide a versatile platform for brain state monitoring—enabling detection of physiological disorders (e.g., Parkinson’s disease, epilepsy [2]) and psychological conditions (e.g., depression, insomnia [3]), with emerging applications extending to sleep staging [4], emotion recognition [5], and human–computer interaction. Clinically, implantable BCI systems enable robotic arm control for spinal cord injury patients through ECoG signal decoding, while non-invasive EEG systems establish novel communication pathways for locked-in syndrome patients. The translational value of such biosignal analysis is further evidenced in ECG monitoring, where cardiovascular diseases (CVDs) accounting for 31% of global mortality (17.9 million annual deaths) [6,7] drive the demand for multimodal diagnostic platforms. These cross-domain applications impose three critical specifications on front-end circuits: (1) microwatt-scale ultra-low power consumption for implantability and continuous monitoring, (2) high quantization accuracy for neural spike detection and pathological biomarker identification, and (3) millimeter-scale miniaturized packaging to support ubiquitous health sensing.

Within the BCI signal chain (Figure 2), the ADC serves as a pivotal interface between analog biopotentials and digital processing. Typical neural signals exhibit distinctive characteristics: 0.1–10 kHz bandwidth, 10–100 μV amplitude, ±300 mV electrode offset tolerance requiring high input impedance, and <10 dB signal-to-noise ratio (SNR) in harsh environments [8]. These constraints demand ADCs achieving 14–16-bit effective resolution with sub-μW power budgets—a stringent requirement conflicting with traditional architectural paradigms.

Current BCI systems primarily evaluate three ADC topologies: SAR, Delta-Sigma (ΔΣ), and pipelined architectures. While conventional SAR ADCs achieve μW-level power efficiency through binary-search quantization, their performance in neural applications faces three fundamental limitations: First, comparator metastability, parasitic capacitance, and capacitor mismatch restrict the ENOB to below 12 bits. Second, the D flip-flop-based logic array incurs excessive power consumption due to the cumulative dynamic switching activity and clock network loading inherent in its architecture. Third, switching noise from large capacitor arrays exacerbates signal integrity challenges in multi-channel arrays [9]. ΔΣ modulators theoretically attain 16-bit resolution through oversampling, yet suffer from mW-level power dissipation due to active integrator stages, rendering them unsuitable for BCI [10]. Pipelined architectures strike favorable speed–accuracy tradeoffs, but incur significant area overhead from digital calibration circuitry [11].

This paper presents a neural signal-optimized SAR ADC with three key enhancements for BCI constraints:

• Compared to conventional architectures, the segmented monotonic switching scheme significantly reduces the capacitor array’s footprint and power dissipation while introducing redundancy to enhance tolerance to parasitic capacitance and relax performance requirements for backend comparators.
• The circuit design primarily employs fully dynamic comparators and a dynamic logic array with enhanced latching speed to minimize total power consumption.
• A relatively high ±500mV input range and a bandwidth extending up to 10 kHz enable the front-end AFE (Analog Front-End) to achieve higher amplification gain, thereby effectively reducing the system’s input-referred noise.

The remainder of this paper is organized as follows: Section 2 details the architectural innovation and circuit implementation, Section 3 presents the post-layout simulation results for the integrated circuit, and Section 4 discusses the conclusions of this work.

2. Circuit Topology

2.1. Architectural Overview

Figure 3 depicts the system architecture of the proposed SAR ADC. The circuit employs a 16 × oversampling technique. During the sampling phase, neural signals are captured using bootstrapped sampling switches and stored on the CDAC array. The SAR quantization phase involves a 12-bit successive approximation conversion, facilitated by the coordinated operation of the CDAC array, an Elzakker-type dynamic comparator, and dynamic SAR logic control.

Key functional blocks include bootstrapped sampling switches for linear signal acquisition, a segmented CDAC array with VCM-based switching to minimize power consumption, and a low-kickback Elzakker dynamic comparator to ensure high-speed and accurate decision-making. The dynamic SAR logic control unit is designed to optimize power efficiency, enabling the ADC to meet the stringent requirements of brain–computer interface applications.

2.2. Bootstrapped Sampling Switch Design

As depicted in Figure 4, the charge-pump bootstrapped sampling circuit incorporates dynamic gate biasing technology. Compared to conventional transmission gate switches, the primary advantage of this architecture lies in its constant on-resistance (R_on): by stabilizing the gate-to-source voltage (V_GS), it maintains a uniform Ron regardless of input signal amplitude variations, while simultaneously avoiding the limited input/output swing issue inherent in complementary CMOS switches and the difficulty of generating precise complementary clock signals. As illustrated in Figure 5 and Figure 6, the circuit operates in two primary phases:

• Φ₁ (Reset Phase):

The circuit enters a reset state where the top and bottom plates of the bootstrap capacitor are connected to V_DD and GND, respectively. The bootstrap capacitor charges to V_DD, storing the necessary charge for subsequent operation.

2.

Φ₂ (Sampling Phase):

The circuit enters a pumped state, where the source terminal of the switch transistor connects to the bottom plate of the bootstrap capacitor and the gate terminal connects to the top plate of the bootstrap capacitor. Consequently, the gate-to-source voltage (V_GS) is pumped to (V_in + V_DD), ensuring V_GS = V_DD (independent of input voltage).

This implementation eliminates the inherent nonlinear Ron variation of standard CMOS switches, with its on-resistance expressed as follows:

$$R_{\mathrm{on},\mathrm{bootstrap}}={\displaystyle \frac{1}{{\mu }_{\mathrm{n}}{C}_{\mathrm{ox}}\frac{W_{\mathrm{N}}}{L_{\mathrm{N}}}\left(V_{\mathrm{DD}}-V_{\mathrm{THN}}\right)}},$$

(1)

where μ_n represents electron mobility (a process-dependent parameter), C_ox denotes the gate oxide capacitance per unit area, W_N and L_N correspond to the width and length of the NMOS switch transistor, V_GS is the gate-to-source voltage, where V_GS equals V_DD., and V_THN is the threshold voltage. The critical term (V_DD − V_THN) remains stabilized through the bootstrapping mechanism, ensuring immunity to input signal fluctuations.

For bootstrapped gate-voltage switch circuits, the primary sources of nonlinearity include the following:

• The charge injection effect in switch transistors manifests when the device turns off, as the inversion layer channel charge redistributes through the source/drain terminals, inducing an error voltage ΔV on the sampled-and-held signal.
• Clock Feedthrough Effect: when the clock signal transitions, it couples onto the sampling capacitor through the gate-drain overlap capacitance (C_gd) or gate-source overlap capacitance (C_gs) of the switch transistor, introducing nonlinear perturbations at the sampled output.
• Body Effect (Substrate Bias Effect): in n-well processes, the body effect in NMOS switch transistors must be rigorously considered, as the threshold voltage (V_TH) exhibits a nonlinear dependence on the input signal (V_in), directly contributing to sampling nonlinearity.

In addition to the aforementioned nonlinearity sources, sampling clock jitter also introduces signal distortion, as visually demonstrated in Figure 7.

δ(nT) denotes the temporal deviation between actual and ideal sampling instants at the time nT, representing clock jitter in the time domain. Δ(nT) quantifies the voltage error between the measured sample value and the ideal value at nT. The polarity of Δ(nT) is determined by the signs of δ(nT) and the input signal’s slope, where for a sinusoidal input signal x(t) = Asin(ωint), the sampling error caused by clock jitter is expressed as follows:

$$\mathsf{\Delta }x\left(nT\right)=A{\omega }_{\mathrm{in}}\delta \left(nT\right)\cos \left({\omega }_{\mathrm{in}}nT\right).$$

(2)

The random clock jitter can be modeled as a white noise source x_jitter(t) that is added to the input prior to ideal sampling, where the resulting sampling error power due to clock jitter is given by the following:

$$x_{jitter}^2\left(t\right)={[A{\omega }_{\mathrm{in}}\cos \left({\omega }_{\mathrm{in}}t\right)]}^2\cdot {\delta }_{jitter}^2\left(t\right)={\displaystyle \frac{{(2\pi f_{\mathrm{in}}A)}^2}{2}}{\delta }_{jitter}^2\left(t\right).$$

(3)

Given the input sinusoidal signal power of A²/2, the resulting signal-to-noise ratio degradation caused by sampling clock jitter is as follows:

$$SN{R}_{jitter}{|}_{\mathrm{dB}}=-20\lg \left[2\pi f_{\mathrm{in}}{\delta }_{jitter}\left(t\right)\right].$$

(4)

The signal-to-noise ratio degradation caused by clock jitter depends not only on the jitter itself, but also on the input frequency, with empirical design practice requiring that jitter-induced noise remains below half of the quantization noise, expressed as follows:

$${\displaystyle \frac{{(2\pi f_{\mathrm{in}}A)}^2}{2}}{\delta }_{jitter}^2\left(t\right)\le {\displaystyle \frac{1}{2\cdot 12}}\cdot {({\displaystyle \frac{2A}{2^N}})}^2,$$

(5)

$${\delta }_{jitter}^2\left(t\right)\le {\displaystyle \frac{1}{12{\pi }^2{f}_{\mathrm{in}}^2{2}^{2N}}}.$$

(6)

For a 12-bit ADC operating at 320 kS/s, the RMS jitter δ_jitter must be maintained at below 2.31 ns—a readily achievable specification—while the white noise introduced by clock jitter can be effectively suppressed through oversampling techniques, demonstrating how moderate-speed converters benefit from relaxed jitter requirements and noise-shaping capabilities.

According to references [12,13], the third-order harmonic distortion introduced by a constant on-resistance sampling switch is given by the following expression, indicating that linearity can be improved by reducing the on-resistance while increasing the V_GS of the sampling transistor.

$$\left|HD3\right|\cong {\displaystyle \frac{1}{4}}{\displaystyle \frac{A^2}{{\left(V_{\mathrm{GS}}-V_{\mathrm{TH}}\right)}^2}}2\pi f_{in}R{C}_L$$

(7)

where A represents the input signal amplitude, fin denotes the input frequency, R is the on-resistance, and C_L signifies the sampling capacitance.

The synchronous clock-controlled circuit features fixed conversion time for each bit. Through a series-connected MOSFET configuration, this design enables optimized switch transistor sizing where each bit’s capacitor employs switches with tailored on-resistance—this approach minimizes the overall device area while maintaining timing precision, as illustrated in Figure 4. The ellipsis (...) in the schematic denotes replicated MOS transistors with identical configurations.

Operating at a 320 kS/s sampling rate with a 9.6875 kHz input frequency that satisfies coherent sampling conditions, the dynamic performance characteristics of the least significant bit in the sampling circuit are demonstrated in Figure 8.

2.3. Capacitive DAC Array Design

The CDAC architecture proposed in this design is shown in Figure 9. The capacitance values in the MSB (most significant bit) section are 32 C_u, 16 C_u, 8 C_u, 4 C_u, 4 C_u, 2 C_u, and 1 C_u; those in the LSB (least significant bit) section are 32 C_u, 16 C_u, 8 C_u, 8 C_u, 4 C_u, 2 C_u, and 1 C_u. Here, C_u represents the unit capacitor. In the schematic, VN0 to VN13 denote the outputs of each stage in the preceding bootstrapped sampling switch, and N13 to N0 and P13 to P0 are signals fed back by the SAR logic array.

The CDAC architecture synergistically integrates three innovative techniques: bottom-plate sampling with a V_CM reference switching protocol for charge injection cancellation, a segmented binary-weighted structure employing bridge capacitors for area-efficient impedance matching, and strategic insertion of redundant bits in both MSB and LSB sections for error correction. This optimized system architecture achieves a remarkable 87% switching energy reduction and 98.3% area savings compared to conventional implementations through novel charge redistribution pathways and switched-capacitor network optimizations.

The bottom-plate sampling technique ensures that the total charge on the capacitor’s top plate node remains constant after switch disconnection, effectively isolating the critical sampling node from charge injection and charge absorption effects during switch transitions while maintaining invariant charge conditions on the upper plate that protect comparator input pair MOSFETs from disturbance, thereby enabling the ADC to achieve a superior linearity performance through this charge-conserving architecture.

The V_CM-based switching scheme incorporates an additional reference voltage at V_CM = 1/2V_DD = 900 mV where, during sampling, all capacitor bottom plates connect to V_CM before the SAR logic array, upon completing comparison, drives each capacitor’s bottom plate to either V_DD or GND based on the conversion results [14]. This methodology ensures that each capacitor switches only once per conversion cycle while maintaining a constant input common-mode voltage at the comparator through simultaneous differential capacitor switching, thereby achieving the dual advantages of power reduction during capacitor switching and a simplified comparator design by eliminating common-mode transients that would otherwise require complex auto-zeroing or offset cancellation circuitry.

The high-precision SAR ADC typically adopts a segmented capacitor array structure, as illustrated in Figure 10, where this partitioning architecture effectively reduces the number of unit capacitors needed to optimize the chip area while simultaneously lowering the performance requirements for sampling switches and accelerating the CDAC settling time through the reduced capacitive load. To ensure proper binary weighting accuracy, the smallest capacitor in the MSB array must maintain precisely twice the weight of the largest capacitor in the LSB section—this critical ratio guarantees that when applying VR step inputs at test points 1 and 2, the resulting DAC output voltage Vo exhibits correct code transition behavior meeting the $d{V}_{o1}=2d{V}_{o2}$ relationship, and:

$$d{V}_{O1}={\displaystyle \frac{K{C}_u\left(C_a+C_{Lt}\right)}{X}}\cdot V_R,$$

(8)

$$d{V}_{O2}={\displaystyle \frac{2^{L-1}{C}_a{C}_u}{X}}\cdot V_R,$$

(9)

where the variables C_u, C_a, and C_Lt represent the unit capacitance serving as the fundamental weighting element, the bridge capacitor that couples the MSB and LSB arrays while compensating for voltage division effects, and the total LSB capacitance incorporating both designed values and parasitic components, respectively.

Hence, we derive that:

$${\displaystyle \frac{C_a}{C_u}}={\displaystyle \frac{k}{2^L-k}}{\displaystyle \frac{C_{Lt}}{C_u}},$$

(10)

$$C_{Lt}\ge \left(2^L-1\right)C_u,$$

(11)

Simplification yields the following:

$$\left\{\begin{array}{c}{\displaystyle \frac{C_a}{C_u}}\ge 1,K=1\\ \\ {\displaystyle \frac{C_a}{C_u}}>K,K>1\end{array}\right..$$

(12)

The finalized bridge capacitor values under various K conditions are presented in

Table 1. Capacitor selection methodology for different K values.

K	${\mathbf{C}}_{\mathbf{a}}/{\mathbf{C}}_{\mathbf{u}}$	${\mathbf{C}}_{\mathbf{L}\mathbf{t}}$
1	1	2L − 1	The parasitic capacitance at the LSB node, $C_{d2}=0$.
1	2	2 × (2L − 1)	The parasitic capacitance at the LSB node, $C_{d2}=$ 2L − 1.
1	4	4 × (2L − 1)	The parasitic capacitance at the LSB node, $C_{d2}=$ 3 × (2L − 1).
2	4	2 × (2L − 2)	The parasitic capacitance at the LSB node, $C_{d2}=$ 2L – 3.

.

Furthermore, the bridge capacitor’s value is determined solely by the parasitic capacitance associated with the LSB capacitor array while remaining independent of MSB parasitics—this critical distinction arises because the MSB parasitic components merely introduce a constant charge offset that uniformly scales the DAC’s gain factor without affecting code-to-code transition linearity, whereas LSB parasitics directly modify the inter-segment charge division ratio and, thus, must be explicitly compensated through careful bridge capacitor sizing to maintain the required C_a/C_Lt proportionality that ensures monotonic step progression.

The incorporation of redundancy effectively corrects comparator decision errors typically caused by four key factors: parasitic resistance and inductance in power/ground routing that induce supply voltage ripple, the limited driving capability of the V_REF buffer, the excessive settling time from large RC time constants in the CDAC capacitor switch network, and intrinsic comparator noise. This redundancy creates multiple digital code representations for single analog values (e.g., value 4 mapping to both 01000 and 00111 codes) through strategically allocated decision threshold overlap, thereby establishing error tolerance margins that absorb timing uncertainties and noise-induced metastability while maintaining conversion accuracy. In the CDAC array of this design with redundancy insertion, the redundancy allocation per bit is tabulated as shown in

Table 2. Redundancy per bit.

	C13	C12	C11	C10	C9	C8	C7	C6	C5	C4	C3	C2	C1	C0
Weight accumulation result	2048	1024	512	256	256	128	64	32	16	8	8	4	2	1
Weight accumulation result of LSB	2311	1287	775	519	263	135	71	39	23	15	7	3	1	0
Redundancy (LSB)	264	264	264	264	8	8	8	8	8	8	0	0	0	0

.

The unit capacitance C_u in the CDAC is bound by two critical factors:

• kT/C noise constraint

The quantization noise of an ADC must exceed its sampling thermal noise.

$${\displaystyle \frac{kT}{C_{unit}}}\le {\displaystyle \frac{V_{REF}^2}{12·2^{2N}}}\Rightarrow C_{unit}\ge {\displaystyle \frac{12·2^{24}kT}{V_{REF}^2}}=96.4 \mathrm{fF}.$$

(13)

2.

Capacitor mismatch

Process variations and parasitic capacitance introduced during the layout design inevitably cause capacitor mismatch. The maximum standard deviation of integral nonlinearity (INL) in the ADC is given by the following:

$${\sigma }_{\mathrm{INL},\max }=\sqrt{2^{\mathrm{N}-1}}{\displaystyle \frac{{\sigma }_u}{\mathrm{Cu}}}\mathrm{LSB}.$$

(14)

The maximum allowable standard deviation of integral nonlinearity (${\sigma }_{\mathrm{INL},\max }$) in an ADC must satisfy the following:

$$3{\sigma }_{INL,max}=3\sqrt{2^{N-1}}\left({\displaystyle \frac{{\sigma }_u}{C_u}}\right)LSB<0.5LSB.$$

(15)

Simplification yields:

$${\displaystyle \frac{{\sigma }_u}{C_u}}<{\displaystyle \frac{1}{6\sqrt{2^N-1}}}.$$

(16)

Solving the equation yields:

$${\displaystyle \frac{{\sigma }_u}{C_u}}<0.37\%.$$

(17)

The process library’s MIM (Metal–Insulator–Metal) capacitor with a minimum value of 127.36 fF demonstrates a 0.22% mismatch (ΔC/C) under Monte Carlo simulation, as illustrated in Figure 11, comfortably meeting the matching requirement for high-precision analog design.

2.4. Dynamic Comparator Design

The conventional StrongARM latch employs a single-stage topology, delivering rapid response times and zero static power consumption for inherently low-power operation [15]. However, the stacked configuration of the latch and input pair introduces severe kickback noise—the complementary output transitions directly couple to the input nodes through the C_GS of the input transistors, creating significant signal disturbance that degrades sampling accuracy in high-resolution ADCs [16].

The double-tail architecture decouples the preamplifier stage from the latch, significantly reducing kickback noise through two-stage isolation—yet it incurs higher power consumption as both differential load capacitors in the preamp stage discharge fully from V_DD to GND during each comparison cycle.

The adopted Elzakker architecture, as illustrated in Figure 12, improves upon the double-tail design by inserting cross-coupled PMOS pairs (M₉, M₁₀) in the latch stage while eliminating the tail current source, achieving direct power savings through two key mechanisms [17]:

• Static Current Elimination

The proposed design eliminates the constant tail current dissipation characteristic of conventional double-tail latches, converting the structure into a fully dynamic implementation with zero static power consumption.

2.

Controlled Regeneration

PMOS pairs M9/M10 accelerate decision-making during metastability, reducing dead-zone time by 30% versus passive loads. This maintains kickback isolation (comparable to double-tail) via retained preamp decoupling.

The operational sequence begins with the reset phase, where M9/M10 precharge internal nodes. In the evaluation phase, the input differential modulates the preamp outputs. Finally, during the regeneration phase, cross-coupled inverters resolve the digital level.

The designed comparator circuit achieves a 0.12 μs resolution time for discriminating 0.12 mV (½LSB @12-bit) signals, with Cadence Virtuoso transient noise simulations verifying an input-referred noise of 69.5 μV RMS—meeting the critical requirements for a 12-bit SAR ADC operating at 320 kS/s. Key validation results include the following:

• Noise Compliance

The measured 69.5 μV noise, representing 0.58 × LSB (where LSB = 120 μV at 1 V range), ensures quantization-limited performance, with its composition dominated by the input pair thermal noise (~60%) and latch metastability-induced uncertainty (~40%).

2.

Monte Carlo Offset Analysis

As illustrated in Figure 13, the simulated offset voltage exhibits 3σ < 0.5LSB (120 μV), achieved through large input devices for mismatch reduction and auto-zeroing during the reset phase.

3.

Speed–Noise–Power Tradeoff

A delay of 0.12 μs ensures a 16× oversampling margin for 320 kS/s operation and consumes 8.982 μW @1.8 V, optimized via dynamic bias control.

2.5. SAR Logic Array Design

The proposed SAR control logic utilizes dynamic circuit techniques to enhance power efficiency, differing from conventional implementations such as ring counters with shift registers (static CMOS) or N flip-flops with combinational logic. As illustrated in Figure 14, this design incorporates event-driven operation that activates only during comparison phases, a dynamic latch array to store comparator decisions until the next reset, and non-overlapping clock control to prevent shoot-through currents.

The timing diagram of the SAR dynamic logic unit operation is shown in Figure 15. During the sampling phase, when the D signal remains at a low logic level and the Valid signal transitions to a high logic state, the CLK signal asserts a high logic level, thereby pulling the voltage at node Q to ground potential. In this configuration, both the positive input (Pi) and negative input (Ni) of the comparator remain at low logic levels, causing the comparator’s differential outputs Outn (negative output) and Outp (positive output) to settle in high-logic states. During the quantization phase, the Sample signal transitions to low logic, while the Valid signal remains highly asserted during the comparator’s comparison phase. The CLK voltage is discharged to low logic through transistors M2 and M3. Upon completion of the comparator’s comparison operation, one of the differential outputs (Outn or Outp) transitions to low logic. If Outn is driven to low logic, transistor M9 is activated, charging the Pi node to high logic, while the Ni node retains its low logic state. When the Pi node transitions to high logic, transistors M14 and M8 are activated, further charging the Pi node and discharging the Ni node, thereby latching the current comparison result. Subsequently, regardless of changes in the comparator’s outputs, the latched result remains stable until a reset signal assertion occurs. During the reset phase of the comparator, the Valid signal is de-asserted (transitioning to low logic). The voltage at node Q is charged to high logic through transistors M4 and M5. This high-logic state at node Q propagates to the subsequent logic gate, triggering a state transition in the downstream circuitry, thereby ensuring that each comparison result is latched.

The circuit augments the conventional architecture by integrating two bypass MOSFETs (M₈ and M₁₁) and two additional inverters. Upon the comparator’s decision, this configuration enables faster result latching, relaxes the requirements for enabling signal transmission circuitry, and mitigates logic errors.

Compared to static implementations, this architecture significantly reduces clock network power, decreases control signal fan-out, and minimizes parasitic capacitance at critical nodes. The absence of continuous DC paths and reduced switching activity collectively enable sub-μW power consumption while ensuring robust metastability handling.

3. Layout Implementation and Post-Layout Simulation Results

The proposed SAR ADC was designed using 180 nm CMOS technology, achieving a compact core area of 0.2475 mm² through meticulous layout optimization. Figure 16 illustrates the symmetrical floorplan with capacitor arrays distributed across the left–right peripheries, while the central placement of critical analog modules—including bootstrapped switches, dynamic comparators, and unity-gain buffers—minimizes interconnected parasitics. The SAR logic block is strategically positioned adjacent to the capacitive DAC array to reduce switching noise coupling. Analog signal routing employs current-density optimized traces (4 mA/μm width) with differential symmetric paths, maintaining a <5% length mismatch through careful metal layer planning. Proximity grouping of the comparator, sampling switches, and CDAC array achieves effective mitigation of RC delay variations.

As illustrated in

Table 3. Simulation performance summary and comparison with state-of-the-art systems.

	[18]	[19]	[20]	[21]	This Work
Topology	IADC2-1	SAR	SAR	SAR	SAR
Process (nm)	180	90	180	180	180
Sampling frequency (Hz)	768 k	20 M	1 k	1 M	320 k
Supply (V)	5	1.8	0.5/1	1.8	1.8
Power (W)	2.95 m	31.6 μ	35.9 μ	40.5 μ	27.9 μ
Peak input (V)	-	500 m	1	-	1
Bandwidth (Hz)	0.5 k	1.25 M	5 k	50 k	10 k
Resolution (bits)	32	5	12	8	14
ENOB (bits)	18.16	4.53	11.12	7.7	13.44
SINAD (dB)	111.1	29	68.7	48.15	82.67
SFDR (dBc)	-	-	83	55.52	89.62

, the SAR ADC developed in this study exhibits remarkable performance metrics tailored for BCI applications, demonstrating superior precision and energy efficiency, as well as dynamic characteristics essential for high-fidelity acquisition of weak biological signals. The design achieves an ENOB of 13.44 bits, surpassing traditional SAR ADCs (e.g., 11.12 bits in [18]) and CT-DSM architectures (9.62 bits), thereby minimizing quantization-induced distortion. Under coherent sampling conditions (Fin = 9.6875 kHz, Fs = 320 kS/s), the ADC demonstrates a SINAD of 82.67 dB and an SFDR of 89.62 dB, as illustrated in Figure 17. The performance sweep results of ENOB and SNR as they vary with input frequency are shown in Figure 18, and the results of SNR and SINAD as they vary with input amplitude are shown in Figure 19, further validating SAR ADC’s capability to maintain high signal integrity and suppress harmonic distortion in real-world operating scenarios.

From a power efficiency perspective, the proposed SAR ADC consumes only 27.9 µW, significantly less than comparable designs (e.g., 40.5 µW in [19]), and is substantially more efficient than IADC2-1 (2.95 mW) [20]. Detailed power analysis reveals that the comparator dominates power consumption at 8.982 μW (32.1% of the total), followed by CDAC switching at 8.946 μW (32.0%), clock distribution at 9.0936 μW (32.5%), and SAR logic at 0.936 μW (3.3%). This optimized power distribution ensures efficient energy utilization, which is critical for extending the operational lifetime of implantable devices and meeting the stringent energy constraints of long-term BCI monitoring. Additionally, the ADC’s bandwidth of 10 kHz accommodates the full spectrum of neural signals (0.5–5 kHz) while supporting higher-frequency signal acquisition, such as electromyographic data or motion artifact monitoring, thereby enhancing system versatility.

Considering the LDO (Low-Dropout Regulator) required for subsequent on-board testing, the circuits designed in this project all operate with a 1.8 V supply voltage, similar to those described in references [19,21], so the requirements for the LDO are quite comparable. Compared to the LDO in [19], this design may have slightly higher power consumption, though it will remain significantly lower than the power consumption reported in [20]. Except for reference [18], which mentions an input capacitance of 2 pF, other references do not provide detailed descriptions of this parameter. Reference [18] uses MOM (Metal–Oxide–Metal) capacitors, where the size of the unit capacitor is 1 pF. Such a small capacitor may introduce the risk of capacitor mismatch. Since the minimum capacitor available in the process library used for this design is a MIM (Metal–Insulator–Metal) capacitor with a value of 127.36 fF, the input capacitance of the circuit is 17 pF. Comparison shows that the area utilization efficiency of the CDAC in this paper is significantly higher than that of the CDAC structure in reference [18]. Compared to the design in [18], this may require the preceding AFE (Analog Front-End) to have stronger driving capability and consume more power.

Designed and post-layout-simulated using a 180 nm process, the proposed SAR ADC benefits from compatibility with established biomedical chip manufacturing technologies, reducing production costs and facilitating integration into multi-channel systems. Moreover, it outperforms traditional SAR ADCs (e.g., the 11.12-bit ENOB in [21]) in terms of resolution, dynamic range, and power consumption, addressing the critical requirements of high-precision neural signal processing. In conclusion, the proposed SAR ADC, through its optimized architecture and circuit design, delivers high resolution and a dynamic performance while maintaining ultra-low power consumption, positioning it as a robust option for long-term implantable monitoring and high-accuracy signal acquisition in BCI systems, with significant potential for widespread adoption in biomedical applications.

4. Conclusions

This paper presents a low-power, high-resolution SAR ADC tailored for BCI systems. Leveraging a segmented monotonic switching scheme, dynamic logic architecture, and an optimized CDAC, the design achieves a 13.44-bit ENOB and 27.9 μW of power consumption at a supply voltage of 1.8 V, with a compact core area of 0.24 mm². The experimental results demonstrate an SNDR of 81.94 dB and an SFDR of 91.69 dBc at a sampling rate of 320 kS/s, making it well suited for neural signal acquisition and biomedical sensing applications. While the 180 nm CMOS process imposes limitations on voltage scaling and current leakage reduction, the design maintains a competitive performance in power efficiency and area optimization. Future work, including process migration to advanced nodes and further circuit-level enhancements, is expected to extend SAR ADC’s applicability to implantable medical devices and portable instrumentation.