# A Bridged-Switch Energy-Efficient Switching Scheme for Successive Approximation Register Analog-to-Digital Converters with a Low-Complexity Capacitor Drive Circuit

^{1}

^{2}

^{*}

## Abstract

**:**

_{cm}; thus, the last comparison consumes little switching energy. The proposed switching scheme achieves an average switching energy value of 47.5 CV

^{2}

_{ref}, which is 96.52% lower than that of the conventional capacitor switching scheme and reduces the area by 75%. The other major circuit modules employed are bootstrapped switches, a fully dynamic comparator, and dynamic SAR logic. The proposed ADC was simulated under the conditions of 180 nm CMOS process and 1 MS/s, resulting in a 9.8-bit effective number of bits (ENOB), a signal-to-noise and distortion ratio (SNDR) of 60.76 dB, a spurious-free dynamic range (SFDR) of 69.85 dB, a power consumption of 14.7 μW, and a figure of merit (FoM) of 16.55 fJ/conv.-step.

## 1. Introduction

_{ref}/2. VBSS [10] and SMS [11] reduce the common-mode shift while lowering the required switching energy, but with high dependence on the accuracy of V

_{cm}. Tri-level [12] and VMS [13] are highly energy-efficient, but they have high control logic complexity and tend to increase the digital power consumption of the ADC. Therefore, it is necessary to design a combined energy-efficient switching scheme without increasing the complexity of the control logic while reducing the common-mode shift and decreasing the dependence on the accuracy of V

_{cm}.

_{cm}, the switching energy is further reduced. The proposed switching strategy has an average switching energy value of 47.5 CV

^{2}

_{ref}, which reduces switching energy consumption by 96.52% while reducing the area by 75%.

## 2. The Proposed SAR ADC

#### 2.1. The Proposed Switching Scheme

_{ref}. The input signal is sampled to the top plate of the capacitor array through a sampling switch. When sampling is complete, the sampling switch is turned off. The comparator can then directly perform the first comparison and output the comparison result (D

_{1}) without consuming switching energy (E

_{1}= 0). The voltage at the time of comparison is

_{1}= 1, in the negative-conversion capacitor array, the reference voltage of the maximum capacitor in the main array is switched from GND to V

_{ref}; moreover, the reference voltage of the other capacitors remains constant. If D

_{1}= 0, in the positive-conversion capacitor array, the reference voltage of the maximum capacitor in the main array is switched from GND to V

_{ref}, and the reference voltage of the other capacitors remains unchanged. Consequently, the low-side voltage increases (V

_{ref}/2), and the high-side voltage remains unchanged. The second comparison is performed, and the comparator outputs the result of the second comparison (D

_{2}). The second comparison does not consume switching energy either (E

_{2}= 0).

_{1}D

_{2}= 11 or 00, in the subarray on the higher-voltage side, the reference voltage of capacitors is switched from V

_{ref}to GND, and in the subarray on the lower-voltage side, the reference voltage of capacitors is switched from GND to V

_{ref}; then, closing the bridge switch between the main array and subarray allows the capacitor array to undergo charge redistribution. If D

_{1}D

_{2}= 10 or 01, the bridge switches are closed directly. As a result, the high-side voltage decreases (V

_{ref}/4) and the low-side voltage does not change. In the third comparison, the capacitor array switching energy is

^{th}comparisons: Based on the output of the previous step, on the higher-voltage side of the main array, the reference voltage of the corresponding capacitor is switched from V

_{ref}to GND, while the reference voltage of the other capacitors remains constant; then, the comparator performs the comparison and outputs the comparison results. The ADC repeats the process until (N-1) comparisons are completed. The switching energy for each comparison, from the 4th to the (N-1)

^{th}, is computed as follows:

^{th}comparison: If D

_{N-1}= 1, in the unit array of the positive-conversion capacitor array, the reference voltage of the unit capacitor is switched from V

_{ref}to V

_{cm}, while the reference voltage of the other capacitors remains constant. If D

_{N-1}= 0, the reference voltage of the capacitor in the unit array of the negative-conversion capacitor array is switched from V

_{ref}to V

_{cm}, and the reference voltage of the other capacitors remains unchanged. At the N

^{th}comparison, the capacitor array switching energy is

_{ref}/4. The voltage conversion flow chart of the 10-bit SAR ADC is shown in Figure 4b. Only after the first comparison does the voltage on the low-voltage side increase (V

_{ref}/2), and each subsequent comparison is a voltage drop (V

_{ref}/2

^{i}) on the high-voltage side.

#### 2.2. Drive Circuit for DAC Capacitor Array

_{ref}and GND; the main array drive circuit only needs to pass through the CMOS inverter, and the capacitors in the subarray need to be controlled with AND and NAND gates, respectively. The reference voltages of the capacitors in the unit array are V

_{cm}and GND, and the drive circuit adopts a hybrid structure comprising a CMOS inverter and a CMOS transmission gate.

#### 2.3. Bridged Switch for DAC Capacitor Array

#### 2.4. Sampling Switch

#### 2.5. Comparator

#### 2.6. SAR Logic

## 3. Results

^{2}

_{ref}, which is 96.52% lower than that of the conventional switching scheme. Figure 11 shows the switching energy of several switching schemes [8,9,10,11,12,13] for 10-bit output code.

_{ref}/2 common-mode shift reduces the linearity of ADCs. VBSS [10] proposes a bidirectional single-side technique based on V

_{cm}that uses symmetrical switching to keep a constant common-mode voltage even after the first comparison, reducing the number of common-mode shifts. SMS [11] proposes an overall shift-monotonic technique that switches one side of the capacitance to the same reference voltage in the second-comparison step without generating switching energy and a common-mode shift of only V

_{ref}/4. Tri-level [12] entails the multiple switching of the reference voltage of the same capacitor, effectively reducing the switching energy required and the area used. VMS [13] combines top-plate sampling techniques and shift-monotonic techniques from capacitor arrays, further reducing the switching energy required.

_{cm}accuracy, which increases the power consumption of the SAR ADC digital module. In this work, the proposed switching scheme makes use of top-plate sampling, charge recycling, and bridge switching; reduces switching energy consumption without increasing the complexity of the control logic; and has a common-mode shift of only V

_{ref}/4.

## 4. Conclusions

_{cm}. As a result, the DAC has lower switching-energy consumption, low drive circuit complexity, and low dependence on V

_{cm}. In the proposed switching scheme, the average switching energy is 47.5 CV

^{2}

_{ref}, which is 96.52% lower and reduces the area by 75% compared with the conventional switching scheme. The key circuit modules to reduce the power consumption of the SAR ADC are a full dynamic comparator, bootstrapped switches, and dynamic SAR logic. The proposed 10-bit SAR ADC was simulated under the conditions of 180 nm CMOS process and 1 MS/s, resulting in an SNDR of 60.76 dB, an SFDR of 69.85 dB, power consumption of 14.7 μW, and an FoM of 16.55fJ/conv.-step. In this paper, although bridge switches are used, the ADC is not designed as a bit-adjustable ADC. So, in future work, an ADC could be designed as a bit-adjustable ADC by using bridge switches to extend the application area of ADCs.

## Author Contributions

## Funding

## Institutional Review Board Statement

## Informed Consent Statement

## Data Availability Statement

## Conflicts of Interest

## Nomenclature

## References

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**Figure 4.**Diagram of voltage change: (

**a**) waveform of the proposed switching scheme; (

**b**) flow chart of the 10-bit SAR ADC.

Switching Scheme | Average Switching Energy (CV ^{2}_{ref}) | Energy Saving | Area Reduction | Control Logic Complexity | Dependency on the Accuracy of V _{cm} | Common-Mode Shift |
---|---|---|---|---|---|---|

Conventional | 1363.3 | Reference | Reference | Low | No | 0 |

SC [7] | 852.3 | 37.48% | 0% | Low | No | 0 |

MCS [8] | 255.5 | 81.26% | 50% | Low | No | V_{ref}/2 |

RFM [9] | 128 | 90.61% | 74.7% | Low | No | V_{ref}/2 |

VBSS [10] | 69.08 | 94.93% | 75% | Low | Very high | V_{ref}/4 |

SMS [11] | 63.75 | 95.32% | 75% | Low | Very high | V_{ref}/4 |

Tri-level [12] | 42.41 | 96.89% | 75% | High | Very high (all bits except MSB) | V_{ref}/2 |

VMS [13] | 31.88 | 97.66% | 75% | High | Very high (all bits except MSB) | V_{ref}/4 |

Proposed | 47.5 | 96.52% | 75% | Low | Very low (only LSB) | V_{ref}/4 |

Parameter | [24] * | [25] * | [26] | [27] * | [6] * | This Work * |
---|---|---|---|---|---|---|

Year | 2016 | 2017 | 2019 | 2020 | 2022 | 2023 |

Process (nm) | 180 | 180 | 55 | 130 | 180 | 180 |

Resolution (bits) | 8 | 10 | 12 | 8 | 10 | 10 |

Sampling rate (MS/s) | 1 | 1 | 1 | 1 | 1 | 1 |

Supply voltage (V) | 1.2 | 1.8 | 0.5/0.9 | 1.2 | 1 | 1.8 |

SNDR (dB) | 48.05 | 61 | 68 | 47.12 | 57.81 | 60.76 |

SFDR (dB) | - | 79.8 | - | 57.36 | 68.63 | 69.85 |

ENOB (bits) | 7.69 | 9.84 | - | 7.54 | 9.31 | 9.8 |

DNL (LSB) | −0.14/0.68 | - | −0.58/0.60 | −0.24 /0.26 | - | −0.16/0.14 |

INL (LSB) | −0.31/0.48 | - | −0.81/0.58 | −0.28/0.26 | - | −0.25/0.11 |

Power consumption (μW) | 8.14 | 35.3 | 30 | 11. 56 | 15.25 | 14.7 |

FoM ^{1} (fJ/conv.-step) | 39 | 38.52 | 24.5 | 62.11 | 20 | 16.55 |

^{1}FoM = Power/(2

^{ENOB}× f

_{sampling}).

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**MDPI and ACS Style**

Hu, Y.; Tang, B.; Chen, C.; Hu, L.; Huang, Q.; Cai, J.; Xie, J.; Li, B.; Wu, Z.
A Bridged-Switch Energy-Efficient Switching Scheme for Successive Approximation Register Analog-to-Digital Converters with a Low-Complexity Capacitor Drive Circuit. *Appl. Sci.* **2023**, *13*, 12897.
https://doi.org/10.3390/app132312897

**AMA Style**

Hu Y, Tang B, Chen C, Hu L, Huang Q, Cai J, Xie J, Li B, Wu Z.
A Bridged-Switch Energy-Efficient Switching Scheme for Successive Approximation Register Analog-to-Digital Converters with a Low-Complexity Capacitor Drive Circuit. *Applied Sciences*. 2023; 13(23):12897.
https://doi.org/10.3390/app132312897

**Chicago/Turabian Style**

Hu, Yunfeng, Bin Tang, Chaoyi Chen, Lexing Hu, Qingming Huang, Jiaqi Cai, Jinbo Xie, Bin Li, and Zhaohui Wu.
2023. "A Bridged-Switch Energy-Efficient Switching Scheme for Successive Approximation Register Analog-to-Digital Converters with a Low-Complexity Capacitor Drive Circuit" *Applied Sciences* 13, no. 23: 12897.
https://doi.org/10.3390/app132312897