Performing Arithmetic Operations with Locally Homogeneous Spiking Neural P Systems
Abstract
:1. Introduction
2. Related Research
2.1. Spiking Neuronal P System
- O = {a} is the singleton alphabet, and a is spiking;
- σ1, σ2, …, σm are neurons of the form σi = (ni, Ri), 1 ≤ i ≤ m, ni is the initial number of spiking in the neuron σi at the beginning of the calculation, ni ≥ 0. Ri is the finite set of rules in each neuron. Ri has two forms of rules (we collectively refer to them as spiking rules):
- ①
- E/ac → ap; d, where E is a regular expression over O, c ≥ 1, p ≥ 1, and c ≥ p, d indicates delayed time, d ≥ 0;
- ②
- E′/as → λ, s ≥ 1, for any rule E/ac → ap; d from any Ri, all meet the condition L(E)∩L(E′) = Φ;
- syn is the set of synapses. The element in syn is an ordered pair of elements shaped like (i, j). (i, j) indicates neurons σi to σj are connected by synapses, with i, j ∈ {1, 2, …, m}, i ≠ j;
- in, out ∈ {1, 2, …, m} indicate the input and output neurons.
- (1)
- O = {a};
- (2)
- σin1 = (0, Rin);
- (3)
- σin2 = (0, Rin);
- (4)
- σAdd = (0, RAdd);
- (5)
- syn = {(in1, Add), (in2, Add)};
- (6)
- in1 = Input1, in2 = Input2;
- (7)
- out = Add;
- (8)
- Rin = {aa}, Radd = {aa, a2/, a3/a2a}.
2.2. Related Literature
3. An Locally Homogeneous Spiking Neural P System for Addition
3.1. An LHSNP System with 1 Input Neuron for 2 Numbers Addition
- (1)
- O = {a};
- (2)
- σin = (0, Raux);
- (3)
- σaddend = (0, Raddend);
- (4)
- σaux1,i = (1, Raux), i = 0, 1;
- (5)
- σaux1,i = (0, Raux), i = 2, …, k + 1;
- (6)
- σaux2,i = (0, Raux), i = 0, 1;
- (7)
- σaux3 = (0, Raux);
- (8)
- σaux4 = (0, Raux4);
- (9)
- σsumi = (0, Rsum), i = 0, …, k − 1;
- (10)
- σAdd = (0, RAdd);
- (11)
- syn = {(in, aux3), (in, addend), (addend, Add), (aux1,1, aux1,0), (aux1,k + 1, aux2,0), (aux1,k + 1, aux2, 1), (aux2,0, aux3), (aux2,1, aux3), (aux2,0, addend), (aux2,1, addend), (aux2,0, aux1,0), (aux2,0, aux1,1), (aux2,1, aux4), (aux4, Add), (aux3, sumk−1), (sum0, Add)}∪{aux1,i, aux1,i + 1}|i ∈ {0, 1, …, k}∪{sumi + 1, sumi}|i ∈ {0, 1, …, k − 2};
- (12)
- in = Input;
- (13)
- out = Add.
- ①
- Input Auxiliary Module
- (1)
- At t = 0 time slice, there is 1 spiking in σaux1,0 and σaux1,1.
- (2)
- t = 1 to k + 1, σaux1,0 and σaux1,1 send 1 spiking to each other and maintain 1 spiking. At the same time, σaux1,1 send 1 spiking to σaux1,2, which will follow the neurons σaux1,3, σaux1,4, …, σaux1, k + 1 sequential transmission. The input auxiliary module has no spiking output. At t = k + 1 time slice, there is 1 spiking in homogeneous neurons in the input auxiliary module.
- (3)
- t = k + 2 to 2k + 3, the input auxiliary module continues to generate spiking output. σaux2,0 send 1 spiking to σaux1,0 and σaux1,1 at each time slice to prevent σaux1,0 and σaux1,1 from continuously generating spiking. At t = k + 3 to 2k + 2 time slice, the spikings in σaux1,2, σaux1,3, …, σaux1,k + 1 are sequentially cleared. At t = 2k + 3 time slice, the spikings in σaux2,0 and σaux2,1 are cleared. And there are no rules that can be fired in all neurons in the input auxiliary module.
- ②
- Summand Input
- (1)
- t = 1 to k, the spiking corresponding to each summand bit is received by σin in order from low to high. At t = k time slice, the input of the summand is completed. These spikings follow σaux3, σsumk−1, σsumk−2, …, σsum0 sequential transmission to σAdd.
- (2)
- t = k + 1 to k + 2, the summand cache module does not generate spiking output. At t = k + 2 time slice, the bits of the summand are stored in σsum0, σsum1, …, σsumk−1 in order from low to high. At the same time, σaux3 starts continuous reception spikings from σaux2,0, σaux2,1, and σin. Until 2k + 3 time slice, these spikings are piled up in σaux3.
- (3)
- t = k + 3 to 2k + 2, the summand cache module continuously generates spiking outputs. At each time slice, σsum0 sends the corresponding spiking of each summand to σAdd in sequence. At the same time, the spiking in σsumk−1, σsumk−2, …, σsum0 are sequentially cleared. Starting from 2k + 2 time slice, there are no rules that can use in the transmit addend neurons.
- ③
- Addend Input
- (1)
- t = 1 to k + 2, σaddend does not generate spiking output. During this time, σaddend received spiking sent by σin is consume by forgetting rule a → ƛ.
- (2)
- t = k + 1 to 2k, the spiking corresponding to each binary addend is transmitted in order from low to high send to σin. At t = 2k time slice, the addend input is completed. These spikings through σaddend transferred to σAdd.
- (3)
- t = k + 2 to 2k + 1, σaddend receives spikings sent by σin. At each time slice, σAdd also receives 2 spikings sent by σaux2,0 and σaux2,1. With the assistance of σaux2,0 and σaux2,1,σaddend send spiking to σAdd transmission addend. During this time slice, if there are 2 spikings in σaddend, σaddend use the forgetting rule a2 → ƛ consuming 2 spikings and sending 0 spikings out. Indicates that the binary addend passed is 02. If there are 3 spikings in σaddend, firing rule a3 → a, consume 3 spikings and send 1 spiking out, indicating that the binary addend passed is 12. At t = k + 3 time slice, the spiking corresponding to the lowest bit of the addend is sent to σAdd. At t = 2k + 2 time slice, the spiking corresponding to the highest bit of the addend is sent to σAdd.
- ④
- Data Overflow Detection
- (1)
- t = 1 to k + 1, σaux4 has no spiking input.
- (2)
- t = k + 2 to 2k + 2, σaux4 received 1 spiking sent by σaux2,1 at each time slice. These spikings are stacked in σaux4. At t = 2k + 2 time slice, σaux4 accumulated k + 1 spikings.
- (3)
- t = 2k + 3, σAdd received four spikings sent by σaux4 firing rule ak + 1 → a4. At the same time, σaux4 received 1 spiking sent by σaux2,1, which accumulates in σaux4 until the system stops. If there are 4 spikings in σAdd, it means that the calculation result does not overflow. If there are 5 spikings in σAdd, it indicates that the calculation result overflows. σAdd use the rule a5 → a4 to send 4 spikings to the environment.
- ⑤
- Addition Operation
- (1)
- Rule a → a indicates performing addition operation: 12 + 02 = 12 or performing addition operation 02 + 02 + 12 = 02(there are carry reservations in σAdd). There are two types of sources for this spiking in σAdd. Case 1: This 1 spiking comes from σsum0 or σaddend. It indicates that the two binary addends input are 0 and 1. Case 2: This spiking comes from reserved in σAdd, and the two addends are 0. At this point, σAdd is fired using rule a → a, consumes 1 spiking and generates 1 spiking, and sends it to the environment.
- (2)
- Rule a2/a → ƛ indicates performing an addition operation: 12 + 12 = 102, or 12 + 02 + 12 = 102 (there is carry reservation in σAdd). There are two sources of these two spikings in σAdd. Case 1: these two spikings come from σsum0 and σaddend. This indicates that the two binary addends input are 1 and 1. Case 2: one spiking comes from σsum0 or σaddend, another spiking from σAdd (i.e., carry 1). At this point, σAdd is fired using rule a2/a → ƛ, consume 1 spiking, retain 1 spiking (i.e., carry 1), and send 0 spiking to the environment.
- (3)
- Rule a3/a2 → a indicates performing an addition operation: 12 + 12 + 12 = 112. These 3 spikings come from σsum0 and σaddend (the 2 binary addends input are 1 and 1) and 1 spiking reserved in σAdd (i.e., carry 1). At this point, σAdd is fired using rule a3/a2 → a, consumes 2 spikings, retains 1 spiking (i.e., carry 1), generates 1 spiking, and sends it to the environment.
- (4)
- Rule a5 → a4 indicates data overflow. Among these 5 spikings, 4 spikings come from σaux4, and 1 spiking comes from the two addends with the highest bits after calculation retained in σAdd (i.e., carry 1). At this point, rule a5 → a4 is fired in σAdd, which consumes 5 spikings and generates 4 spikings to be sent to the environment.
- ①
- Input Auxiliary Module
- (1)
- t = 1 to 9, the input auxiliary module does not generate spiking output. At each time slice, σaux1,0 and σaux1,1 continuously send spiking to each other, while σaux1,1 continuously sends spiking to σaux1,2. This spiking along σaux1,3, σaux1,4, …, σaux1,9, σaux2,i (i = 0, 1) sequential transmission. At t = 9 time slice, all neurons in the input auxiliary module have 1 spiking.
- (2)
- t = 10 to 19, σaux2,0 continuously sending spiking to σaux1,0 and σaux1,1. At t = 10 time slice, σaux1,0 and σaux1,1 also received 1 spiking sent by each other. These spikings are stacked in σaux1,0 and σaux1,1. At t = 11 time slice, σaux1,0 and σaux1,1 stop generating spiking output. At t = 10 to 19 time slices, σaux2,0 and σaux2,1 continuously generate spiking output. At t = 11 to 19 time slices, the spikings in σaux1,2, σaux1,3, …, σaux1,9, σaux2, i (i = 0, 1) are sequentially cleared. At t = 19 time slice, there are 11 spikings stacked in σaux1,0 and σaux1,1. And there is no spiking in σaux1,3, σaux1,4, …, σaux1,9, σaux2, i (i = 0, 1).
- ②
- Summand Input
- (1)
- t = 1 to 8, the spiking 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 corresponding to the summand from low to high are sequentially received by σin. These spikings along the σaux3, σsum7, …, σsum0 transferred to σAdd. At t = 1 time slice, spiking 1 corresponding to the lowest bit of the summand is received by σin. At t = 8 time slice, the spiking 0 corresponding to the highest bit of the addend is received by σin.
- (2)
- t = 2 to 9, σin sends spiking to both σaux3 and σaddend. σaddend uses forgetting rule a → ƛ to consume these spiking.
- (3)
- t = 10, the summand is stored in ascending order from low to high in the σsum0, σsum1, …, σsum7. There are 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 spikings in σsum0, σsum1, …, σsum7.
- (4)
- t = 11 to 18, the spiking corresponding to each summand is sequentially in order from low to high received by σAdd.
- ③
- Addend Input
- (1)
- t = 1 to 10, there is no spiking output in σaddend.
- (2)
- t = 9 to 16, the corresponding spiking 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 of the addend from low to high are sequentially represented received by σin. These spikings through σaddend transferred to σAdd. At t = 9 time slice, the spiking 0 corresponding to the lowest bit of the addend is received by σin. At t = 16 time slice, the spiking 0 corresponding to the highest bit of the addend is received by σin.
- (3)
- t = 10 to 17, there are 2, 3, 3, 2, 2, 2, 2, 2, 2 spikings in σaddend at each time slice. These spikings come from σaux2,0, σaux2,1, and σin. During the time slice t = 10 to 17, σaux3 receives spikings sent by σaux2,0, σaux2,1 and σin at each time slice. At t = 17 time slice, there are 18 spikings stacked in σaux3.
- (4)
- t = 11 to 18, the spiking in σsum7, σsum6, …, σsum0 are sequentially cleared.
- ④
- Overflow Monitoring
- (1)
- t = 0 to 9, there is no spiking input in σaux4.
- (2)
- t = 10 to 18, σaux4 receives 1 spiking sent by σaux2,1 at each time slice. And stack these spiking in σaux4. At t = 18 time slice, 9 spikings stacked in σaux4.
- (3)
- At t = 19 time slice, σaux4 sends 4 spikings after using rule a9 → a4 to σAdd. At this point, the highest bit of the two addends have been calculated and no carry has been generated. There are 4 spikings in σAdd, no rules can be use, and there is no data overflow. At the same time, σaux4 received 1 spiking sent by σaux2,1, which is stacked in σaux4.
- ⑤
- Addition Operation
- (1)
- t = 1 to 10, there is no spiking input in σAdd.
- (2)
- t = 11 to 18, the spiking corresponding to each of the two binary addends is sent in sequence from low to high to σAdd. At t = 11 time slice, σAdd received the spiking corresponding to the lowest order of two addends. At this time, there is 1 spiking in σAdd. At t = 18 time slice, σAdd received spiking corresponding to the highest bit of 2 addends, there are 0 spiking in σAdd.
- (3)
- t = 12 to 19, it is the effective output time of ПAdd2. During this time slice, the calculation results are sent to the environment in order from low to high. In each time slice, the environment received 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 spikings in sequence.
- (4)
- t = 19, σAdd received 4 spikings sent by σaux4. At this time, there are no rules that can be used in ПAdd2, and the system operation stops. The system ПAdd2 calculates that the sum of 000001012 and 000001102 is 000010112, and the calculation result is correct.
3.2. An LHSNP System with 1 Input Neuron for n-addition
- ①
- Input Assistance Module
- (1)
- Add an auxiliary neuron σaux5. σaux5 and σaux1,0 connected to each other. And σaux5 is also connected to σaux1,1. σaux5 controls σaux1,0 and σaux1,1 to stop generating spiking. σaux1,0 send 1 spiking to σaux1,1 while also sending 1 spiking to σaux5. These spikings accumulate in σaux5 until the number of spiking reaches (n − 1)k. When there are (n − 1)k spikings, σaux5 is fired and sends spiking to σaux1,0 and σaux1,1 to stop generating spiking output.
- (2)
- Add a connection between σAdd and σsumk−2. σAdd send the calculation results to both the environment and σsumk−2 for accumulate plus.
- (3)
- Add overflow monitoring neuron σOF. If data overflow, σOF sends 4 spikings to some neurons in the system truncation spiking transmission. The aim is to stop the system.
- (4)
- Modify the conditions for firing σaux4. If the number of stacked spiking in σaux4 reaches k, then firing σaux4 sends 4 spikings to σAdd to mark the highest bit of the 2 addends in σAdd.
- ②
- The First Addend Input
- (1)
- t = 1 to k, the spiking corresponding to the first binary addend is received by σin in order from low to high. At each time slice, these spikings are transmitted sequentially along σaux3, σsumk−1, σsumk−2, …, σsum0. At the same time, σaddend also receives spikings from σin at each time slice. These spikings are consumed by rule a → ƛ in σaddend. In order to stop the first addend transmit through σaddend.
- (2)
- t = k + 1 to k + 2, the addend cache module does not generate spiking output. At t = k + 2 time slice, the spiking corresponding to each bit of the first binary addend is sequentially stored in σsum0, σsum1, …, σsumk−1 from low to high. At the same time, σaux3 continues to receive spiking sent by σin, σaux2,0, σaux2,1 until (n − 1) k + 3 time slice. And these spikings accumulate in σaux3.
- (3)
- t = k + 3 to 2k + 2, the spiking corresponding to the first binary addend is sequentially received by σAdd. At t = 2k + 2 time slice, the spiking corresponding to the highest bit of the first addend is received by σAdd.
- ③
- The 2nd to nth Addend Input
- (1)
- t = 1 to k + 1, σaddend does not generate spiking output.
- (2)
- t = (i − 1) k + 1 to ik (2 ≤ i ≤ n), the spiking corresponding to the i-th binary addend is received by σin in order from low to high. At each time slice, these spikings are transmitted to σAdd through σaddend.
- (3)
- t = (i − 1) k + 2 to ik + 1 (2 ≤ i ≤ n), the spiking corresponding to the i-th binary addend is sequentially received by σaddend. At the same time, σaddend will also receive 1 spiking sent by σaux2,0 and σaux2,1 at each time slice. σaux2,0 and σaux2,1, σaddend is fired and send spiking to σAdd. If there are 2 spikings in σaddend, σaddend firing rule a2 → ƛ sends 0 spiking to σAdd. If there are 3 spikings in σaddend, σaddend firing rule a3 → a to send 1 spiking to σAdd.
- (4)
- t = (i − 1) k + 3 to ik + 2 (2 ≤ i ≤ n), the spiking corresponding to the nth binary addend is sequentially received by σAdd. At t = ik + 2 (2 ≤ i ≤ n) time slice, the highest bit of the 2nd to nth addend is received by σAdd.
- ④
- N-addition
- (1)
- t = 1 to k + 2, there is no spiking input in σAdd.
- (2)
- t = k + 3 to 2k + 2, the spiking corresponding to the first and the second addends are sequentially received by σAdd. At t = k + 4 to 2k + 3 time slice, σAdd simultaneously sends the calculation results to the environment, σsumk−2 and σOF at each time slice. At t = k + 4 time slice, the lowest order of the results of two addend operations is output to the environment, σOF, and σsumk−2. At t = (i − 1) k + 4 to ik + 3 (2 ≤ i ≤ n) time slice, σAdd sends the calculation results to the environment, σsumk−2 and σOF at each time slice.
- (3)
- At t = k + 4 until the system stops, the summand cache module receives spiking sent by σAdd at each time slice. These spikings are transmitted along σsumk−3, σsumk−4, …, σsum0. At t = 2k + 2 time slice, the results of the first and the second addends are stored in σsum0, σsum1, …, σsumk−1 in order from low to high. At t = ik + 2 (2 ≤ i ≤ n) time slice, the operation results of n addends are stored in σsum0, σsum1, …, σsumk−1 in order from low to high.
- (4)
- From t = 2k + 3 to 3k + 2, complete accumulate plus in σAdd. At t = (i − 1) k + 3 to ik + 2 (2 ≤ i ≤ n), complete the accumulation with the i-th addend.
- (5)
- In the absence of overflow in the calculation results, (n − 1) k + 4 to nk + 3 time slice is the effective output time of ПAdd3. At nk + 3 time slice, the highest bit of n addend calculation results is output to the environment.
- ⑤
- Adder
- (1)
- Rule a → a represents executing equation 12 + 02 = 12. It consume one spiking in σAdd and send one spiking outward, which is the calculation result.
- (2)
- a2/a → ƛ indicates the execution of equation 12 + 12 = 102. One spiking retainedin σAdd indicating carry 1, and zero spikings sent outward indicating the operation result 0.
- (3)
- a3/a2 → a indicates the execution of equation 12 + 12 + 12 = 112. One spiking retain in σAdd indicates carry 1, and one spiking sent outward indicates the operation result 1.
- (4)
- a4 → ƛ; a5 → a; a6 → a4; a7 → a4 is used to perform the highest order operation. a4 → ƛ indicates that the highest order calculation performed is 02 + 02 = 02. a5 → a indicates that the highest order calculation performed is 12 + 02 = 12. a6 → a4 indicates that the highest bit calculation performed is 12 + 12 = 102, which indicates that data overflow and sends out 4 spikings. a7 → a4 indicates that the highest bit calculation performed is 12 + 12 + 12 = 112, which indicates that data overflow. σAdd sends 4 spikings outward.
- ⑥
- Data Overflow Monitoring
- (1)
- t = 1 to k + 1, there is no spiking input in σaux4.
- (2)
- t = (i − 1) k + 2 to ik + 1 (2 ≤ i ≤ n), σaux4 receives 1 spiking sent by σaux2,1 at each time slice, and these spikings are stacked in σaux4. At t = ik + 2 (1 ≤ i ≤ n) time slice, σaux4 is fired using rule ak → a send 4 spikings to σAdd.
- ①
- Input Auxiliary Module
- (1)
- t = 0, there is 1 spiking in σaux1,0 and σaux1,1.
- (2)
- t = 1 to 9, σaux1,0 and σaux1,1 send spiking to each other and maintain one spiking in. At the same time, σaux1,1 send 1 spiking to σaux1,2 at each time slice. These spikings are transmitted sequentially along σaux1,2, σaux1,3, …, σaux1,9. σaux1,1 will send 1 spiking to σaux5 at each time slice, these spikings are stacked in the σaux5. During this time slice, the input auxiliary module does not generate spiking output.
- (3)
- t = 10 to 17, all neurons in the input auxiliary module maintain 1 spiking. At the same time, σaux2,1 send 1 spiking to σaux4 at each time slice. And these spikings are stacked in σaux4. σaux1,1 send 1 spiking to σaux5 at each time slice. And these spikings are stacked in σaux5. At t = 17 time slice, there are 8 spikings stacked in σaux4 and 16 spikings stacked in σaux5.
- (4)
- t = 18 to 21, the neurons in the input auxiliary module stop sending spikings in the order of (σaux1,0, σaux1,1), σaux1,2, σaux1,3, …, σaux1,9, (σaux2,0, σaux2,1). At t = 18 time slice, σaux1,0 and σaux1,1 receives 1 spiking sent by σaux5 firing rule a16 → a. σAdd received 4 spikings sent by σaux4 firing rule a8 → a4. At t = 20 time slice, σaux1,0, σaux1,1, σaux1,2, …, σaux1,9 receives 4 spikings sent by σOF and cut off the transmission of the spiking in neurons. At t = 21 time slice, the spiking in σaux2,0, σaux2,1 are consumed and there are no rules to fire in the input auxiliary module.
- ②
- The First Addend Input
- (1)
- t = 1 to 8, σin received spiking corresponding to bit of the first binary addend.
- (2)
- t = 2 to 18, the first addend is transmitted along σaux3, σsum7, σsum6, …, σsum0, σAdd at each time slice. At t = 2 to 9 time slice, σaddend received spiking sent by σin. This spikings are consumed by the forgetting rule a → ƛ in σaddend. At t = 10 time slice, the spiking corresponding to the first addend is stored in σsum7, σsum6, …, σsum0 in order from low to high. At t = 11 time slice, the spiking corresponding to the lowest bit of the first addend is received by σAdd. At t = 18 time slice, the spiking corresponding to the highest bit of the first addend is received by σAdd.
- ③
- The Second Addend Input
- (1)
- t = 1 to 9, σaddend does not generate spiking output.
- (2)
- t = 9 to 16, σin receives bits of the second binary addend.
- (3)
- t = 10 to 18, the second addend is transmitted along σaddend and σAdd at each time slice. At t = 10 to 17 time slice, σaux3 received spiking sent by σin, and 2 spikings sent by σaux1,0 and σaux1,1. These spikings are stacked in σaddend. At t = 11 time slice, the spiking corresponding to the lowest bit of the second addend is received by σAdd. At t = 18 time slice, the spiking corresponding to the highest bit of the second addend is received by σAdd.
- ④
- The Third Addend Input
- (1)
- t = 17 to 21, σin receives the last 5 bits of the third binary addend.
- (2)
- t = 18 to 21, the third addend is transmitted along σaddend and σAdd at each time slice. At t = 18 to 21 time slice, σaux3 received spiking sent by σin, and 1 spiking sent by σaux1,0 and σaux1,1. These spikings are stacked in σaddend. At t = 19 time slice, the spiking corresponding to the lowest bit of the third addend is received by σAdd. At t = 21 time slice, the spiking corresponding to the a6 bit of the third addend is received by σAdd.
- ⑤
- Addition
- (1)
- t = 1 to 10 does not have an addend reaching σAdd. So, there is no spiking in σAdd.
- (2)
- t = 11 to 18, the first and the second addends are received by σAdd in order from low to high. At t = 18 time slice, the highest bits of the first and second addends are received by σAdd, and the 4 spikings sent by σaux4 are received by σAdd too.
- (3)
- t = 12 to 19, the operation results of the first and the second addends are sent to the environment, σOF and σsum6. At t = 19 time slice, the environment, σOF and σsum6 receive 4 spikings sent by σAdd using rule a6 → a4. It indicates data overflow.
- (4)
- t = 20, σOF is fired and send 4 spikings to σAdd, σaux1,2, σaux1,3, … σaux1,9. At the same time, the environment, σOF and σsum6 received 1 spiking sent by σAdd.
- (5)
- At t = 21 time slice, there is no rule can be firing in σAdd and σOF. ПAdd3 stops running.
3.3. Comparison
4. An Locally Homogeneous Spiking Neural P System for Subtraction
4.1. An LHSNP System with 2 Input Neurons for 2 Numbers Subtraction
- (1)
- O= {a};
- (2)
- σin1 = (0, Raux);
- (3)
- σin2 = (0, Raux);
- (4)
- σaux1,i = (1, Raux), 0 ≤ i ≤ 1;
- (5)
- σaux1,i = (0, Raux), 2 ≤ i ≤ 7;
- (6)
- σaux2 = (0, Raux2);
- (7)
- σaux3 = (0, Raux3);
- (8)
- σm = (0, Rm);
- (9)
- σs = (0, Raux);
- (10)
- σSub = (0, RSub);
- (11)
- syn = {(in1, aux1,6), (in2, aux1,7), (aux1,6, m), (aux1,7, s), (m, Sub), (s, Sub), (aux1,0, aux1,1), (aux1,1, aux1,0), (aux1,1, aux2), (aux2, aux1,0), (aux2, aux1,1), (aux1,1, aux1,2), (aux1,2, aux1,3), (aux1,2, aux1,4), (aux1,3, auxm), (aux1,4, auxm), (aux1,4, aux1,5), (aux1,5, aux3), (aux3, Sub)};
- (12)
- in1 = Input1, in2 = Input2;
- (13)
- out = Sub.
- ①
- Input Auxiliary Module
- (1)
- t = 0, there is one spiking in σaux1,0 and σaux1,1.
- (2)
- t = 1 to 2, the input auxiliary module does not generate spiking output. At each time slice, σaux1,0 and σaux1,1 send spiking to each other and maintain 1 spiking. At the same time, σaux1,0 at every time slice sends 1 spiking to σaux1,2. These spikings are transmitted along σaux1,2 and (σaux1,3, σaux1,4).
- (3)
- t = 3 to k + 2, the input auxiliary module does not send spiking output. σaux1,3 and σaux1,4 send one spiking to σminuend at each time slice. t = 3 to k − 1, σaux1,0 and σaux1,1 send spiking to each other. And σaux1,0 at each time sends 1 spiking to σaux1,2. At k − 1 time slice, k − 1 spikings stacked in σaux2. At t = k time slice, σaux1,0 and σaux1,1 received 2 spiking. One of the spiking comes from what they send to each other. Another spiking is sent by σaux2 using rule ak−1 → a. At k + 1 time slice, the spiking in σaux1,2 is cleared to zero. At k + 1 time slice, the spiking in σaux1,3 and σaux1,4 is cleared to zero.
- (4)
- At the k + 3 time slice, σaux1,5 send 1 spiking to σaux3. There are 8 spikings stacked in σaux3.
- (5)
- At the k + 4 time slice, the input auxiliary module no longer generates spiking.
- ②
- Minuend Input
- (1)
- t = 1 to k, the spiking corresponding to each binary bit of the minuend is sequentially received by σin1 in order from low to high. These spikings are transmitted along σaux1,6, σminuend, and σSub.
- (2)
- t = 3 to k + 2, the spiking corresponding to each binary bit of the minuend is sequentially received by σminuend. At the same time, σminuend also received 2 spikings at each time from σaux1,3 and σaux1,4.
- (3)
- t = 4 to k + 3, the spiking corresponding to each binary bit of the minuend sent by σminuend is sequentially received by σSub. At each time slice, one spiking sent by minuend represents the binary number 1, and 2 spiking represents the binary number 0. At k + 3 time slice, the highest bit of the minuend is received by σSub.
- ③
- Subtrahend Input
- (1)
- t = 1 to k, the spiking corresponding to each binary bit of the subtrahend is sequentially received by σin2 in order from low to high. These spikings are transmitted along σaux1,7, σsutrahend, and σSub.
- (2)
- t = 3 to k + 2, the spiking corresponding to each binary bit of the subtrahend is sequentially received by σsutrahend.
- (3)
- t = 4 to k + 3, the spiking corresponding to each binary bit of the subtrahend is sequentially received by σSub. At each time slice, one spiking sent by σsutrahend represents the binary number 1, and zero spiking represents the binary number 0. At k + 3 time slice, the highest bit of the subtrahend is received by σSub.
- ④
- Subtraction Operation
- (1)
- t = 1 to 3, there is no spiking were received in σsub.
- (2)
- t = 4 to k + 3, the spiking corresponding to each binary bit of the minuend and subtrahend sent by σminuend and σsutrahend are sequentially received by σSub.
- (3)
- t = 5 to k + 4, σsub sends calculation results to the environment at each time slice. It is the effective output time of ПSub1 when there is no overflow in the calculation. At t = k + 3 time slice, the highest bit of the two subtractors is calculated. At t = k + 4 time slice, σaux3 uses rule ak → a5 to send 5 spikings to σsub. These 5 spikings in the σsub detect whether there is a carry after the calculation of the highest bit of the two subtractions. If there is a carry generation, σsub uses rule a6 → a4 to send 4 spikings to the environment to indicate data overflow.
- ⑤
- Subtraction Rules
- (1)
- Rule a → a indicates performing subtraction calculation: 12 − 02 = 12. There is one spiking in σsub, which comes from σminuend. It represents the subtracted binary bit 1. Rule a → a represents consumption 1 spiking in σsub, and sending 1 spiking to the environment, namely performing subtraction operation 12 − 02 = 12.
- (2)
- Rule a2 → ƛ indicates performing subtraction calculation: 02 − 02 = 02 or 12 − 12 = 02. There are two spikings in the σsub, and there are three sources of these two spikings. In the first case, these two spikings have come from σminuend and σsubtrahend. In the second case, one of them come from σsub retained spiking in σsub (be borrowed), and the other one come from σsubtrahend. In the third case, these two spikings came from σminuend. Rule a2 → ƛ consumption 2 spikings in σsub, and send 0 spiking to the environment, namely performance subtraction operation 02 − 02 = 02 or 12 − 12 = 02.
- (3)
- Rule a3/a2 → a indicates performing subtraction calculation: 02 − 12 = 12 and borrowing one digit forward. Two spikings come from σminuend and one spiking comes from σaddend. Rule a3/a2 → a represents consuming 2 spikings in σsub, retaining 1 spiking (representing forward borrowing), and sending 1 spiking to the environment. That is, the subtraction operation performed is 02 − 12 = 12 and borrowing 1 digit forward.
- (4)
- Rule a4/a3 → ƛ means to perform subtraction: 02 − 12 − 12 = 02 and borrow 1 bit forward. Two spikings were sent by σminuend, one spiking was sent by σaddend, and one spiking was retained in σSub. Rule a4/a3 → ƛ means that 3 spikings in σSub are consumed, 1 spiking is reserved (representing forward borrowing), and 0 spikings are sent to the environment. That is, the subtraction operation is 02 − 12 − 12 = 02, and 1 bit is borrowed forward.
- (5)
- Rule a6 → a4 indicates that the highest bit of two binary numbers is carried during calculation in σsub, data overflow. A total of 5 spikings come from the σaux3 and 1 spiking comes from σsub reservation. Rule a6 → a4 means that 6 spikings in σsub are consumed and generate 4 spikings are sent to the environment, indicating data overflow.
- ①
- Input Auxiliary Module
- (1)
- At t = 0 time slice, there is one spiking in σaux1,0 and σaux1,1.
- (2)
- t = 1 to 7, σaux1,0 and σaux1,1 send 1 spiking to each other and maintain one spiking in. At the same time, σaux1,1 will send one spiking to σaux2 and σaux1,2. After receiving spiking, these spikings accumulate inside σaux2. And at t = 7 time slice, σaux2 accumulates 7 spikings. The spiking received by σaux1,2 is transmitted along three paths.
- (3)
- At t = 8 time slice, σaux1,0 and σaux1,1 sent 1 spiking to each other. And σaux1,0, σaux1,1 receives 1 spiking from σaux2 using rule a7 → a. At the same time, σaux2 received 1 spiking sent by σaux1,1. And when the system stops, there is only 1 spiking in σaux2.
- (4)
- At t = 9 time slice, σaux1,0 and σaux1,1 stop generating spiking. At the same time, the spiking in σaux1,2 is consumed.
- (5)
- At t = 10 time slice, σaux1,0, σaux1,1, …, σaux1,4 stop generating spiking.
- (6)
- At t = 11 time slice, 8 spikings sent by σaux1,5 are stacked in σaux3.
- (7)
- At t = 12 time slice, there are no rules to execute in the input auxiliary module.
- ②
- Minuend Input
- (1)
- t = 1 to 8, the corresponding spiking of the minuend binary bits are sequentially received by σin1 in order from low to high.
- (2)
- t = 2 to 9, the corresponding spiking of the minuend binary bits are sequentially received by σaux1,6.
- (3)
- t = 3 to 10, the corresponding spiking of the minuend binary bits are sequentially received by σm. At each time slice, σm receives 2 spiking sent by σaux1,3 and σaux1,4.
- (4)
- t = 4 to 11, the corresponding spiking of the minuend binary bits are sequentially received by σsub. In σsub, 1 spiking represent binary number 1, and 2 spikings represent binary number 0.
- ③
- Subtrahend Input
- (1)
- t = 1 to 8, the corresponding spiking of the subtrahend binary bit is sequentially received by σin2 in order from low to high.
- (2)
- t = 2 to 9, the corresponding spiking of the subtrahend binary bit is sequentially received by σaux1,7.
- (3)
- t = 3 to 10, the corresponding spiking of the subtrahend binary bit is sequentially received by σs.
- (4)
- t = 4 to 11, the corresponding spiking of the subtrahend binary bit is sequentially received by σsub. Subtrahend in σsub represents binary number 1 with 1 spiking, and 0 spiking represent binary number 0.
- ④
- Subtraction Operation
- (1)
- t = 1 to 3, there is no spiking in the σsub.
- (2)
- t = 4 to 11, the spiking corresponding to the minuend and subtracted binary bit is received by the σsub in order from low to high.
- (3)
- t = 5 to 12 is the effective output time of ПSub1. During this time slice, σsub sends the calculation result 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 to the environment in order from low to high. At t = 12 time slice, σsub receives 5 spikings sent by σaux3 using rule ak → a5, and these 5 spikings are stacked in σsub, the calculation result did not overflow.
4.2. An LHSNP System with 1 Input Neuron for 2 Number Subtraction
- (1)
- O= {a};
- (2)
- σin = (0, Raux);
- (3)
- σaux1,i = (0, Raux), i = 0, 1;
- (4)
- σaux1,i = (1, Raux), i = 2, …, k + 1;
- (5)
- σaux2,i = (0, Raux), i = 0, 1, 2;
- (6)
- σauxi = (0, Raux), i = 3, 4;
- (7)
- σaux5 = (0, Raux5);
- (8)
- σm0 = (0, Rm);
- (9)
- σmi = (0, Raux), i = 1, 2, …, k − 1;
- (10)
- σs = (0, Rs);
- (11)
- σSub = (0, RSub);
- (12)
- syn = {(in, aux4), (in, s), (s, Sub), (aux4, mk−1), (m0, Sub), (aux1,1, aux1,0), (aux1,k−1, aux3), (aux1,k−1, aux3), (aux3, aux1,1), (aux3, aux1,0), (aux1,k + 1, aux2,0), (aux1,k + 1, aux2,1), (aux2,0, aux4), (aux2,1, aux4), (aux2,0, m0), (aux2,1, m0), (aux2,1, aux2,2), (aux2,1, s), (aux2,2, aux5), (aux5, Sub), (s, Sub)}∪{(aux1,i, aux1,i + 1), i ∈ {0, 1, …, k}}∪{(mi−1, mi), i ∈ {1, 2, …, k}};
- (13)
- in = Input;
- (14)
- out = Sub.
- ①
- Input Auxiliary Module
- (1)
- t = 0, there is 1 spiking in σaux1,0 and σaux1,1.
- (2)
- t = 1 to k + 1, σaux1,0 and σaux1,1 send 1 spiking to each other and maintain one spiking. At the same time, σaux1,1 sends 1 spiking to σaux1,2 at each time slice, and these spiking will be transmitted sequentially along σaux1,2, σaux1,3, …, σaux1,k + 1. At time t = k − 1, σaux3 receives 1 spiking sent by σauxk−1. At t = k time slice, σaux1,0 and σaux1,1, respectively receive 1 spiking sent by each other, and σaux3 sent 1 spiking to σaux1,0 and σaux1,1. It truncate the input to the auxiliary module for continuous spiking generation. At time t = k, the spiking in σaux1,2 are cleared.
- (3)
- t = k + 2 to 2k + 1, the input auxiliary module will continue to generate spiking output. σaux2,0 and σaux2,1 send 1 spiking to σaux4, σm0, σms at each time slice. Send spiking to σaux4 to truncate the spiking corresponding to the subtraction bit and transmit it through σaux4. Send 1 spiking to σm0, respectively, to modify the spiking corresponding to the binary number 0 in the subtrahend number. Send spiking to the σms to transmit the subtraction through the σms. σaux2,1 also sends 1 spiking to σaux2,2 at each time slice, and σaux2,2 receives the spiking and sends it to σaux5, which accumulates in σaux5. Input the spiking in σaux1,3, …, σaux1,k + 1, σaux2,0 and σaux2,1 of the auxiliary module in each time slice and clear them sequentially. At t = 2k + 1 time slice, σaux2,0 and σaux2,1 stops generating spiking output.
- (4)
- t = 2k + 2, in the input auxiliary module, σaux2,2 send 1 spiking to σaux5. And the spiking in σaux2,2 is cleared. At this time, 8 spikings are accumulated in σaux5, and the input auxiliary module stops generating spiking inputs.
- (5)
- t = 2k + 3, there are no rules can be firing in the input auxiliary module.
- ②
- Minuend Input
- (1)
- t = 1 to k, the spiking corresponding to the minuend bits are received by σin in order from low to high. At t = k time slice, the input of the minuend is completed. At each time slice, these spikings are transmitted sequentially along σaux4, σsumk−1, σsumk−2, …, σsum0. At t = 2 to k + 1 time slice, σs receives the spiking sent by σin at each time slice. This part of the spiking is forgotten by the rule a → ƛ in σs.
- (2)
- t = k + 1 to 2k + 2, the corresponding spiking of the minuend is sequentially transmitted to σSub along σaux4, σsumk−1, σsumk−2, …, σsum0, while the spiking in the neuron is sequentially cleared. At t = k + 2 to 2k + 1 time slice, the corresponding spiking of the minuend is sequentially received by σsum0, and at the same time, σsum0 also receives 1 spiking sent by σaux2,0, σaux2,1 at each time slice. At t = k + 3 to 2k + 2 time slice, the spiking corresponding to the minuend bits are received by σSub in order from low to high. At t = 2k + 2 time slice, there is no spiking in the minuend cache module.
- ③
- Subtrahend Input
- (1)
- t = 1 to k + 1, σs does not generate spiking output.
- (2)
- t = k + 1 to 2k, the corresponding spiking of the subtrahend is received by σin in order from low to high. At t = 2k time slice, the subtrahend input is completed. At each time slice, these spikings are sequentially transmitted along σs to σSub.
- (3)
- t = k + 2 to 2k + 1, σs receives spiking sent by σin and 1 spiking sent by σaux2,0, σaux2,1 at each time slice.
- (4)
- t = k + 3 to 2k + 2, the spiking corresponding to the subtrahend is received by σSub in order from low to high. At t = 2k + 2 time slice, there is no spiking in σs.
- ④
- Subtraction Operation
- (1)
- t = 1 to k + 2, σSub has no spiking input.
- (2)
- t = k + 3 to 2k + 2, the spiking corresponding to the minuend and subtrahend bits received by σSub in order from low to high.
- (3)
- t = k + 4 to 2k + 3, σSub will send the settlement results to the environment in order from low to high. At t = 2k + 2 time slice, the highest order of the two subtractions is calculated in σSub. At t = 2k + 3 time slice, σSub receives 5 spiking sent by σaux5. If a carry is generated at 2k + 2 time slice, then there are 6 spikings in σSub. In the 2k + 4 time slice, the environment will receive 4 spikings sent by σSub after using rule a6 → a4, indicating data overflow. If there is no carry generation at 2k + 2 time slice, then there are 5 spiking in σSub without using any rules.
- ①
- Input Auxiliary Module
- (1)
- The spikingin the input auxiliary module is transmitted along σaux1,2, σaux1,3, …, σaux1,9, and they are all homogeneous neurons, so the cases of aux1,3-aux1,8 are omitted in Table 5. t = 0, σaux1,0 and σaux1,1 each have 1 spiking.
- (2)
- t = 1 to 7, σaux1,0 and σaux1,1 sends 1 spiking to each other. And σaux1,1 also sends 1 spiking to σaux1,2 at each time slice, and these spiking are transmitted sequentially along σaux1,3, σaux1,4, …, σaux1,9.
- (3)
- t = 7 to 14, σaux3 receives 1 spiking sent by σaux1,7 at each time slice, and these spiking are, respectively, sent to σaux1,0, σaux1,1 through σaux3 and stacked in it. At t = 8 time slice, σaux1,0, σaux1,1 receives 1 spiking sent by each other and 1 spiking sent by σaux3, truncating the continuous generation of spiking in the input auxiliary module.
- (4)
- t = 9 to 18, the spiking of σaux1,2, σaux1,3, …, σaux1,9, (σaux2,0, σaux2,1), σaux2,2 in the input auxiliary module are sequentially cleared. At t = 10 to 17 time slice, σaux2,0, σaux2,1 continuously generates spiking output, while σaux2,1 also continuously sends spiking to σaux2,2. After receiving the spiking, σaux2,2 continuously sends the spiking to σaux5 and accumulates it. At t = 18 time slice, there are 8 spiking stacked in σaux5.
- (5)
- t = 19, there are no rules to execute in the input auxiliary module.
- ②
- Minuend Input
- (1)
- t = 1 to 8, the spiking corresponding to the minuend bits are received by σin in the order of 1, 0, 1, 1, 0, 0, 0, 0, 0. These spikings are transmitted sequentially to σSub along σaux4, σm7, σm6, …, σm0.
- (2)
- t = 2 to 9, the minuend bits are sequentially received by σaux4 and σs. During this time slice, the spiking received by σs is consumed by the forgetting rule a → ƛ.
- (3)
- t = 10 to 17, the minuend bits are sequentially received by σm0, and at each time slice σaux2,0 and σaux2,1 is also sent a spiking to σm0.
- (4)
- t = 11 to 18, the corresponding spiking 1, 2, 1, 1, 2, 2, 2, 2, 2, 2 of the minuend bits are sequentially sent to σsub.
- ③
- Subtrahend Input
- (1)
- t = 0 to 8, σs did not generate spiking output.
- (2)
- t = 9 to 16, the spiking corresponding to the subtrahend bits are received by σin in the order of 1, 1, 1, 0, 0, 0, 0, 0, 0 from low to high.
- (3)
- t = 10 to 17, the corresponding spiking of the subtrahend bits are sequentially received by σs. At the same time, σs also receives 1 spiking sent by σaux2,0, σaux2,1 at each time slice. σs has 3, 3, 3, 2, 2, 2, 2, 2 spiking in each time slice, using rule a2 → ƛ or a3 → a direction sends spiking to σsub.
- (4)
- t = 11 to 18, the spiking corresponding to the subtrahend bits 1, 1, 1, 0, 0, 0, 0, 0 is sequentially received by σsub.
- ④
- Subtraction Operation
- (1)
- t = 1 to 11, σsub did not generate spiking output.
- (2)
- t = 11 to 18, the minuend and subtrahend bits are sequentially received by σsub, and σsub has 2, 3, 3, 2, 2, 2, 2, 2 spiking in each time slice.
- (3)
- t = 12 to 19, σsub sends the operation results 0, 1, 1, 0, 0, 0, 0, 0 to the environment in sequence. At t = 19 time slice, σsub received 5 spikings sent by σaux5, no rules can be used, and there is no data overflow.
4.3. An LHSNP System with 1 Input Neuron for n-Subtraction
- ①
- Input Auxiliary Module
- (1)
- The spikings continuously sent by σaux1,1 in the auxiliary module are transmitted along σaux1,2, σaux1,3, …, σaux1,8. And these neurons are homogeneous neurons. So, we omit the description of the spiking situation of aux1,3, …, aux1,7 in Table 6. t = 0, there is 1 spiking in σaux1,0 and σaux1,1.
- (2)
- t = 1 to 17, σaux1,0 and σaux1,1 sends 1 spiking to each other. And σaux1,1 also sends 1 spiking to σaux3 at each time slice. These spikings are stacked in σaux3. At t = 16 time slice, σaux3 accumulates 16 spikings in neurons. σaux1,1 also sends 1 spiking to σaux1,2 at each time slice. And these spikings are transmitted sequentially along σaux1,3, σaux1,4, …, σaux1,8, (σaux2,0, σaux2,1). At t = 1 to 9 time slice, the input auxiliary module does not generate spiking output. At each time slice after t = 10, the input auxiliary module generates spiking output, σaux2,0 and σaux2,1 send one spiking to σaux4, σm0, σs at each time slice. At the same time, σaux2,1 also sends one spiking to σaux5, which is stacked in σaux5 until the number of spikings reaches 8. Then, use the rule a8 → a5 to consume spikings. At t = 17, σaux1,0 and σaux1,1 receive 1 spiking sent to each other. σaux3 uses rule a16 → a consume 16 spikings and generates 1 spiking output.
- (3)
- t = 18 to 22, σaux1,0, σaux1,1 no longer generates spiking output. The spikings in σaux1,2, σaux1,3, σaux1,4 are sequentially cleared. At t = 21 time slice, σaux1,0, σaux1,1, σaux1,2, σaux1,3, …, σaux1,8 simultaneously receives 4 spikings sent by σOF, truncating the transmission of spiking in the input auxiliary module.
- ②
- Minuend Input
- (1)
- t = 1 to 8, the corresponding spiking of the minuend bit is received by σin, and these spikings are transmitted along σaux4, σm7, σm6, …, σm0.
- (2)
- t = 2 to 9, σin simultaneously sends spiking to σaux4 and σs. After receiving the spiking, σaux4 passes the spiking to the minuend cache module. After receiving spiking, σs does not generate spiking output, and these spiking are consumed by the forgetting rule a → ƛ in σs.
- (3)
- t = 10 to 17, the corresponding spiking of the first minuend bit is sequentially received by σm0. And at each time slice, σm0 also receives 1 spiking sent by σaux2,0 and σaux2,1. In σm0, the spiking corresponding to the minuend binary number 0 is changed to 2 through the rule a2 → a2, in order to distinguish it from the spiking corresponding to the subtrahend binary number 0.
- (4)
- t = 11 to 18, the spikings 1, 2, 1, 1, 2, 2, 2, 2 corresponding to the first minuend bit are sequentially received by σSub. A total of 1 spiking represents the minuend number 12, and 2 spikings represent the minuend number 02.
- (5)
- From t = 12 to the system stops, σm6 receives spikings (i.e., calculation results) sent by σSub at each time slice. And these spikings are transmitted along σm5, σm4, …, σm0 to σSub achieve accumulate plus with the next subtrahend. At t = 20 time slice, σm6 receives 4 spikings sent by σSub, and σm6 no longer generates spiking output in the following time. At t = 21 time slice, σm5, σm4, …, σm0 simultaneously receives 4 spikings sent by σOF. These spikings truncate the transmission of spiking in the minuend module. And σm6 receives 1 spiking sent by σSub.
- ③
- Subtrahend Input
- (1)
- t = 1 to 8, σs does not generate spiking output. And the spiking σs received at each time slice has been consumed by the forgetting rule a → ƛ.
- (2)
- t = 9 to 16, the corresponding spiking 1, 1, 1, 1, 0, 0, 0, 0 of the first subtrahend bit are sequentially received by σin. These spikings are transmitted along σs to the σin.
- (3)
- t = 10 to 17, σs receives the spiking corresponding to the first subtrahend bit sent by σin. At the same time, σs receives 1 spiking sent by σaux2,0 and σaux2,1 at each time slice. σs uses rule a2 → ƛ or a3 → a to consume spikings and send spikings to σSub. From t = 10 to system stop, σaux4 receives spiking from σin, σaux2,0, and σaux2,1 at each time slice, these spikings are stacked in σaux4. t = 13 to 20, the spiking corresponding to each of the first subtrahend bits, 1, 1, 1, 1, 0, 0, 0, 0 are sequentially received by σSub. In a neuron, 1 spiking represents the binary number 12, and 0 spiking represents the binary number 02.
- (4)
- From 17 to 22, the spiking 0, 0, 0, 1, 0, 0 corresponding to the second subtrahend are received by σin. These spikings are transmitted along σs to the σSub. The transmission process is consistent with the first subtrahend. At t = 21 time slice, 4 spikings sent by σOF are received in σs, and the subtrahend transmission is truncated.
- ④
- Subtraction Operation
- (1)
- t = 1 to 10, σSub has no spiking input.
- (2)
- t = 11 to 18, the spiking corresponding to the first minuend and each subtrahend bit is received by σSub in order from low to high.
- (3)
- t = 12 to 19, σSub sends the calculation results to the environment, σOF, and σm6 simultaneously at each time. If σOF receives 1 spiking, it consumes the spiking by forgetting rule a → ƛ. After receiving the spiking in σm6, these spikings are transmitted along σm5, σm4, …, σm0 to the σsub to achieve accumulate subtract with the next subtrahend. At t = 19 time slice, the highest bit of the first minuend and subtrahend are received by σsub. And at the same time, σsub received 5 spikings sent by σaux5 after using the rule a8 → a5. At this time, σsub has 8 spikings.
- (4)
- t = 20, the environment, σOF, and σm6 receives four spikings sent by σSub after using rule a8 → a4. It represents data overflow. At the same time, 1 spiking sent by σm0 was received in the σSub.
- (5)
- At t = 21, σm5, σm4, …, σm0, σaux1,0, σaux1,1, …, σaux1,8, σs, σSub simultaneously receives 4 spikings sent by σOF after using rule a4 → a4. It truncates the transmission of spiking in ПSub3. At the same time, σSub sends 1 spiking to the environment, σOF, and σm6, respectively.
- (6)
- At t = 22, there are no rules can be fired in ПSub3.
4.4. Comparison
5. Conclusions
- The LHSNP system ПAdd2 with 1 input neuron for any 2 k-bit binary number addition operation;
- The LHSNP system ПAdd3 with 1 input neuron for any n k-bit binary number addition;
- The LHSNP system ПSub1 with 2 input neurons for any 2 k-bit binary number subtraction;
- The LHSNP system ПSub2 with 1 input neuron for any 2 k-bit binary number subtraction;
- The LHSNP systemПSub3 with 1 input neuron for any n k-bit binary number subtraction.
Author Contributions
Funding
Institutional Review Board Statement
Informed Consent Statement
Data Availability Statement
Conflicts of Interest
References
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t | in | aux3 | sum7 | sum6, …, sum1 | sum0 | aux1,0 | aux1,1 | aux1,2 | aux1,3, …,aux1,8 | aux1,9 | aux2,0 | aux2,1 | aux4 | addend | Add | out | OF |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
t = 0 | - | 0 | 0 | … | 0 | 1 | 1 | 0 | … | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 |
t = 1 | 1 | 0 | 0 | … | 0 | 1 | 1 | 1 | … | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 |
t = 2 | 0 | 1 | 0 | … | 0 | 1 | 1 | 1 | … | 0 | 0 | 0 | 0 | 1 | 0 | - | 0 |
t = 3 | 1 | 0 | 1 | … | 0 | 1 | 1 | 1 | … | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 |
t = 4 | 0 | 1 | 0 | … | 0 | 1 | 1 | 1 | … | 0 | 0 | 0 | 0 | 1 | 0 | - | 0 |
5,…,8 | … | … | … | … | … | … | … | … | … | … | … | … | 0 | … | … | … | … |
t = 9 | 0 | 0 | 0 | … | 0 | 1 | 1 | 1 | … | 1 | 1 | 1 | 0 | 0 | 0 | - | 0 |
t = 10 | 1 | 2 | 0 | … | 1 | 2 | 2 | 1 | … | 1 | 1 | 1 | 1 | 2 | 0 | - | 0 |
t = 11 | 1 | 5 | 0 | … | 0 | 3 | 3 | 0 | … | 1 | 1 | 1 | 2 | 3 | 1 | - | 0 |
t = 12 | 0 | 8 | 0 | … | 1 | 4 | 4 | 0 | … | 1 | 1 | 1 | 3 | 3 | 1 | 1 | 1 |
t = 13 | 0 | 10 | 0 | … | 0 | 5 | 5 | 0 | … | 1 | 1 | 1 | 4 | 2 | 2 | 1 | 1 |
t = 14 | 0 | 12 | 0 | … | 0 | 6 | 6 | 0 | … | 1 | 1 | 1 | 5 | 2 | 1 | 0 | 0 |
t = 15 | 0 | 14 | 0 | … | 0 | 7 | 7 | 0 | … | 1 | 1 | 1 | 6 | 2 | 0 | 1 | 1 |
16,…,18 | … | … | … | … | … | … | … | … | … | … | … | … | … | … | … | … | … |
t = 19 | - | 22 | 0 | … | 0 | 11 | 11 | 0 | … | 0 | 0 | 0 | 1 | 2 | 4 | 0 | 0 |
t | in | aux3 | sum7 | sum6, …, sum1 | sum0 | aux1,0 | aux1,1 | aux1,2 | aux1,3, …, aux1,9 | aux2,0 | aux2,1 | aux4 | aux5 | addend | Add | Out | OF |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
t = 0 | - | 0 | 0 | … | 0 | 1 | 1 | 0 | … | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 |
t = 1 | 0 | 0 | 0 | … | 0 | 1 | 1 | 1 | … | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 |
2, …, 7 | … | … | … | … | … | … | … | … | … | … | … | … | … | … | … | … | … |
t = 8 | 1 | 0 | 0 | … | 0 | 1 | 1 | 1 | … | 0 | 0 | 0 | 7 | 0 | 0 | - | 0 |
t = 9 | 0 | 1 | 0 | … | 0 | 1 | 1 | 1 | … | 1 | 1 | 0 | 8 | 1 | 0 | - | 0 |
t = 10 | 1 | 2 | 1 | … | 0 | 1 | 1 | 1 | … | 1 | 1 | 1 | 9 | 2 | 0 | - | 0 |
t = 11 | 1 | 5 | 0 | … | 1 | 1 | 1 | 1 | … | 1 | 1 | 2 | 10 | 3 | 0 | - | 0 |
t = 12 | 0 | 8 | 0 | … | 1 | 1 | 1 | 1 | … | 1 | 1 | 3 | 11 | 3 | 2 | 0 | 0 |
t = 13 | 0 | 10 | 0 | … | 0 | 1 | 1 | 1 | … | 1 | 1 | 4 | 12 | 2 | 3 | 0 | 0 |
t = 14 | 0 | 12 | 0 | … | 0 | 1 | 1 | 1 | … | 1 | 1 | 5 | 13 | 2 | 1 | 1 | 0 |
t = 15 | 0 | 14 | 0 | … | 0 | 1 | 1 | 1 | … | 1 | 1 | 6 | 14 | 2 | 0 | 1 | 0 |
t = 16 | 1 | 16 | 0 | … | 0 | 1 | 1 | 1 | … | 1 | 1 | 7 | 15 | 2 | 0 | 0 | 0 |
t = 17 | 1 | 19 | 0 | … | 1 | 1 | 1 | 1 | … | 1 | 1 | 8 | 16 | 3 | 0 | 0 | 0 |
t = 18 | 0 | 22 | 0 | … | 0 | 2 | 2 | 1 | … | 1 | 1 | 1 | 1 | 3 | 6 | 0 | 0 |
t = 19 | 0 | 24 | 0 | … | 0 | 2 | 2 | 0 | … | 1 | 1 | 2 | 1 | 2 | 1 | 4 | 4 |
t = 20 | 0 | 26 | 0 | … | 5 | 6 | 6 | 4 | … | 1 | 1 | 3 | 1 | 6 | 4 | 1 | 1 |
t = 21 | 0 | 28 | 0 | … | 5 | 6 | 6 | 4 | … | 0 | 0 | 4 | 1 | 8 | 0 | 0 | 0 |
SN P System | SN P System with 1 Input for 2 Natural Number Addition | SN P System with 1 Input for n Natural Number Addition | |||||
---|---|---|---|---|---|---|---|
Parameter | |||||||
Number of Neurons | Complete Time | Number of Rules | Number of Neurons | Complete Time | Number of Rules | ||
This work | 2k + 9 | 2k + 3 | 8 | 2k + 11 | nk + 3 | 13 | |
Zhang Xingyi [25] | - | - | - | 3k + 5 | (n + 1)k + 4 | 9 | |
Wang Huifang [34] | - | - | - | 2k + 4 | (n + 1)k + 1 | 5k − 1 |
t | in1 | in2 | aux1,0 | aux1,1 | aux1,2 | aux1,3 | aux1,4 | aux1,5 | aux1,6 | aux1,7 | aux2 | aux3 | m | s | Sub | out |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
t = 0 | - | - | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - |
t = 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | - |
t = 2 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 2 | 0 | 0 | 0 | 0 | - |
t = 3 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 3 | 0 | 3 | 1 | 0 | - |
t = 4 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 4 | 1 | 2 | 1 | 2 | - |
t = 5 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 5 | 2 | 3 | 1 | 3 | 0 |
t = 6 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 6 | 3 | 3 | 0 | 3 | 1 |
t = 7 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 7 | 4 | 2 | 0 | 2 | 1 |
t = 8 | 0 | 0 | 2 | 2 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 5 | 2 | 0 | 2 | 0 |
t = 9 | - | - | 2 | 2 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 6 | 2 | 0 | 2 | 0 |
t = 10 | - | - | 2 | 2 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 7 | 2 | 0 | 2 | 0 |
t = 11 | - | - | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 8 | 0 | 0 | 2 | 0 |
t = 12 | - | - | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 5 | 0 |
t | in | aux4 | m7 | m6, …, m1 | m0 | aux1,0 | aux1,1 | aux1,2 | aux1,3, …, aux1,8 | aux1,9 | aux2,0 | aux2,1 | aux2,2 | aux3 | aux5 | s | Sub | out |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
t = 0 | - | 0 | 0 | … | 0 | 1 | 1 | 0 | … | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - |
t = 1 | 1 | 0 | 0 | … | 0 | 1 | 1 | 1 | … | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - |
t = 2 | 0 | 1 | 0 | … | 0 | 1 | 1 | 1 | … | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | - |
t = 3 | 1 | 0 | 1 | … | 0 | 1 | 1 | 1 | … | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - |
t = 4 | 1 | 1 | 0 | … | 0 | 1 | 1 | 1 | … | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | |
t = 5 | 0 | 1 | 1 | … | 0 | 1 | 1 | 1 | … | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | - |
t = 6 | 0 | 0 | 1 | … | 0 | 1 | 1 | 1 | … | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - |
t = 7 | 0 | 0 | 0 | … | 0 | 1 | 1 | 1 | … | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | - |
t = 8 | 0 | 0 | 0 | … | 0 | 2 | 2 | 1 | … | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | - |
t = 9 | 1 | 0 | 0 | … | 0 | 3 | 3 | 0 | … | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | - |
t = 10 | 1 | 3 | 0 | … | 3 | 4 | 4 | 0 | … | 1 | 1 | 1 | 1 | 1 | 0 | 3 | 0 | - |
t = 11 | 1 | 6 | 0 | … | 2 | 5 | 5 | 0 | … | 1 | 1 | 1 | 1 | 1 | 1 | 3 | 2 | - |
t = 12 | 0 | 9 | 0 | … | 3 | 6 | 6 | 0 | … | 1 | 1 | 1 | 1 | 1 | 2 | 3 | 3 | 0 |
t = 13 | 0 | 11 | 0 | … | 3 | 7 | 7 | 0 | … | 1 | 1 | 1 | 1 | 1 | 3 | 2 | 3 | 1 |
t = 14 | 0 | 13 | 0 | … | 2 | 8 | 8 | 0 | … | 1 | 1 | 1 | 1 | 1 | 4 | 2 | 2 | 1 |
t = 15 | 0 | 15 | 0 | … | 2 | 9 | 9 | 0 | … | 1 | 1 | 1 | 1 | 0 | 5 | 2 | 2 | 0 |
t = 16 | 0 | 17 | 0 | … | 2 | 9 | 9 | 0 | … | 0 | 1 | 1 | 1 | 0 | 6 | 2 | 2 | 0 |
t = 17 | - | 19 | 0 | … | 2 | 9 | 9 | 0 | … | 0 | 0 | 0 | 1 | 0 | 7 | 2 | 2 | 0 |
t = 18 | - | 19 | 0 | … | 0 | 9 | 9 | 0 | … | 0 | 0 | 0 | 0 | 0 | 8 | 0 | 2 | 0 |
t = 19 | - | 19 | 0 | … | 0 | 9 | 9 | 0 | … | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 0 |
t | in | aux4 | m7 | m6, …, m2 | m1 | m0 | s | aux1,0 | aux1,1 | aux1,2 | aux1,3, …, aux1,7 | aux1,8 | aux2,0 | aux2, 1 | aux3 | aux5 | Sub | out | OF |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
t = 0 | - | 0 | 0 | … | 0 | 0 | 0 | 1 | 1 | 0 | … | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 |
t = 1 | 1 | 0 | 0 | … | 0 | 0 | 0 | 1 | 1 | 1 | … | 0 | 0 | 0 | 1 | 0 | 0 | - | 0 |
t = 2 | 0 | 1 | 0 | … | 0 | 0 | 1 | 1 | 1 | 1 | … | 0 | 0 | 0 | 2 | 0 | 0 | - | 0 |
t = 3 | 1 | 0 | 1 | … | 0 | 0 | 0 | 1 | 1 | 1 | … | 0 | 0 | 0 | 3 | 0 | 0 | - | 0 |
t = 4 | 1 | 1 | 0 | … | 0 | 0 | 1 | 1 | 1 | 1 | … | 0 | 0 | 0 | 4 | 0 | 0 | - | 0 |
t = 5 | 0 | 1 | 1 | … | 0 | 0 | 1 | 1 | 1 | 1 | … | 0 | 0 | 0 | 5 | 0 | 0 | - | 0 |
t = 6 | 0 | 0 | 1 | … | 0 | 0 | 0 | 1 | 1 | 1 | … | 0 | 0 | 0 | 6 | 0 | 0 | - | 0 |
t = 7 | 0 | 0 | 0 | … | 0 | 0 | 0 | 1 | 1 | 1 | … | 0 | 0 | 0 | 7 | 0 | 0 | - | 0 |
t = 8 | 0 | 0 | 0 | … | 0 | 0 | 0 | 1 | 1 | 1 | … | 1 | 0 | 0 | 8 | 0 | 0 | - | 0 |
t = 9 | 1 | 0 | 0 | … | 1 | 0 | 0 | 1 | 1 | 1 | … | 1 | 1 | 1 | 9 | 0 | 0 | - | 0 |
t = 10 | 1 | 3 | 0 | … | 0 | 3 | 3 | 1 | 1 | 1 | … | 1 | 1 | 1 | 10 | 0 | 0 | - | 0 |
t = 11 | 1 | 6 | 0 | … | 1 | 2 | 3 | 1 | 1 | 1 | … | 1 | 1 | 1 | 11 | 1 | 2 | - | 0 |
t = 12 | 1 | 9 | 0 | … | 1 | 3 | 3 | 1 | 1 | 1 | … | 1 | 1 | 1 | 12 | 2 | 3 | 0 | 0 |
t = 13 | 0 | 12 | 0 | … | 0 | 3 | 3 | 1 | 1 | 1 | … | 1 | 1 | 1 | 13 | 3 | 3 | 1 | 1 |
t = 14 | 0 | 15 | 0 | … | 0 | 2 | 2 | 1 | 1 | 1 | … | 1 | 1 | 1 | 14 | 4 | 3 | 1 | 1 |
t = 15 | 0 | 16 | 0 | … | 0 | 2 | 2 | 1 | 1 | 1 | … | 1 | 1 | 1 | 15 | 5 | 3 | 1 | 1 |
t = 16 | 0 | 18 | 0 | … | 0 | 2 | 2 | 1 | 1 | 1 | … | 1 | 1 | 1 | 16 | 6 | 3 | 1 | 1 |
t = 17 | 0 | 20 | 0 | … | 0 | 2 | 2 | 2 | 2 | 1 | … | 1 | 1 | 1 | 1 | 7 | 3 | 1 | 1 |
t = 18 | 0 | 22 | 0 | … | 1 | 2 | 2 | 2 | 2 | 0 | … | 1 | 1 | 1 | 1 | 8 | 3 | 1 | 1 |
t = 19 | 0 | 24 | 0 | … | 1 | 3 | 2 | 2 | 2 | 0 | … | 1 | 1 | 1 | 1 | 1 | 8 | 1 | 1 |
t = 20 | 1 | 26 | 0 | … | 1 | 3 | 2 | 2 | 2 | 0 | … | 1 | 1 | 1 | 1 | 2 | 1 | 4 | 4 |
t = 21 | 0 | 29 | 0 | … | 5 | 7 | 7 | 6 | 6 | 0 | … | 5 | 1 | 1 | 1 | 3 | 7 | 1 | 1 |
t = 22 | 0 | 31 | 0 | … | 5 | 9 | 9 | 6 | 6 | 0 | … | 5 | 0 | 0 | 1 | 4 | 0 | 0 | 0 |
SN P System | SN P System with 2 Input for 2 Natural Number Subtraction ПSub1 | SN P System with One Input for 2 Natural Numbers Subtraction ПSub2 | SN P System with 1 Input for n Natural Numbers Subtraction ПSub3 | |||||||
---|---|---|---|---|---|---|---|---|---|---|
Parameter | ||||||||||
Number of Neurons | Complete Time | Number of Rules | Number of Neurons | Complete Time | Number of Rules | Number of Neurons | Complete Time | Number of Rules | ||
This work | 15 | k + 4 | 9 | 2k + 11 | 2k + 3 | 9 | 2k + 10 | nk + 5 | 15 | |
Zeng Xiang [23] | 12 | time free | 4 | - | - | - | - | - | - |
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Zhang, X.; Hu, Z.; Li, J.; Liu, R. Performing Arithmetic Operations with Locally Homogeneous Spiking Neural P Systems. Appl. Sci. 2023, 13, 8460. https://doi.org/10.3390/app13148460
Zhang X, Hu Z, Li J, Liu R. Performing Arithmetic Operations with Locally Homogeneous Spiking Neural P Systems. Applied Sciences. 2023; 13(14):8460. https://doi.org/10.3390/app13148460
Chicago/Turabian StyleZhang, Xu, Zongrong Hu, Jingyi Li, and Ran Liu. 2023. "Performing Arithmetic Operations with Locally Homogeneous Spiking Neural P Systems" Applied Sciences 13, no. 14: 8460. https://doi.org/10.3390/app13148460
APA StyleZhang, X., Hu, Z., Li, J., & Liu, R. (2023). Performing Arithmetic Operations with Locally Homogeneous Spiking Neural P Systems. Applied Sciences, 13(14), 8460. https://doi.org/10.3390/app13148460