A High-Power-Factor Dimmable LED Driver with Integrated Boost Converter and Half-Bridge-Topology Converter

Abstract

This paper proposes a dimmable light-emitting diode (LED) driver featuring a high power factor and zero-voltage switching on (ZVS). The circuit is obtained by integrating a boost converter and a dc-dc converter with half-bridge topology. The high power factor is achieved by operating the boost converter in discontinuous current mode (DCM). The LEDs are dimmed by the control scheme of asymmetrical pulse-width modulation (ASPWM). The developed circuit eliminates the inherited dc-offset current of the transformer in a conventional asymmetrical half-bridge converter by introducing a balance capacitor. Both active switches can operate at ZVS by freewheeling the boost inductor current and the transformer magnetizing current to discharge the energy stored in their parasitic capacitance. The circuit operation is analyzed in detailed, and mathematical equations are derived. Finally, a 115-W prototype circuit for driving high brightness LEDs was built and tested. The experimental results verify the feasibility of the proposed LED driver with satisfactory performance. It can achieve a high power factor and ZVS operation.

1. Introduction

The amount of power consumption for lighting applications accounts for around 15–20% of the total generated electric power. Therefore, any small increase in lighting efficiency will result in a significant reduction in energy consumption. For improving the illuminous efficiency of lighting sources, vast manpower and resource are engaged to develop light-emitting diodes (LEDs). Compared with traditional lighting sources, LED has the advantages of a small size, high luminous efficiency, and long life span and are the most promising lighting device [1,2,3,4,5].

Owing to the simple circuit topology and easy control, half-bridge converters are widely used in medium-and low-power applications. Nevertheless, the active switches of the half-bridge converter suffer from hard switching, resulting in high voltage/current stresses and high switching losses. In order to solve the problem of hard switching, an active clamp and snubber circuits are usually used to make the active switches operate at zero-voltage switching on (ZVS), leading to low voltage and/or current stresses [6,7,8,9]. In addition, the circuit efficiency can be effectively improved. However, these techniques require the use of additional auxiliary switches, diodes, and passive components to enable the active switch to operate at ZVS or zero-current switching off (ZCS). It These soft-switching techniques would increase the complexity and cost of the circuit. Besides, current loops in active clamp circuits or snubber circuits can cause additional conduction losses and even more switching losses.

Recently, in order to comply with the more stringent regulations such as IEC61000-3-2 class C, an additional alternating current-to-direct current (ac/dc) conversion stage is required to cascade in front of the dc/dc converter to perform the function of the power factor correction (PFC). For the sake of reducing circuit costs, many single-stage circuits have been developed for driving LEDs by integrating a PFC converter into the original LED driver [10,11,12,13,14,15]. Although these single-stage approaches can achieve a high power factor and low total current harmonic distortion (THDi), one or more active switches in these single-stage circuits still suffer from the hard switching problem. On the other hand, an LED driver with dimming capability is needed in many applications. Some single-stage approaches are derived by integration of a boost and a half-bridge resonant converter [14,15]. The half-bridge converters usually use an inductor-inductor-capacitor (LLC) or a capacitor-inductor-capacitor-inductor (CLCL) resonant tank to achieve ZVS. Frequency modulation control is usually used to achieve the dimming operation. Since the boost converter and the resonant converter share the same active switch, the switching frequency of the boost converter also varies to accomplish the dimming operation. Generally, the input power of the boost converter is inversely proportional to the switching frequency. In order to achieve wide dimming operation, the switching frequency should vary in a wide range. The higher the switching frequency, the lower the LED power. Moreover, higher switching frequency would incur more switching losses, leading to low efficiency at low power operation.

In single-stage circuits, a dc-link capacitor is usually required to absorb or release power due to the mismatch between input power and output power. The voltage across the dc-link capacitor varies when the LEDs are dimmed. When the dimming range is large, the voltage of the dc-link capacitor changes greatly. Generally, the methods of symmetrical pulse-width modulation (PWM) or asymmetrical pulse-width modulation (ASPWM) are often used to control the active switches to regulate LED power [16,17,18,19]. When both control schemes are compared, the voltage across the dc-link capacitor of the PWM scheme is higher than that of the ASPWM one [18,19]. Although the ASPWM scheme always incurs noticeable dc-offset current in the transformer, resulting in increasing transformer core loss [20], the dc-offset current can be easily eliminated by connecting a dc-balance capacitor in series with the primary winding.

Aiming to developing a dimmable LED driver with the features of a high power factor and ZVS, this manuscript proposes a single-stage circuit based on integrating a boost-type PFC converter and a half-bridge converter. The developed LED driver integrates the advantages of soft switching and PFC techniques, leading to high efficiency and a high power factor. Besides, it can achieve wide dimming range. The circuit operation is analyzed, and the mathematical equations for designing component parameters are generated. Finally, a 115-W prototype LED driver circuit is designed and implemented to validate the feasibility of the proposed circuit.

2. Proposed Circuit Configuration and Operation Analysis

2.1. Circuit Topology

Figure 1 shows the proposed circuit configuration of the LED driver. The half-bridge converter consists of two active switches (S₁, S₂), a transformer (T₁), a capacitor (C_b1), a diode rectifier (D₁–D₄), an output inductor (L_o), and an output capacitor (C_o). The diodes D_S1 and D_S2 are the intrinsic diodes of S₁ and S₂, respectively. L_m represents the mutual inductance of the transformer T₁. C_b1 is used to eliminate the dc-offset current in the transformer. S₁ and S₂ are operated by the control scheme of ASPWM to dim the LEDs.

A boost converter performs the function of power-factor correction which consists of an inductor L_PFC and the lower arm switch S₂. By operating the boost converter in discontinuous-conduction mode (DCM), the peak value of the inductor current i_LPFC will follow the track of the rectified input voltage v_in. The frequency of i_LPFC is far greater than the input-line frequency. The inductor L_f and the capacitor C_f form a low-pass filter which is used to filter out the high frequency component of i_LPFC. In this way, the input current can be close to a sinusoidal waveform and in phase with the input-line voltage, thus achieving a high power factor. The magnetizing current in L_m can be used to remove the energy accumulated on parasitic capacitors of S₁ and S₂ to attain ZVS operation. Thus, the switching losses can be drastically reduced, and the operating efficiency can be promoted.

2.2. Operation Analysis

For simplifying the operation analysis, the following assumptions are made.

• Ignoring the conduction voltage drop for all switching devices, such as diodes and active switches.
• The switching frequency is much greater than the input-line frequency.
• Ignoring voltage ripples on all capacitors because the Cbus and Cb1 are large enough.
• The output inductor Lo is large enough, and its current is assumed to be a constant ILo.

At steady state, the operation of the proposed circuit can be divided into seven modes according to the conducting status of the semiconductor devices in one high-frequency switching cycle. These operation modes and the theoretical voltage and current waveforms of the key components are shown in Figure 2 and Figure 3, respectively. For simplifying the circuit analysis, the low-pass filter and the diode rectifier at the input side are represented by the rectified voltage v_rec, and the LED string is represented by its equivalent resistance R_LED. The detailed description of each operation mode is as follows.

A. Mode I (t₀ < t < t₁)

As illustrated in Figure 2a, Mode I begins at the time when the gate signal v_GS1 turns from a high level to a low level. For maintaining the magnetic flux in L_m, the magnetizing current i_Lm flows via the capacitor C_b1 and the parasitic capacitance of S₂. The parasitic capacitance of S₂ is discharged, and the voltage across S₂ decreases. Generally, the parasitic capacitance of the active switch is quite small, and it is completely discharged very rapidly. When the energy on the parasitic capacitance of S₂ is totally released, i_Lm diverts from the parasitic capacitance to the intrinsic diode D_S2. Hereafter, the voltage across S₂, v_DS2 is clamped at zero volts. Thus, the ZVS operation can be achieved. The voltage across the primary winding is equal to −V_Cb1, and diodes D₂ and D₃ are on, and the current in the secondary winding i_Ts flows through D₂, D₃ and L_o. During this interval, i_Ts is equal to the output inductor current I_Lo. The i_Lm and the primary current i_Tp can be written as Equations (1) and (2), respectively.

$$i_{Lm}\left(t\right)=i_{Lm}\left(t_0\right)-\frac{V_{Cb1}}{L_m}\left(t-t_0\right),$$

(1)

$$i_{Tp}(t)=i_{Lm}(t)-\frac{N_S}{N_P}{I}_{Lo},$$

(2)

where N_S and N_P represent the turns of the primary winding and the secondary winding, respectively.

Since S₂ is clamped at zero volts, the voltage across the PFC inductor is equal to the rectified input voltage. The PFC current increases linearly and is expressed as:

$$i_{LPFC}(t)=\frac{v_{rec}\left(t\right)}{L_{PFC}}(t-t_0)=\frac{V_m\left|\sin \left(2\pi f_{L}t\right)\right|}{L_{PFC}}(t-t_0),$$

(3)

where V_m and f_L represent the amplitude and frequency of the input line voltage, respectively. After a very short deadtime, the gate signal v_GS2 turns from a low level to a high level in this mode. Based on Equations (1)–(3), i_Tp decreases. On the contrary, i_LPFC increases. The mode ends at the time when i_LPFC becomes higher than i_Tp.

B. Mode II (t₁ < t < t₂)

The current i_S2 is the difference between i_LPFC and i_Tp. Hence, i_S2 changes its polarity when i_LPFC becomes higher than i_Tp and S₂ is turned on at zero voltage. During this mode, the current equations are the same as Equations (1)–(3). Current i_LPFC keeps increasing while i_Tp keeps decreasing. When i_Tp decreases to zero, the circuit operation enters Mode III.

C. Mode III (t₂ < t < t₃)

The current i_Tp becomes negative at the beginning of this mode. Both i_Tp and i_LPFC flow through S₂. The current i_LPFC keeps increasing while the current i_Tp keeps decreasing. As soon as the gate signal v_GS2 turns from a high level to a low level, the circuit operation enters Mode IV.

D. Mode IV (t₃ < t < t₄)

Both the current i_LPFC and i_Tp divert from S₂ to flow through the parasitic capacitance of S₁ when S₂ is turned off. The parasitic capacitance of S₁ is discharged, and the voltage across S₁, v_DS1 decreases. Since the parasitic capacitance is quite small, it is completely discharged very rapidly. When energy on the parasitic capacitance of S₁ is totally released, i_LPFC and i_Tp divert from the parasitic capacitance to flow through the intrinsic diode D_S1. The voltage across S₁, v_DS1 is clamped at zero volts. Thus, the ZVS operation can be achieved. During this mode, the voltage across L_PFC and the transformer primary winding can be respectively expressed as

$$v_{LPFC}\left(t\right)=v_{rec}\left(t\right)-V_{Cbus},$$

(4)

$$v_{Tp}(t)=V_{Cbus}-V_{Cb1},$$

(5)

The current i_LPFC can be expressed as

$$i_{LPFC}(t)=i_{LPFC}\left(t_3\right)+\frac{v_{rec}\left(t\right)-V_{Cbus}}{L_{PFC}}(t-t_3),$$

(6)

Regarding a boost-type PFC converter, the dc-link voltage should be designed to be higher than the rectified voltage; therefore, the inductor current i_LPFC starts to decrease. The magnetizing current i_Lm and the primary current can be expressed as

$$i_{Lm}\left(t\right)=i_{Lm}\left(t_3\right)+\frac{V_{Cbus}-V_{Cb1}}{L_m}\left(t-t_3\right),$$

(7)

$$i_{Tp}(t)=i_{Lm}(t)+\frac{N_S}{N_P}{I}_{Lo},$$

(8)

Since the primary voltage is positive, both i_Lm and i_Tp increase. On the other hand, the voltage across the secondary winding is positive. Therefore, the secondary winding supplies current to flow through D₁ and D₄ to the output inductor. After a very short deadtime, the gate signal v_GS1 turns from a low level to a high level. This mode ends when i_Tp becomes zero and changes polarity.

E. Mode V (t₄ < t < t₅)

In this mode, i_Tp is smaller than i_LPFC. The current flowing through D_S1 is equal to i_LPFC minus i_Tp. When i_Tp becomes higher than i_LPFC, S₁ is turned on at zero volts, and the circuit enters Mode VI.

F. Mode VI (t₅ < t < t₆)

In Figure 2f, v_GS1 remains at high level and i_LPFC keeps decreasing. When i_LPFC decreases to zero, the circuit enters Mode VII.

G. Mode VII (t₆ < t < t₇)

In Figure 2g, the trigger signal v_GS1 remains at a high state. The dc-link capacitor C_bus keeps supplying energy via the transformer to the output. At the instant when v_GS1 turns into a low state, this mode ends and the circuit operation enters Mode I of the next high-frequency cycle.

3. Circuit Parameter Design

A. Transformer turn ratio n

To simplify the analysis, the voltage across the primary windings of the transformer is idealized as a square-wave voltage source with the amplitude swinging between V_Cbus–V_Cb1 and −V_Cb1, as shown in Figure 4. With the turn ratio of the primary winding to the secondary winding being n:1, the peak-to-peak value across the transformer secondary winding is V_Cbus/n. Referring to Figure 4, it is known that the average value of the voltage across the primary winding is zero.

$$\left(V_{cbus}-V_{cb1}\right)(1-D)T-V_{cb1}DT=0,$$

(9)

where D and T are the duty ratio and the switching period of the active switch S₂. From (9), the following can be obtained:

$$V_{cb1}=\left(1-D\right)V_{cbus},$$

(10)

At steady-state operation, the average voltage of the inductor is zero, i.e., the average value of the rectified voltage of the secondary winding is equal to the output voltage.

$$V_{CD}=\frac{\left(V_{cbus}-V_{cb1}\right)(1-D)+V_{cb1}D}{n}=V_o,$$

(11)

Substituting Equation (10) into Equation (11), the transformer turn ratio can be expressed as

$$n=\frac{2D(1-D)V_{cbus}}{V_o},$$

(12)

B. Output inductor L_o

The selection of the output filter inductance L_o is related to its current ripple. During the conducting interval of S₂, the current variation of L_o can be expressed as

$$\Delta i_{Lo}=\frac{DT\left(\left(1-D\right)V_{Cbus}/n-V_o\right)}{L_o},$$

(13)

By rearranging Equation (13), the inductance of the output inductor can be expressed as:

$$L_o=\frac{DT\left(\left(1-D\right)V_{Cbus}/n-V_o\right)}{\Delta i_{Lo}},$$

(14)

C. PFC Inductor L_PFC

In order to pursue the high power factor, the boost-type PFC converter should be operated at DCM. The inductance of the PFC inductor is inversely proportional to the output power and can be expressed as follows [21].

$$L_{PFC}=\frac{\eta D^2{V}_m{}^2}{2P_o{f}_s}\cdot y,$$

(15)

where P_o is the output power; f_s is the switching frequency; η is the circuit energy-conversion efficiency, and y is expressed as Equation (16).

$$y=\frac{k^3}{\sqrt{k^2-1}}\left(1+\frac{2}{\pi }{\sin }^{-1}\frac{1}{k}\right)-k^2-\frac{2}{\pi }\cdot k\left(k\equiv \frac{V_{Cbus}}{V_m}\right),$$

(16)

4. Illustrative Example and Experimental Results

A prototype of the proposed asymmetrical half-bridge dimmable LED driver was implemented and tested. The driven load is specified as 115 W (96 V/1.2 A), and the associated circuit specification is listed in

Table 1. Circuit Specification.

Input voltage Vin	110 +/− 10% Vrms, 60 Hz
Rated output current Io	1.2 A
Rated output voltage Vo	96 V
Rated output power Po	115 W
Switching frequency fs	50 kHz
Full-load duty cycle D	0.45
DC-link Voltage VCbus at full load	310 V

. The parameter design, including the transformer turn ratio, the PFC inductor, and the output inductor, is based on the derivation in Section 3. The input filter inductor L_f and input filter capacitor C_f are selected with reference to [22]. By assigning the voltage ripple to be less than 5%, the value of the dc-link capacitor C_bus is obtained with reference to [23]. The component parameters of the practical implementation are listed in

Table 2. Component parameters.

Transformer turn-ratio n	Np:Ns = 1.4:1
Block capacitor Cb1	0.1 μF
PFC inductor LPFC	0.340 mH
Input filter inductor Lf	2.2 mH
Input filter capacitor Cf	0.47 μF
Output filter inductor Lo	2.2 mH
Output filter capacitor Co	470 μF
DC-link capacitor Cbus	100 μF
MOSFET S1, S2	TOSHIBA 2SK2611

.

Figure 5 shows the dimming control circuit that mainly consists of a pulse-width-modulation controller (TL494) and a half-bridge driver (IR2302). The TL494 outputs a square-wave voltage of which the oscillation frequency is determined by the capacitor (C₂) connected to pin 5 and the resistor connected to pin 5 (R₂), and the pulse width is determined by the voltage at pin 4. The output of TL494 is connected to pin 2 of the IR2320. The IR2320 features a high-pulse current buffer stage designed for minimum driver cross-conduction. It outputs two complementary square-wave voltages (HO and LO) used to drive the high and low side MOSFETs (S1 and S2), respectively. The high-side gate driver (HO) is in phase with the logic input (pin 2). Therefore, by varying the resistor R₁ to adjust the pulse width of the TL494 output (E1), ASPWM control is achieved with respect to dimming the LEDs.

Figure 6 shows the measured voltages of the active switches v_GS1, v_GS2, v_DS1, v_DS2. It is obvious that prior to the instant when the gate voltages reach a high level, the voltages across the power switches reach nearly zero. This ensures ZVS operation of the active switches. Figure 7 shows the measured diode currents. As expected, these waveforms are consistent with the theoretical ones.

The LEDs are dimmed from 100% to 4% rated power. Figure 8 shows the waveforms of the gate voltage of S₂, the transformer secondary winding current, and the output filter inductor current at different output powers. It can be seen that the LED power is controlled by varying the duty ratio of S₂. From (15), for a given PFC inductor, the output power is proportional to the square of the duty ratio. As seen in Figure 7 and Figure 8, there are negative and positive spike currents in the transformer secondary winding and the diodes on its secondary side. In addition, the negative and positive spike currents happen simultaneously. The spike current is the reverse recovery current of the diode. It is seen that the negative spike current happens when a pair of diodes are turned off, and this spike current flows through the transformer secondary winding and the other pair of diodes. Therefore, the positive spike current can be seen in the secondary winding and the other pair of diodes. Figure 9 shows the measured waveforms of the input voltage and PFC inductor current under heavy and light loads. Regardless of a heavy or light load, the peak values of PFC inductor currents always follow the track of the input voltage. Also, the PFC inductor is energized and de-energized at a very high frequency which is hundreds of multiples higher than the input-line frequency. Additionally, the PFC inductor currents coincide well with the input voltage at zero-crossing points, thus warranting the active power-factor correction of the proposed circuit. The measured power factor at different output powers is illustrated in Figure 10. At rated output power (P_o = 115 W), the power factor is as high as 0.99. The power factor decreases as the output power decreases the power factor decreases to about 0.92 at 4% rated power. Figure 11 shows the harmonic spectrum of the input line current at the rated power operation. It can be seen that all harmonics are in compliance with the IEC 61000-3-2 Class C standard. The measured THDi is 12.64%. Figure 12 shows the prototype of the proposed LED driver.

5. Conclusions

This study developed and designed a single-stage dimmable LED driver. The circuit topology is derived by integrating a boost converter and an asymmetrical half-bridge converter. The lower-arm switch of the half-bridge converter is shared with the boost converter. The boost converter plays the role of the PFC converter. It operates at DCM to ensure a high power factor at the input line. By freewheeling the PFC inductor and the magnetizing current of the transformer to discharge the parasitic capacitance of the active switches, both active switches can be operated at ZVS, leading to high circuit efficiency. The measured circuit efficiency at rated output power is 92.7%. Experiments are performed to validate the effectiveness of the proposed circuit. The LEDs are dimmed by varying the duty ratio of the active switch. A high power factor is ensured when the LEDs are dimmed from 100% to 4% rated power.