# A High-Power-Factor Dimmable LED Driver with Integrated Boost Converter and Half-Bridge-Topology Converter

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## Abstract

**:**

## 1. Introduction

## 2. Proposed Circuit Configuration and Operation Analysis

#### 2.1. Circuit Topology

_{1}, S

_{2}), a transformer (T

_{1}), a capacitor (C

_{b}

_{1}), a diode rectifier (D

_{1}–D

_{4}), an output inductor (L

_{o}), and an output capacitor (C

_{o}). The diodes D

_{S1}and D

_{S}

_{2}are the intrinsic diodes of S

_{1}and S

_{2}, respectively. L

_{m}represents the mutual inductance of the transformer T

_{1}. C

_{b1}is used to eliminate the dc-offset current in the transformer. S

_{1}and S

_{2}are operated by the control scheme of ASPWM to dim the LEDs.

_{PFC}and the lower arm switch S

_{2}. By operating the boost converter in discontinuous-conduction mode (DCM), the peak value of the inductor current i

_{LPFC}will follow the track of the rectified input voltage v

_{in}. The frequency of i

_{LPFC}is far greater than the input-line frequency. The inductor L

_{f}and the capacitor C

_{f}form a low-pass filter which is used to filter out the high frequency component of i

_{LPFC}. In this way, the input current can be close to a sinusoidal waveform and in phase with the input-line voltage, thus achieving a high power factor. The magnetizing current in L

_{m}can be used to remove the energy accumulated on parasitic capacitors of S

_{1}and S

_{2}to attain ZVS operation. Thus, the switching losses can be drastically reduced, and the operating efficiency can be promoted.

#### 2.2. Operation Analysis

- Ignoring the conduction voltage drop for all switching devices, such as diodes and active switches.
- The switching frequency is much greater than the input-line frequency.
- Ignoring voltage ripples on all capacitors because the Cbus and Cb1 are large enough.
- The output inductor Lo is large enough, and its current is assumed to be a constant ILo.

_{rec}, and the LED string is represented by its equivalent resistance R

_{LED}. The detailed description of each operation mode is as follows.

_{0}< t < t

_{1})

_{GS1}turns from a high level to a low level. For maintaining the magnetic flux in L

_{m}, the magnetizing current i

_{Lm}flows via the capacitor C

_{b1}and the parasitic capacitance of S

_{2}. The parasitic capacitance of S

_{2}is discharged, and the voltage across S

_{2}decreases. Generally, the parasitic capacitance of the active switch is quite small, and it is completely discharged very rapidly. When the energy on the parasitic capacitance of S

_{2}is totally released, i

_{Lm}diverts from the parasitic capacitance to the intrinsic diode D

_{S2}. Hereafter, the voltage across S

_{2}, v

_{DS2}is clamped at zero volts. Thus, the ZVS operation can be achieved. The voltage across the primary winding is equal to −V

_{Cb1}, and diodes D

_{2}and D

_{3}are on, and the current in the secondary winding i

_{Ts}flows through D

_{2}, D

_{3}and L

_{o}. During this interval, i

_{Ts}is equal to the output inductor current I

_{Lo}. The i

_{Lm}and the primary current i

_{Tp}can be written as Equations (1) and (2), respectively.

_{S}and N

_{P}represent the turns of the primary winding and the secondary winding, respectively.

_{2}is clamped at zero volts, the voltage across the PFC inductor is equal to the rectified input voltage. The PFC current increases linearly and is expressed as:

_{m}and f

_{L}represent the amplitude and frequency of the input line voltage, respectively. After a very short deadtime, the gate signal v

_{GS2}turns from a low level to a high level in this mode. Based on Equations (1)–(3), i

_{Tp}decreases. On the contrary, i

_{LPFC}increases. The mode ends at the time when i

_{LPFC}becomes higher than i

_{Tp}.

_{1}< t < t

_{2})

_{S2}is the difference between i

_{LPFC}and i

_{Tp}. Hence, i

_{S2}changes its polarity when i

_{LPFC}becomes higher than i

_{Tp}and S

_{2}is turned on at zero voltage. During this mode, the current equations are the same as Equations (1)–(3). Current i

_{LPFC}keeps increasing while i

_{Tp}keeps decreasing. When i

_{Tp}decreases to zero, the circuit operation enters Mode III.

_{2}< t < t

_{3})

_{Tp}becomes negative at the beginning of this mode. Both i

_{Tp}and i

_{LPFC}flow through S

_{2}. The current i

_{LPFC}keeps increasing while the current i

_{Tp}keeps decreasing. As soon as the gate signal v

_{GS2}turns from a high level to a low level, the circuit operation enters Mode IV.

_{3}< t < t

_{4})

_{LPFC}and i

_{Tp}divert from S

_{2}to flow through the parasitic capacitance of S

_{1}when S

_{2}is turned off. The parasitic capacitance of S

_{1}is discharged, and the voltage across S

_{1}, v

_{DS1}decreases. Since the parasitic capacitance is quite small, it is completely discharged very rapidly. When energy on the parasitic capacitance of S

_{1}is totally released, i

_{LPFC}and i

_{Tp}divert from the parasitic capacitance to flow through the intrinsic diode D

_{S}

_{1}. The voltage across S

_{1}, v

_{DS1}is clamped at zero volts. Thus, the ZVS operation can be achieved. During this mode, the voltage across L

_{PFC}and the transformer primary winding can be respectively expressed as

_{LPFC}can be expressed as

_{LPFC}starts to decrease. The magnetizing current i

_{Lm}and the primary current can be expressed as

_{Lm}and i

_{Tp}increase. On the other hand, the voltage across the secondary winding is positive. Therefore, the secondary winding supplies current to flow through D

_{1}and D

_{4}to the output inductor. After a very short deadtime, the gate signal v

_{GS1}turns from a low level to a high level. This mode ends when i

_{Tp}becomes zero and changes polarity.

_{4}< t < t

_{5})

_{Tp}is smaller than i

_{LPFC}. The current flowing through D

_{S1}is equal to i

_{LPFC}minus i

_{Tp}. When i

_{Tp}becomes higher than i

_{LPFC}, S

_{1}is turned on at zero volts, and the circuit enters Mode VI.

_{5}< t < t

_{6})

_{GS1}remains at high level and i

_{LPFC}keeps decreasing. When i

_{LPFC}decreases to zero, the circuit enters Mode VII.

_{6}< t < t

_{7})

_{GS1}remains at a high state. The dc-link capacitor C

_{bus}keeps supplying energy via the transformer to the output. At the instant when v

_{GS1}turns into a low state, this mode ends and the circuit operation enters Mode I of the next high-frequency cycle.

## 3. Circuit Parameter Design

_{Cbus}–V

_{Cb1}and −V

_{Cb1}, as shown in Figure 4. With the turn ratio of the primary winding to the secondary winding being n:1, the peak-to-peak value across the transformer secondary winding is V

_{Cbus}/n. Referring to Figure 4, it is known that the average value of the voltage across the primary winding is zero.

_{2}. From (9), the following can be obtained:

_{o}

_{o}is related to its current ripple. During the conducting interval of S

_{2}, the current variation of L

_{o}can be expressed as

_{PFC}

_{o}is the output power; f

_{s}is the switching frequency; η is the circuit energy-conversion efficiency, and y is expressed as Equation (16).

## 4. Illustrative Example and Experimental Results

_{f}and input filter capacitor C

_{f}are selected with reference to [22]. By assigning the voltage ripple to be less than 5%, the value of the dc-link capacitor C

_{bus}is obtained with reference to [23]. The component parameters of the practical implementation are listed in Table 2.

_{2}) connected to pin 5 and the resistor connected to pin 5 (R

_{2}), and the pulse width is determined by the voltage at pin 4. The output of TL494 is connected to pin 2 of the IR2320. The IR2320 features a high-pulse current buffer stage designed for minimum driver cross-conduction. It outputs two complementary square-wave voltages (HO and LO) used to drive the high and low side MOSFETs (S1 and S2), respectively. The high-side gate driver (HO) is in phase with the logic input (pin 2). Therefore, by varying the resistor R

_{1}to adjust the pulse width of the TL494 output (E1), ASPWM control is achieved with respect to dimming the LEDs.

_{GS1}, v

_{GS2}, v

_{DS1}, v

_{DS2}. It is obvious that prior to the instant when the gate voltages reach a high level, the voltages across the power switches reach nearly zero. This ensures ZVS operation of the active switches. Figure 7 shows the measured diode currents. As expected, these waveforms are consistent with the theoretical ones.

_{2}, the transformer secondary winding current, and the output filter inductor current at different output powers. It can be seen that the LED power is controlled by varying the duty ratio of S

_{2}. From (15), for a given PFC inductor, the output power is proportional to the square of the duty ratio. As seen in Figure 7 and Figure 8, there are negative and positive spike currents in the transformer secondary winding and the diodes on its secondary side. In addition, the negative and positive spike currents happen simultaneously. The spike current is the reverse recovery current of the diode. It is seen that the negative spike current happens when a pair of diodes are turned off, and this spike current flows through the transformer secondary winding and the other pair of diodes. Therefore, the positive spike current can be seen in the secondary winding and the other pair of diodes. Figure 9 shows the measured waveforms of the input voltage and PFC inductor current under heavy and light loads. Regardless of a heavy or light load, the peak values of PFC inductor currents always follow the track of the input voltage. Also, the PFC inductor is energized and de-energized at a very high frequency which is hundreds of multiples higher than the input-line frequency. Additionally, the PFC inductor currents coincide well with the input voltage at zero-crossing points, thus warranting the active power-factor correction of the proposed circuit. The measured power factor at different output powers is illustrated in Figure 10. At rated output power (P

_{o}= 115 W), the power factor is as high as 0.99. The power factor decreases as the output power decreases the power factor decreases to about 0.92 at 4% rated power. Figure 11 shows the harmonic spectrum of the input line current at the rated power operation. It can be seen that all harmonics are in compliance with the IEC 61000-3-2 Class C standard. The measured THDi is 12.64%. Figure 12 shows the prototype of the proposed LED driver.

## 5. Conclusions

## Author Contributions

## Funding

## Conflicts of Interest

## References

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**Figure 2.**Operation modes. (

**a**) Mode I, (

**b**) Mode II, (

**c**) Mode III, (

**d**) Mode VI, (

**e**) Mode V, (

**f**) Mode VI, (

**g**) Mode VII.

**Figure 6.**Voltage waveforms of active switches. (v

_{GS1}and v

_{GS}

_{2}: 10V/div, v

_{DS1}and v

_{DS}

_{2}: 200 V/div, Time: 5 μs/div).

**Figure 7.**Current waveforms of rectifying diodes. (i

_{D1}, i

_{D2}, i

_{D3}, i

_{D4}: 1 A/div, Time: 10 μs /div).

**Figure 8.**Waveforms of v

_{GS2}, i

_{Ts}, and i

_{Lo}at (

**a**) 100%, (

**b**) 50%, (

**c**) 25%, and (

**d**) 4% rated power. (v

_{GS2}: 10 V/div, i

_{Ts}: 2 A/div, i

_{Lo}: 1 A/div, Time: 10 μs/div).

**Figure 9.**Waveforms of the input voltage and PFC inductor current. (

**a**) 100% and (

**b**) 4% rated power. (v

_{in}: 100 V/div, i

_{PFC}: 1 A/div, Time: 5 ms/div).

Input voltage V_{in} | 110 +/− 10% V_{rms}, 60 Hz |

Rated output current I_{o} | 1.2 A |

Rated output voltage V_{o} | 96 V |

Rated output power P_{o} | 115 W |

Switching frequency f_{s} | 50 kHz |

Full-load duty cycle D | 0.45 |

DC-link Voltage V_{Cbus} at full load | 310 V |

Transformer turn-ratio n | N_{p}:N_{s} = 1.4:1 |

Block capacitor C_{b1} | 0.1 μF |

PFC inductor L_{PFC} | 0.340 mH |

Input filter inductor L_{f} | 2.2 mH |

Input filter capacitor C_{f} | 0.47 μF |

Output filter inductor L_{o} | 2.2 mH |

Output filter capacitor C_{o} | 470 μF |

DC-link capacitor C_{bus} | 100 μF |

MOSFET S_{1}, S_{2} | TOSHIBA 2SK2611 |

© 2020 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).

## Share and Cite

**MDPI and ACS Style**

Cheng, H.-L.; Chang, Y.-N.; Hwang, L.-C.; Yen, H.-C.; Chan, S.-Y.; Yang, W.-F.
A High-Power-Factor Dimmable LED Driver with Integrated Boost Converter and Half-Bridge-Topology Converter. *Appl. Sci.* **2020**, *10*, 2775.
https://doi.org/10.3390/app10082775

**AMA Style**

Cheng H-L, Chang Y-N, Hwang L-C, Yen H-C, Chan S-Y, Yang W-F.
A High-Power-Factor Dimmable LED Driver with Integrated Boost Converter and Half-Bridge-Topology Converter. *Applied Sciences*. 2020; 10(8):2775.
https://doi.org/10.3390/app10082775

**Chicago/Turabian Style**

Cheng, Hung-Liang, Yong-Nong Chang, Lain-Chyr Hwang, Hau-Chen Yen, Shun-Yu Chan, and Wen-Fu Yang.
2020. "A High-Power-Factor Dimmable LED Driver with Integrated Boost Converter and Half-Bridge-Topology Converter" *Applied Sciences* 10, no. 8: 2775.
https://doi.org/10.3390/app10082775