Practical Submodule Capacitor Sizing for Modular Multilevel Converter Considering Grid Faults

Abstract

Submodule (SM) capacitors are key elements in the modular multilevel converter (MMC), the design of which influences the entire system performance. In practical cases, SM capacitor sizing must consider the abnormal system operation (e.g., grid faults). In order to find a clear design boundary for SM capacitors, a practical capacitor sizing method is presented for the first time in this paper, considering the grid-fault-ride-through operation of the MMC, impact of MMC control system, and aging mechanism of capacitors. The SM capacitor rated voltage, capacitance, ESR, thermal resistance, and lifetime can be decided to ensure reliable operations of the MMC during grid faults. The effectiveness of the proposed method has been verified through experimental tests on a down-scale MMC system.

1. Introduction

Several commercial modular multilevel converter (MMC) projects have been deployed in the past few decades [1,2,3]. Compared with the traditional line-commutated converter (LCC), the MMC has many competitive advantages, e.g., low switching frequency, high conversion efficiency, strong scalability and reduced harmonic distortion [4,5,6,7,8,9]. As a key part in the MMC, the SM capacitors must achieve high reliability in industrial projects, due to their high-voltage and high-power operating environment. Moreover, according to the national grid code shown in [10], the ability of grid-fault-ride-through is required for grid-tied MMCs. Especially in countries such as Germany and Canada, the converters must stay connected to the grid when a 100% voltage dip [11,12] appears. These unexpected grid fault operation will bring extra voltage stress on SM devices (IGBTs and capacitors), which is one of the critical reasons leading to system-level failure [13,14,15,16]. To avoid this problem, the SM capacitor is normally over-designed in practical cases, causing the rise of size and cost of the overall system. Thus, an optimized SM capacitor sizing method considering grid fault conditions is necessary for the practical MMC design.

Some efforts have been devoted to the SM capacitor sizing to ensure the steady-state operation of MMCs [17,18,19,20]. For instance, an SM capacitor sizing method is given in [17], based on the energy storage requirement of each SM. Dimensioning of SM capacitors considering energy fluctuation, ripple voltage is given in [18]. The minimum size for the SM capacitors to keep their voltage fluctuation is given in [19]. A computational design procedure in the aspects of maximum SM voltage, SM ripple voltage, and current stress is given in [20], considering the impact of the modulation index and the instantaneous power output. However, these methods assume that the system operates in steady-state with normal grid conditions, which cannot be used to predict the SM voltage during grid faults. To solve this problem, the control method of the MMC under unbalanced grid conditions is discussed in [21] and the literature [22] gives the mathematical model of the SM voltage, considering the positive- and negative-sequence of grid voltages and the MMC arm currents.

The above solutions can be used for SM capacitor sizing when the system operates in steady-state. However, the SM voltage is also affected by other factors, such as control strategies, modulation methods, circuit configurations, etc. For instance, the impact of the circulating current suppresion control (CCSC) on SM capacitor voltage ripples under different unbalanced AC grid conditions is discussed in [23]. With a second-order circulating current control [24], the SM voltage ripple can be reduced, i.e., a lower SM capacitance is required. An improved DC-loop regulator is proposed in [25] to suppress the capacitor voltage fluctuations. Considering unbalanced grid conditions, the DC-link voltage ripple is regulated through an arm voltage feed-forward control [26]. The interaction between the MMC modulation methods and the SM voltage stress is discussed in [27]. By applying a power decoupling circuit to each SM, the voltage ripple can be suppressed [28]. Hence, the sizing of SM capacitor should take the system control schemes into consideration.

In addition, the SM capacitor sizing should also consider the transient state of the MMC during grid faults, which may induce catastrophic damage to the SM. To study the transient behavior of MMC system, a few literature works have been conducted [16,29,30]. A time-domain transient SM voltage analysis is shown in [16]. By taking the grid current control into account, the transient SM voltage response during grid faults is discussed in [29]. In Ref. [30], the transient response of CCSC and its impact on SM voltage are analyzed.

Considering the impact factors above, the aim of this paper is ensure the reliability of SM capacitors when the system operates both in normal and grid fault states. Thus, a practical SM capacitor sizing method is proposed in this paper. Accordingly, the SM capacitor rated voltage and capacitance are chosen based on the grid fault operation principle of the MMC, including the transient voltage stress on SM. Moreover, the ESR, thermal resistance, and rated lifetime of the SM capacitor is chosen considering the aspect of reliability requirement. The rest of this paper is structured as follows: Section 2 discusses the operation principles and control schemes of the MMC system. The transient state SM voltage is analyzed in Section 3, where an analytical model is proposed. Design considerations of the MMC system are provided in Section 4, while the SM capacitor selection procedure is given in Section 5. A detailed design example of a down-scale MMC system is given in Section 6, where experimental tests are performed to validate the proposed method. Finally, concluding remarks are presented.

2. Steady-State Analysis of SM Capacitor Voltage

A three-phase MMC topology is shown in Figure 1. Each arm of the MMC contains N identical half-bridge SMs and one series-connected arm inductor L_a. The SM is formed by two IGBTs and a parallel SM capacitor C_sm. The SM voltage v_sm is defined as the voltage across each SM capacitor, while the DC-bus voltage is considered as a constant denoted by V_dc.The AC output of the MMC is connected to the grid through a three-phase $\Delta$/Y transformer. Thus, there will not be any zero-sequence currents on the converter side during grid fault conditions.

To simplify the analysis, it is assumed that the voltage across each SM is well-balanced. Thus, an equivalent circuit can be derived for each phase-leg of the MMC, as shown in Figure 2. All the SMs in each arm are combined into a single equivalent capacitor being $C_{eq}=C_{sm}/N$. The equivalent capacitors hold the total voltage stress of the upper arm v_uj and lower arm v_lj, where j indicates the phase (j = a, b, c). The switching devices of each SM are replaced by a pair of equivalent controlled-sources. The grid phase voltage and output current of each phase are represented by v_j and i_j. The circulating current is denoted as i_cj. The insertion index of the upper and lower arms is represented by n_uj and n_lj, while the arm current is defined as i_uj and i_lj. Due to the symmetrical characteristic of the MMC system, only the expression of upper arm is given.

In steady-state, the grid voltage and current of each phase can be expressed as

$$v_j={\widehat{V}}_{j}cos\left({\omega }_{1}t\right)$$

(1)

$$i_j={\widehat{I}}_{j}cos\left({\omega }_{1}t-{\varphi }_j\right)$$

(2)

where ${\omega }_1$ is the fundamental line frequency, ${\varphi }_j$ is the power factor angle, and ${\widehat{V}}_j$ and ${\widehat{I}}_j$ are the peak value of grid voltage and current.

The total energy variation of the upper arm is analyzed in [17] with

$$e_{uj}=\frac{C_{sm}{V}_{dc}^2}{2N}+\frac{V_{dc}{\widehat{I}}_j}{16{\omega }_1}[4sin({\omega }_{1}t-{\varphi }_j)-msin(2{\omega }_{1}t-{\varphi }_j)-2m^{2}sin\left({\omega }_{1}t\right)cos\left({\varphi }_j\right)]$$

(3)

where m is the modulation index, given by $m=2{\widehat{V}}_j/V_{dc}$.

Meanwhile, the energy storage in the upper arm can be represented as

$$e_{uj}=\frac{1}{2}{C}_{eq}{v}_{uj}^2=\frac{1}{2}N{C}_{sm}{v}_{sm}^2$$

(4)

Combining Equations (3) and (4), the voltage stress of an SM capacitor in the upper arm can be given as

$$v_{smj}=\sqrt{\frac{V_{dc}^2}{N^2}+\frac{V_{dc}{\widehat{I}}_j}{8N{C}_{sm}{\omega }_1}\mathbf{F}}$$

(5)

where

$$\mathbf{F}=4sin({\omega }_{1}t-{\varphi }_j)-msin(2{\omega }_{1}t-{\varphi }_j)-2m^{2}sin\left({\omega }_{1}t\right)cos\left({\varphi }_j\right)$$

(6)

To study the steady-state SM voltage ripple, the waveform of F function under different operating point is shown in Figure 3. Hence, the operating voltage boundary of SM capacitors in steady-state can be obtained as

$$V_{ssmax}=\sqrt{\frac{V_{dc}^2}{N^2}+\frac{V_{dc}{\widehat{I}}_j}{8N{C}_{sm}{\omega }_1}{\mathbf{F}}_{max}}$$

(7)

$$V_{ssmin}=\sqrt{\frac{V_{dc}^2}{N^2}+\frac{V_{dc}{\widehat{I}}_j}{8N{C}_{sm}{\omega }_1}{\mathbf{F}}_{min}}$$

(8)

where F_max and F_min are the maximum and minimum value of the F function.

3. Transient SM Capacitor Voltage during Grid Faults

3.1. System Dynamics and Control Schemes

Based on Figure 2, the dynamics of an MMC can be described as

$$L_a\frac{d{i}_{cj}}{dt}=\frac{V_{dc}}{2}-v_{cj}$$

(9)

$$\frac{L_a}{2}\frac{d{i}_j}{dt}=v_{sj}-v_j$$

(10)

$$C_{eq}\frac{d{v}_{uj}}{dt}=n_{uj}{i}_{uj}$$

(11)

$$i_{uj}=i_{cj}+\frac{1}{2}{i}_j$$

(12)

where v_cj is the voltage driving the circulating current through each phase-leg, and v_sj is the differential voltage controlling the current injected into the grid. Accordingly, v_cj and v_sj are given as

$$v_{cj}=\frac{n_{uj}{v}_{uj}+n_{lj}{v}_{lj}}{2}$$

(13)

$$v_{sj}=\frac{-n_{uj}{v}_{uj}+n_{lj}{v}_{lj}}{2}$$

(14)

By applying the Park transformation on Formula (10), the output current dynamic can be described in the dq-frame as

$$\frac{L_a}{2}\frac{d}{dt}\left[\begin{array}{c}{i}_{d+}\\ i_{q+}\end{array}\right]=\left[\begin{array}{c}{v}_{sd+}\\ v_{sq+}\end{array}\right]-\left[\begin{array}{c}{v}_{d+}\\ v_{q+}\end{array}\right]+\frac{L_a}{2}\left[\begin{array}{cc}0& {\omega }_1\\ -{\omega }_1& 0\end{array}\right]\left[\begin{array}{c}{i}_{d+}\\ i_{q+}\end{array}\right]$$

(15)

$$\frac{L_a}{2}\frac{d}{dt}\left[\begin{array}{c}{i}_{d-}\\ i_{q-}\end{array}\right]=\left[\begin{array}{c}{v}_{sd-}\\ v_{sq-}\end{array}\right]-\left[\begin{array}{c}{v}_{d-}\\ v_{q-}\end{array}\right]+\frac{L_a}{2}\left[\begin{array}{cc}0& -{\omega }_1\\ {\omega }_1& 0\end{array}\right]\left[\begin{array}{c}{i}_{d-}\\ i_{q-}\end{array}\right]$$

(16)

where $v_{sd+}$, $v_{sq+}$, $v_{sd-}$, and $v_{sq-}$ are the positive- and negative-sequence components of $v_{sj}$ in the dq-frame.

According to Equations (15) and (16), a typical output control loop can be constructed for the MMC as shown in Figure 4. A positive-sequence control and a negative-sequence control using PI regulators are adopted, where K_op and K_i are the gains. The positive- and negative-sequence components of the grid voltage can be extracted with methods in [31] and used as the input of a grid current reference generator, which is applied to provide the active and reactive current references ($i_{d+}^{\ast }$, $i_{q+}^{\ast }$, $i_{d-}^{\ast }$, $i_{q-}^{\ast }$) for the controller.

According to Equation (14), a circulating current suppression control (CCSC) of the MMC can be designed as shown in Figure 5 [14]. A PR controller is applied to eliminate the dominant double-line frequency ripple in the circulating current, where K_cp and K_r represent its gains. The DC reference of the circulating current control will be given by a circulating current reference generator.

3.2. Grid Fault SM Voltage Estimation

Based on the dynamics of the SM voltage shown in Equation (11), the SM voltage stress of each phase-leg is governed by the arm currents (i_uj and i_lj) and its insertion indexes (n_uj and n_lj). According to Equation (12), the arm currents are composed of the circulating current and phase output current.

As shown in Figure 4, the state functions of the positive current sequence can be represented as

$$\dot{\mathbf{X}}=\mathbf{AX}+\mathbf{BU}$$

(17)

where

$$\dot{\mathbf{X}}={\left[\begin{array}{cccc}{\dot{i}}_{d+}& {\dot{i}}_{q+}& {\dot{\alpha }}_{d+}& {\dot{\alpha }}_{q+}\end{array}\right]}^{\mathrm{T}}$$

$$\mathbf{A}=\left[\begin{array}{cccc}-\frac{2K_{op}}{L_a}& {\omega }_1& K_i& 0\\ -{\omega }_1& -\frac{2K_{op}}{L_a}& 0& K_i\\ -1& 0& 0& 0\\ 0& -1& 0& 0\end{array}\right]$$

$$\mathbf{X}={\left[\begin{array}{cccc}{i}_{d+}& i_{q+}& {\alpha }_{d+}& {\alpha }_{q+}\end{array}\right]}^{\mathrm{T}}$$

$$\mathbf{B}=\left[\begin{array}{cccc}{K}_{op}& 0& -1& 0\\ 0& K_{op}& 0& -1\\ 1& 0& 0& 0\\ 0& 1& 0& 0\end{array}\right]$$

$$\mathbf{U}={\left[\begin{array}{cccc}{i}_{d+}^{\ast }& i_{q+}^{\ast }& v_{d+}& v_{q+}\end{array}\right]}^{\mathrm{T}}$$

in which ${\alpha }_{d+}=i_{d+}^{\ast }-i_d$ and ${\alpha }_{q+}=i_{q+}^{\ast }-i_q$.

According to Formula (17), the transfer functions of the positive-sequence current can be written as $\mathbf{X}\left(s\right)=\mathbf{CU}$ with matrix $\mathbf{C}={(s\mathbf{I}-\mathbf{A})}^{-1}\mathbf{B}$. Based on this method, the transfer functions of output current control can be represented as

$$\left\{\begin{array}{c}{i}_{d+}\left(s\right)=H_1\left(s\right)i_{d+}^{\ast }+H_2\left(s\right)i_{q+}^{\ast }-H_3\left(s\right)v_{d+}-H_4\left(s\right)v_{q+}\hfill \\ i_{q+}\left(s\right)=-H_2\left(s\right)i_{d+}^{\ast }+H_1\left(s\right)i_{q+}^{\ast }+H_4\left(s\right)v_{d+}-H_3\left(s\right)v_{q+}\hfill \\ i_{d-}\left(s\right)=H_1\left(s\right)i_{d-}^{\ast }-H_2\left(s\right)i_{q-}^{\ast }-H_3\left(s\right)v_{d-}+H_4\left(s\right)v_{q-}\hfill \\ i_{q-}\left(s\right)=H_2\left(s\right)i_{d-}^{\ast }+H_1\left(s\right)i_{q-}^{\ast }-H_4\left(s\right)v_{d-}-H_3\left(s\right)v_{q-}\hfill \end{array}\right.$$

(18)

in which $H_1\left(s\right)$, $H_2\left(s\right)$, $H_3\left(s\right)$, $H_4\left(s\right)$ are given in Formula (19), respectively:

$$\left\{\begin{array}{c}{H}_1\left(s\right)=\frac{K_{op}{L}_a^2{s}^3+(2K_{op}^2{L}_a+K_i{L}_a^2)s^2+(K_{op}{K}_i{L}_a^2+2K_{op}{K}_i{L}_a)s+K_i^2{L}_a^2}{L_a^2{s}^4+4K_{op}{L}_a{s}^3+(4K_{op}^2+L_a^2{\omega }_1^2+2K_i{L}_a^2)s^2+4K_{op}{K}_i{L}_{a}s+K_i^2{L}_a^2}\hfill \\ H_2\left(s\right)=\frac{K_{op}{\omega }_1{L}_a^2{s}^2+K_i{\omega }_1{L}_a^{2}s}{L_a^2{s}^4+4K_{op}{L}_a{s}^3+(4K_{op}^2+L_a^2{\omega }_1^2+2K_i{L}_a^2)s^2+4K_{op}{K}_i{L}_{a}s+K_i^2{L}_a^2}\hfill \\ H_3\left(s\right)=\frac{L_a^2{s}^3+2K_{op}{L}_a{s}^2+K_i{L}_a^{2}s}{L_a^2{s}^4+4K_{op}{L}_a{s}^3+(4K_{op}^2+L_a^2{\omega }_1^2+2K_i{L}_a^2)s^2+4K_{op}{K}_i{L}_{a}s+K_i^2{L}_a^2}\hfill \\ H_4\left(s\right)=\frac{L_a^2{\omega }_1{s}^2}{L_a^2{s}^4+4K_{op}{L}_a{s}^3+(4K_{op}^2+L_a^2{\omega }_1^2+2K_i{L}_a^2)s^2+4K_{op}{K}_i{L}_{a}s+K_i^2{L}_a^2}\hfill \end{array}\right.$$

(19)

Meanwhile, the dynamic response of the circulating current can be derived according to Figure 5:

$$i_{cj}\left(s\right)=\frac{K_{cp}{s}^2+K_{r}s+4K_{cp}{\omega }_1^2}{L_a{s}^3+K_{cp}{s}^2+(K_r+4L_a{\omega }_1^2)s+4K_{cp}}{i}_{cj}^{\ast }$$

(20)

$$v_{cj}\left(s\right)=\frac{K_{cp}{L}_a{s}^3+K_r{L}_a{s}^2+4K_{cp}{L}_a{\omega }_1^{2}s}{L_a{s}^3+K_{cp}{s}^2+(K_r+4L_a{\omega }_1^2)s+4K_{cp}}{i}_{cj}^{\ast }$$

(21)

To describe the system dynamics during grid faults,

Table 1. Quiescent operation point of the MMC.

Normal Operation Point	Grid Fault Operation Point
$v_{d+\_normal}$ = $V_{d+}$	$v_{d+\_fault}$ = $V_{d+}^{\prime }$
$v_{q+\_normal}$ = 0	$v_{q+\_fault}$ = $V_{q+}^{\prime }$
$v_{d-\_normal}$ = 0	$v_{d-\_fault}$ = $V_{d-}^{\prime }$
$v_{q-\_normal}$ = 0	$v_{q-\_fault}$ = $V_{q-}^{\prime }$
$i_{d+\_normal}^{\ast }$ = $I_{d+}$	$i_{d+\_fault}^{\ast }$ = $I_{d+}^{\prime }$
$i_{q+\_normal}^{\ast }$ = 0	$i_{q+\_fault}^{\ast }$ = $I_{q+}^{\prime }$
$i_{d-\_normal}^{\ast }$ = 0	$i_{d-\_fault}^{\ast }$ = $I_{d-}^{\prime }$
$i_{q-\_normal}^{\ast }$ = 0	$i_{q-\_fault}^{\ast }$ = $I_{q-}^{\prime }$
$i_{cj\_normal}^{\ast }$ = $I_{cj}$	$i_{cj\_fault}^{\ast }$ = $I_{cj}^{\prime }$

indicates the operation point of the MMC system during normal state and grid fault conditions. By applying the reverse Laplace transformation on Equation (18), the time-domain transient response of the system in the dq-frame can be obtained as

$$\left\{\begin{array}{c}{i}_{d+\_tran}\left(t\right)=I_{d+}+{\mathcal{L}}^{-1}\left[i_{d+}\left(s\right)\right]\hfill \\ i_{q+\_tran}\left(t\right)={\mathcal{L}}^{-1}\left[i_{q+}\left(s\right)\right]\hfill \\ i_{d-\_tran}\left(t\right)={\mathcal{L}}^{-1}\left[i_{d-}\left(s\right)\right]\hfill \\ i_{q-\_tran}\left(t\right)={\mathcal{L}}^{-1}\left[i_{q-}\left(s\right)\right]\hfill \\ i_{cj\_tran}\left(t\right)={\mathcal{L}}^{-1}\left[i_{cj}\left(s\right)\right]\hfill \\ v_{cj\_tran}\left(t\right)={\mathcal{L}}^{-1}\left[v_{cj}\left(s\right)\right]\hfill \end{array}\right.$$

(22)

where the input of the system can be regarded as a series of step signals in the s-domain

$$\left\{\begin{array}{c}{i}_{d+}^{\ast }\left(s\right)=\frac{I_{d+}^{\prime }-I_{d+}}{s}\hfill \\ i_{q+}^{\ast }\left(s\right)=\frac{I_{q+}^{\prime }}{s}\hfill \\ i_{d-}^{\ast }\left(s\right)=\frac{I_{d-}^{\prime }}{s}\hfill \\ i_{q-}^{\ast }\left(s\right)=\frac{I_{q-}^{\prime }}{s}\hfill \\ v_{d+}\left(s\right)=\frac{V_{d+}^{\prime }-V_{d+}}{s}\hfill \\ v_{q+}\left(s\right)=\frac{-V_{q+}^{\prime }}{s}\hfill \\ v_{d-}\left(s\right)=\frac{-V_{d-}^{\prime }}{s}\hfill \\ v_{q-}\left(s\right)=\frac{-V_{q-}^{\prime }}{s}\hfill \\ i_{cj}^{\ast }\left(s\right)=\frac{I_{cj}^{\prime }-I_{cj}}{s}\hfill \end{array}\right.$$

(23)

According to [32], the dynamics of the output current can be calculated as

$$\begin{array}{cc}{i}_{j\_tran}\left(t\right)\hfill & =i_{d+\_tran}cos({\omega }_{1}t-{\phi }_j)+i_{q+\_tran}sin({\omega }_{1}t-{\phi }_j)\hfill \\ \hfill & +i_{d-\_tran}cos({\omega }_{1}t+{\phi }_j)+i_{q-\_tran}sin({\omega }_{1}t+{\phi }_j)\hfill \end{array}$$

(24)

By applying the direct modulation [33], the insertion indexes of the upper and lower arms can be calculated as

$$n_{uj\_tran}=\frac{v_{cj\_tran}-v_{j\_fault}}{V_{dc}}$$

(25)

$$n_{lj\_tran}=\frac{v_{cj\_tran}+v_{j\_fault}}{V_{dc}}$$

(26)

According to Equation (11), the dynamic response of the total SM voltage can be obtained as

$$v_{uj\_tran}=v_{uj}\left(t_0\right)+\frac{1}{C_{eq}}\int (i_{cj\_tran}+\frac{1}{2}{i}_{j\_trans})n_{uj\_tran}$$

(27)

$$v_{lj\_tran}=v_{lj}\left(t_0\right)+\frac{1}{C_{eq}}\int (i_{cj\_tran}-\frac{1}{2}{i}_{j\_trans})n_{lj\_tran}$$

(28)

where $t_0$ is the initial time of the grid fault. As the voltage across each SM in the same arm is assumed to be balanced, the voltage stress on each SM can be given as

$$v_{smuj\_tran}\left(t\right)=\frac{v_{uj\_tran}\left(t\right)}{N}$$

(29)

Thus, the maximum SM voltage stresses during the grid fault transient can be predicted as

$$V_{tmax}=\max [v_{smuj\_tran}\left(t\right),v_{smlj\_tran}\left(t\right)]$$

(30)

4. Design Consideration of SM Capacitors

4.1. Energy Storage Requirement

According to [17], the energy stored in each arm of the MMC must be larger than the required energy by the grid. In steady-state, the required inserted voltage for the upper arm can be expressed as

$$v_{uj\_req}=\frac{V_{dc}}{2}-v_j$$

(31)

By substituting Equation (31) into (5), the energy requirement of SM capacitor can be given as

$$e_{uj}\ge \frac{1}{2N}{C}_{sm}{(\frac{V_{dc}}{2}-v_j)}^2$$

(32)

By taking Equation (3) into (32), the required SM capacitance for each phase-leg can be obtained as

$$C_{sm\_enj}\ge max\left\{\frac{2N{V}_{dc}{\widehat{I}}_j}{16{\omega }_1[{(\frac{V_{dc}}{2}-v_j)}^2-V_{dc}^2]}\mathbf{F}\right\}$$

(33)

4.2. SM Ripple Voltage Requirement

To ensure the stability and efficiency of the MMC, the SM voltage ripple must be kept in a safe range during steady-state operation. Defining the allowable peak-to-peak voltage ripple as $V_{rip}$, the following condition should be satisfied:

$$V_{ssmax}-V_{ssmin}\le V_{rip}$$

(34)

Solving Equation (34) yields the minimum capacitance requirement as

$$C_{sm\_ripj}\ge \frac{V_{dc}{\widehat{I}}_j({\mathbf{F}}_{max}-{\mathbf{F}}_{min})}{8N{\omega }_1{V}_{rip}^2}$$

(35)

4.3. Transient SM Voltage Constraint

For industrial MMC projects, a series of protection strategies are embedded in the control system to avoid switching devices (e.g., IGBTs) getting over-stressed. Once the operating SM voltage reaches a preset threshold $V_{th}$, the SM will be bypassed by the control blocks [34]. If a large amount of SMs get over-charged at the same time, a system-level shutdown may be triggered. Thus, the transient SM voltage $V_{tmax}$ must be constrained under the threshold $V_{th}$, which can be written as $V_{tmax}<V_{th}$.

By substituting Equations (27) and (28) into the equation, it can be obtained as

$$C_{sm\_tj}\ge \frac{max[\int (i_{cj\_tran}+\frac{1}{2}{i}_{j\_trans})n_{uj\_tran}]}{V_{th}-max\left[\frac{v_{uj}\left(t_0\right)}{N}\right]}$$

(36)

$$C_{sm\_tj}\ge \frac{max[\int (i_{cj\_tran}-\frac{1}{2}{i}_{j\_trans})n_{lj\_tran}]}{V_{th}-max\left[\frac{v_{lj}\left(t_0\right)}{N}\right]}$$

(37)

It should be noted that the maximum transient SM voltage for upper and lower arms can be different during grid faults. The selected SM capacitance should fulfill the Equations (49) and (50) in the meantime.

4.4. ESR, Thermal Resistance, and Lifetime Assessment

To ensure a long-term reliable operations of the MMC, the thermal stresses of SM capacitors must be evaluated. According to [35], a simple lifetime model of SM capacitors can be given as

$$L_{life}=L_0\times {\left(\frac{V_{dc}}{N{V}_{rated}}\right)}^{-\delta }\times 2^{\frac{T_0-T_h}{10}}$$

(38)

where $L_0$ is the lifetime of the capacitor under rated voltage $V_{rated}$ and testing temperature $T_0$; the exponent $\delta$ is normally selected from 7 to 9.4 for metallized polypropylene film (MPPF) capacitor; $T_h$ is the operating hot-spot temperature of the capacitors.

In order to study the thermal behavior of the SM capacitors, a lumped thermal model of film capacitors are given in Figure 6 [36], where the steady-state hot-spot temperature of capacitors can be expressed as

$$T_h=R_{th}{P}_{loss}+T_a$$

(39)

The thermal resistance of the capacitor R_th relates to the material of the capacitor. T_a is the ambient temperature, P_loss is the power losses of the SM capacitor.

By neglecting the harmonics on the circulating current, the SM capacitor charging current can be decomposed by a fundamental line frequency component and a double-line frequency component, which can be expressed as [37]

$$i_{smj}={\beta }_{\omega 1}{\widehat{I}}_s+{\beta }_{\omega 2}{\widehat{I}}_s$$

(40)

$${\beta }_{{\omega }_1}=\frac{1}{8}[2cos({\omega }_{1}t-{\phi }_j)-m^{2}cos\left({\omega }_{1}t\right)cos\left({\phi }_j\right)]$$

(41)

$${\beta }_{{\omega }_2}=-\frac{m}{8}[cos(2{\omega }_{1}t-{\phi }_j)]$$

(42)

With different modulation index and phase angle, the RMS value of ${\beta }_{{\omega }_1}$ is shown in Figure 7, while the RMS value of ${\beta }_{{\omega }_2}$ equals $m/\left(8\sqrt{2}\right)$. Thus, the power losses for SM capacitors can be calculated as

$$P_{loss}=(R_{esr\_\omega 1}\times {\beta }_{\omega 1\_rms}^2+R_{esr\_\omega 2}\times {\beta }_{\omega 2\_rms}^2){\widehat{I}}_s^2$$

(43)

where $R_{esr\_\omega 1}$ is the equivalent-series-resistance (ESR) of the SM capacitor under fundamental line frequency, $R_{esr\_\omega 2}$ is the ESR under double line frequency.

5. SM Capacitor Selection

5.1. SM Capacitance Selection

According to Equations (33), and (35)–(37), the design boundary of the SM capacitance can be obtained. Considering the capacitance losses caused by aging of capacitors [38], an extra design margin must be guaranteed. Thus, the SM capacitance can be chosen as

$$s{C}_{sm}=\eta \times max(C_{sm\_enj},C_{sm\_ripj},C_{sm\_tj})$$

(44)

where $\eta$ is the redundancy factor of SM capacitance selection. Normally, $\eta$ is chosen from 1.2 to 2.

5.2. Rated Voltage Selection

According to characteristics of film capacitors [39], the peak value of the operating voltage must not exceed their rated DC voltage. Thus, the rated voltage of the SM capacitor can be chosen as

$$V_{rated}\ge max(V_{ssmax},V_{tmax})$$

(45)

where the maximum voltage stress on SM capacitors can be calculated according to Equations (10) and (38)–(42).

5.3. Design Flowchart

Based on the analysis above, a design procedure flowchart is shown in Figure 8. First, some basic parameters are required, which includes the DC-link voltage ($V_{dc}$), number of SMs in each arm (N), arm inductance ($L_a$), AC-side fundamental angular frequency (${\omega }_1$), gain of the MMC control loops ($K_{op},K_{cp},K_i$, and $K_r$ ) allowable peak-to-peak SM voltage ripple ($V_{rip}$), maximum SM voltage threshold ($V_{th}$), expected SM capacitor lifetime ($L_{exp}$), and system operating points in normal and grid fault conditions. Then, the minimum SM capacitance that satisfies the energy storage, voltage ripple, and transient SM voltage requirements can be calculated using the Equations (33) and (35)–(37). After that, the SM capacitance $C_{sm}$ can be decided by adding a proper redundancy to the highest value among $C_{sm\_enj}$, $C_{sm\_ripj}$, $C_{sm\_tj}$. Based on the selected capacitance, the rated voltage of SM capacitor $V_{rated}$ can be obtained using Formula (45). Since the capacitance and rated voltage have been decided, a certain type of capacitor product can be selected in the market. In the end, the lifetime of the selected capacitor product needs to be checked using Equations (38) and (43). It should be noted that the MMC system may encounter different fault conditions. Thus, this design process may be conducted multiple times based on different grid fault operating points. Through comparison, the maximum calculation value of $C_{sm}$ and $V_{rated}$ can be chosen as the final result.

6. Case Study

6.1. Design Example

To verify the correctness of the proposed method, a down-scale three-phase MMC design case is given. Key system parameters and design requirement were as shown in

Table 2. System parameters and design requirement.

System Parameters
SM number in each arm (N)	3
Arm Inductance (La)	5 mH
Grid frequency	50 Hz
Switching frequency	8 kHz
DC-bus voltage	120 V
Kop	10
Ki	60
Kcp	5
Kr	35
Design Requirement
Peak-to-peak SM voltage ripple (Vrip)	4 V
Maximum SM voltage threshold (Vth)	50 V
Capacitance redundancy factor ($\eta$)	1.2

. The maximum SM voltage ripple $V_{rip}$ should be limited within 10% of the SM DC-bias, while the allowable SM voltage $V_{th}$ is selected 25% higher than the SM DC-bias. Two common grid fault conditions are selected for SM capacitor sizing: single-line-to-ground fault and three-phase short-circuit fault. Both positive- and negative-sequence currents will be injected into the grid when the grid fault is detected. The reactive current injection strategy follows the German grid code, as shown in [40]. Thus, the MMC operating points during the normal state and grid fault conditions are shown in

Table 3. Possible operation points of the MMC.

Normal Operation Point
Grid voltage	$V_{d+}$ = 50 V
Grid current injection	$I_{d+}$ = 5 A; $I_{q+}$ = 0
Circulating current reference	$I_{cj}$ = 0.417 A
Single-Line-to-Ground Condition
Grid voltage	$V_{d+}^{\prime }$ = 33.5 V
	$V_{d-}^{\prime }$ = 16.5 V
Grid current injection	$I_{d+}^{\prime }$ = 1.67 A
	$I_{q+}^{\prime }$ = 2.875 A
	$I_{d-}^{\prime }$ = 0; $I_{q-}^{\prime }$ = −3.5 A
Three-Phase Short-Circuit Condition
Grid voltage	$V_{d+}^{\prime }$ = 0; $V_{d-}^{\prime }$ = 0
Grid current injection	$I_{d+}^{\prime }$ = 0; $I_{q+}^{\prime }$ = 4.5 A
	$I_{d-}^{\prime }$ = 0; $I_{q-}^{\prime }$ = 0

.

By putting the design parameters above into Formulas (33) and (35), the SM capacitance demand for energy storage requirement and ripple voltage requirement can be calculated as: $C_{sm\_enj}=250.8\mathsf{\mu }$F, $C_{sm\_ripj}=857.7\mathsf{\mu }$F. According to Equations (38)–(39), the relationship between SM capacitance $C_{sm}$ and the maximum transient SM voltage stress $V_{tmax}$ can be calculated and shown in Figure 9. To keep the SM voltage in a safety range during both grid fault conditions, $C_{sm\_tj}$ is selected as 1.14 mF. With a 20% extra design margin ($\eta =1.2$), the final SM capacitor is chosen as 1.36 mF, formed by two 680 $\mathsf{\mu }$F capacitors connecting in parallel. By setting the rated voltage of the SM capacitor at 100 V, the information of the selected product is given in

Table 4. Key parameters of the selected capacitor product.

Part Number	UBY2A681MHL
Capacitance	680 $\mathsf{\mu }$F
ESR	28 m$\Omega$ at 50 Hz; 14 m$\Omega$ at 100 Hz
Thermal resistance	1.5 ${}^{°}$C/W
Reference lifetime	3000 h at 125 ${}^{°}$C, 20–50 V

. By taking the ESR value into Formula (43), the power losses of the SM capacitor is around 0.1 W, which is relatively small. Thus, the hot-spot temperature of the SM capacitor is considered as equal to the ambient temperature in this case study. Assuming the operating ambient temperature is 60 ${}^{°}$C, the SM capacitor lifetime can be estimated using Equation (51) as $2.7\times {10}^5$ h.

6.2. Experimental Verification

By using the selected components given in Table 4, an experiment platform has been assembled, the structure of which is shown in Figure 10. The platform is formed with three phase-legs. The DC-side voltage of the MMC is provided by a constant DC source. A dSPACE system is used as the controller of the MMC, while an auxiliary DC supply is used to provide power for the sensors and gate drivers in the system. The AC side of the platform is connected to a grid simulator, which is used to generate the grid fault signal. The system operation waveforms during grid fault conditions are shown in Figure 11, where the system state during single-line-to-ground condition and three-phase short-circuit condition is shown in Figure 11a,b, respectively. Due to the symmetrical characteristic, only the SM voltage of upper arm is given.

It can be seen that the circulating current through each phase-leg is well-suppressed when the system operates in steady-state. During normal operation, the peak-to-peak SM voltage ripple is 3.5 V, which is well constrained within the design limit. During the transient state of both grid fault conditions, an obvious voltage over-shoot appears on each SM capacitor, which is caused by the dynamic response of the control system [30]. In Figure 11a, the maximum SM voltage in three phase-legs is 48.8 V, which is 1.5 V higher than the model-estimated value shown in Figure 9a. For three-phase short circuit condition, the maximum SM voltage is close to the expectation, with only a 1 V difference. These estimation errors are caused by the signal coupling within the MMC control system. However, all SM voltage is limited under 40 V, which proves the effectiveness of the proposed SM capacitor selection method.

7. Conclusions

A straightforward practical SM capacitor sizing method is proposed in this paper for MMC systems. Compared with the existing solutions, the proposed method is more applicable for a grid-connected MMC project, especially for cases requiring grid-fault-ride-through ability, such as static synchronous compensator (STATCOM) and the MMC-based HVDC system. A reliable path is given to select the capacitance, rated voltage, ESR, thermal resistance, and rated lifetime of the SM capacitor, considering the system requirement during normal operation state and grid-fault-ride-through conditions. Through analyzing the control loop, a quantitative estimation method of the maximum voltage stresses was given, which provides an insight into the impact of different control schemes on the SM capacitor design and improves the reliability of the MMC operating under grid fault conditions. A down-scale MMC experimental platform is designed and assembled. By comparing the experiment results with the design requirement, all design parameters are well achieved, which proves the effectiveness of the proposed design method.