Impacts of SiC-MOSFET Gate Oxide Degradation on Three-Phase Voltage and Current Source Inverters

Abstract

In this paper, the performance variations of SiC MOSFET-based voltage and current source inverters under gate oxide degradation are studied. It is confirmed that the turn-on and turn-off delays of SiC MOSFETs change significantly by high electric field stress, which accelerates the gate oxide degradation. Variations in the turn-on and turn-off delays of switching devices extend or reduce the duty error of voltage source inverters and current source inverters. The performance variations of the voltage and current source inverter due to the duty error changes caused by the gate oxide degradation are analyzed through simulations. As a result, the gate oxide degradation worsens the performance of the voltage source inverter. Furthermore, the negative gate oxide degradation, which lowers the threshold voltage, decreases the performance of the current source inverter.

1. Introduction

Along with gallium nitride (GaN) field effect transistor (FET), silicon carbide (SiC) metal-oxide-semiconductor field (MOSFET), a wide bandgap (WBG) device, is attracting attention as a next-generation power switching device due to its high efficiency and power density [1,2]. In particular, SiC MOSFET is increasingly used in systems close to human life, such as electric vehicles [3]. As a result, the reliability of SiC MOSFET is becoming more important.

A gate oxide degradation is a major aging phenomenon that affects the reliability of SiC MOSFET along with a package degradation [4]. The package degradation is caused by thermomechanical stress caused by temperature change [5]. If the package degradation continues, phenomena, such as bond wire crack and lift-off, occur, leading to a switching device failure [6,7]. Meanwhile, SiC MOSFET has a thin gate oxide layer, so electrons can be injected into the oxide layer by the Fowler–Nordheim tunneling current. Moreover, there are more interface trapped charges on the SiC/SiO₂ interface than Si MOSFET [8,9]. In particular, the interface trapped charge reduces the effective channel-carrier mobility and changes the threshold voltage (V_th). The reduced effective channel-carrier mobility eventually increases the on-resistance (R_on) of the switch. The shift direction of the V_th is determined by the sum of the oxide trapped charge and the interface trapped charge. These charges are changed more significantly by the gate oxide degradation. An increase in V_th causes an increase in conduction losses. Moreover, a decrease in V_th increases the risk of the switch being turned on undesirably [10,11]. If the gate oxide degradation continues, the gate insulation is eventually destroyed, and the control ability of the gate to switch is lost [12].

The gate oxide degradation is accelerated under high electric field (HEF) stress or high-temperature stress [13]. HEF stress is divided into positive HEF (PHEF) stress applying a positive voltage to the gate, and negative HEF (NHEF) stress using a negative voltage. Characteristic changes during the gate oxide degradation of SiC MOSFETs have been studied through muchresearch [8,10,13,14,15,16,17], and

Table 1. Summary of previous research about characteristics of SIC MOSFETs under gate oxide degradation.

Reference	Types of HEF		Stationary Properties				Transient Properties
	PHEF	NHEF	Vth	Ron	Cgs, Cgd	Vsd	Vm	Tm	Tgc	Tdon	Tdoff
[8]	O	O	O	O	O	X	X	X	X	X	X
[10]	O	O	O	X	X	O	X	X	X	X	X
[13]	O	X	O	X	X	X	O	X	X	O	X
[14]	O	O	O	X	X	X	X	X	X	X	X
[15]	O	O	O	X	X	X	X	X	X	X	X
[16]	O	O	O	X	X	X	X	X	O	X	X
[17]	O	X	O	X	X	X	O	O	X	X	X

summarizes the previous research about the characteristics of SiC MOSFETs under gate oxide degradation. In Table 1, characteristics covered by the study were marked with an O, and properties not investigated by the analysis were marked with an X. Furthermore, the characteristics measured when the switching state is fixed are defined as stationary properties, and the properties measured when the switching state changes are defined as transient properties. The stationary properties are V_th, R_on, gate–drain capacitance (C_gd), gate–source capacitance (C_gs), and body diode forward voltage (V_sd). Moreover, the transient properties are Miller plateau voltage (V_m), Miller plateau time (T_m), gate charge time (T_gc), turn-on delay (T_don), and turn-off delay (T_doff).

As shown in Table 1, previous studies dealt with the SiC MOSFET’s stationary properties under gate oxide degradation. However, research about transient characteristics of SiC MOSFET has not been conducted much. Especially, except for T_don in [13], no studies on T_don and T_doff under gate oxide degradation were conducted in previous studies. T_don and T_doff can impact the performance of voltage and current source converters. The voltage source converter has a dead time to prevent a short circuit accident when one leg’s switches are turned on simultaneously [18]. The dead time causes a duty error in the voltage vector. In addition to the dead time, T_don and T_doff introduce duty errors. These duty errors change the output quality of the voltage source converter. Furthermore, an overlap time is required in the current source converter to prevent an overvoltage of the DC link inductor from occurring when all upper or lower switches are turned off simultaneously [19]. Like the voltage source converter, the overlap time, T_don, and T_doff generate the duty errors in the current vector, resulting in changes in the output quality of the current source converter. Therefore, studies on changes in T_don and T_doff under gate oxide degradation are necessary.

In this paper, the changes of T_don and T_doff of SiC MOSFET in the gate oxide degradation are examined. In addition, the effects of T_don and T_doff variations caused by the gate oxide degradation on the performance of voltage and current source inverters are studied.

The structure of this paper is as follows. Section 1 is the introduction. Section 2 analyzes the effects of V_th on R_on, T_don, and T_doff. Section 3 describes HEF stress to accelerate the gate oxide degradation. Section 4 compares V_th and R_on changes of SiC MOSFET under HEF stress with those of Si-based devices. Section 5 compares the changes in T_don and T_doff of SiC MOSFET under HEF stress with those of Si-based devices. In Section 6, the performance variations of voltage and current source inverters according to the duty error changes due to the gate oxide degradation are examined by the simulation. Section 7 is the conclusion.

2. Effects of Threshold Voltage Variation on On-Resistance, Turn-On Delay and Turn-Off Delay

2.1. Gate Oxide Degradation

Gate oxide degradation is aging occurring in the gate oxide layer. Furthermore, it is one of the major degradations of MOSFETs, like package degradation. As the gate oxide degradation progresses, there is a change in V_th, and this change can be explained by the oxide trapped charge and the interface trapped charge in the gate oxide layer. Figure 1 is a structure of the MOSFET and the gate oxide layer.

In Figure 1, Q_ot denotes the oxide trapped charge, and Q_it means the interface trapped charge. By the gate oxide degradation, Q_ot is generated inside the oxide layer, and Q_it is generated on the surface of the oxide layer. V_th can be expressed as (1) using Q_ot and Q_it [20]:

$$V_{th}=V_{th0}+\frac{Q_{it}-Q_{ot}}{C_{ox}},Q_{it}=q{N}_{it}, Q_{ot}=q{N}_{ot}$$

(1)

In (1), V_th0 means V_th in a fresh condition where the gate oxide degradation does not proceed. C_ox represents the gate oxide capacitance per unit area. Furthermore, q stands for the electric charge. Moreover, N_it and N_ot mean the interface trap density and the oxide trap density, respectively. When the gate oxide degradation proceeds, Q_it and Q_ot are generated. V_th increases or decreases depending on which charge is more generated relatively. As seen from (1), when Q_it occurs relatively significantly, V_th rises. On the other hand, when Q_ot is relatively large, V_th decreases. The gate oxide degradation is accelerated by HEF stress. In general, in PHEF stress where a positive voltage is applied to the gate voltage, Q_it is generated significantly to increase V_th. Meanwhile, in NHEF stress where a negative voltage is applied to the gate voltage, Q_ot is generated relatively significantly, and V_th decreases.

2.2. On-Resistance Variation Caused by Threshold Voltage

R_on can be subdivided into several types of resistances as follows (2) [8]:

$$R_{on}=R_{ch}+R_A+R_{JFET}+R_D+R_{sub}$$

(2)

In (2), R_ch is the channel resistance, R_A is the accumulation resistance, R_JFET is the JFET region resistance, R_d is the drift region resistance, and R_sub is the substrate resistance. In the case of SiC MOSFETs, among the five resistance types, R_ch is the most dominant [8]. R_ch can be expressed as (3) [8]:

$$R_{ch}\approx \frac{L_{ch}}{W_{ch}\mu C_{ox}{V}_{over}}, V_{over}=V_{gs}-V_{th}$$

(3)

In (3), L_ch means the channel length, and W_ch represents the channel width. In addition, μ and V_over represent the channel mobility and the overdrive voltage, respectively. V_over is expressed as the difference between the gate–source voltage (V_gs) and V_th. As seen from (3), the variation of V_over changes R_ch. Therefore, when V_th changes, R_ch also changes. When V_th increases, V_over decreases, and R_ch increases. When V_th decreases, V_over increases, and R_ch decreases. As a result, R_on increases when V_th increases, and R_on decreases when V_th decreases.

2.3. Turn-On Delay Variation Caused by Threshhold Voltage

A definition of T_don is the time from when V_gs starts to rise to when the drain–source current (I_ds) starts to increase [21]. V_th is related to T_don because V_th is the voltage at which I_ds starts flowing through the switch. Figure 2 shows V_gs and I_ds waveforms when the switch is turned on.

In Figure 2, t₀ means the time when V_gs starts to increase to turn on the switch. In addition, t_thf indicates the time when I_ds in the fresh condition begin to rise. t_thn and t_thp denote a time at which I_ds start to grow when V_th is negatively shifted and positively shifted, respectively. V_th and I_ds in the fresh condition are expressed as V_thf and I_dsf, respectively. Furthermore, V_th and I_ds in the negative V_th shift are described as V_thn and I_dsn, respectively. Moreover, V_th and I_ds in the positive V_th shift are denoted as V_thp and I_dsp, respectively. As shown in Figure 2, I_ds starts to flow when V_gs becomes greater than V_th. T_don of the fresh state, the negative V_th shift, and the positive V_th shift can be expressed by (4), respectively:

$$T_{donf}=t_{thf}-t_o,T_{donn}=t_{thn}-t_o,T_{donp}=t_{thp}-t_o$$

(4)

T_donf, T_donn, and T_donp in (4) mean T_don in fresh condition, negative V_th shift, and positive V_th shift, respectively. As shown in Figure 2, comparisons of T_donf, T_donn, and T_donp are expressed as (5). Therefore, as V_th increases, T_don increases:

$$T_{donn}<T_{donf}<T_{donp}$$

(5)

2.4. Turn-Off Delay Caused by Threshold Voltage

A definition of T_doff is the time from when V_gs starts to decrease to when the drain–source voltage (V_ds) begins to grow [22]. The point at which V_ds increases in the off transition is when V_gs enters V_m [22]. Therefore, the change in T_doff can be explained by V_m. The relationship between V_m and V_th can be expressed by (6) [20]:

$$V_m=V_{th}+\sqrt{\frac{I_{ds}{L}_{ch}}{\mu C_{ox}{W}_{ch}}}$$

(6)

Partial differentiation of (6) with respect to N_ot and N_it gives the following (7) [20]:

$$\frac{\partial V_m}{\partial N_{it}}=\frac{\partial V_{th}}{\partial N_{it}}-\frac{{\mu }^{-1.5}}{2}\sqrt{\frac{I_{ds}{L}_{ch}}{C_{ox}{W}_{ch}}}\frac{\partial \mu }{\partial N_{it}}\approx \frac{\partial V_{th}}{\partial N_{it}}>0,$$

(7)

$$\frac{\partial V_m}{\partial N_{ot}}=\frac{\partial V_{th}}{\partial N_{ot}}-\frac{{\mu }^{-1.5}}{2}\sqrt{\frac{I_{ds}{L}_{ch}}{C_{ox}{W}_{ch}}}\frac{\partial \mu }{\partial N_{ot}}\approx \frac{\partial V_{th}}{\partial N_{ot}}<0.$$

From (7), it can be seen that an increase in V_th increases V_m and vice versa. Figure 3 shows the relationship between the change in V_m and T_doff.

In Figure 3, V_mp, V_mf, and V_mn mean V_m in positive V_th shift, fresh state, and negative V_th shift, respectively. In addition, t_mp, t_mf, and t_mn indicate a time when V_ds increases in positive V_th shift, fresh state, and negative V_th shift, respectively. t_m0 is the point at which V_gs begins to decrease to turn off the switch. Figure 3 indicates that the time at which V_ds increases is faster as V_m increases. Therefore, as V_m increases, T_doff decreases and vice versa. T_doff can be expressed as (8):

$$T_{dofff}=t_{mf}-t_{m0}, T_{doffp}=t_{mp}-t_{m0},T_{doffn}=t_{mn}-t_{m0}$$

(8)

In (8), T_doffp, T_dofff, and T_doffn denote T_doff in a positive V_th shift, fresh state, and negative V_th shift, respectively. The magnitudes of T_doffp, T_dofff, and T_doffn can be expressed as (9):

$$T_{doffp}<T_{dofff}<T_{doffn}$$

(9)

3. High Electric Field Stress

As shown in Figure 4, The HEF stress circuit was constructed to accelerate the gate oxide degradation. The fabricated circuit was configured to apply HEF stress to five devices simultaneously. The drain and source or collector and emitter of the switching device were shorted to be connected to the ground. A resistor of 200 Ω was inserted to alleviate the overshoot of the gate current when HEF stress was applied to the gate side [8]. HEF stress was applied for 3600 s at room temperature, and the switching devices were disconnected from the HEF stress circuit every 900 s to measure V_th, R_on, T_don, and T_doff of the switching devices. The gate bias value used for HEF stress should be the proper value for accelerating the gate oxide degradation and preventing the gate insulation destruction. For this, 50 V was used as the gate bias value in PHEF. In the case of NHEF, the gate bias value was set to −38 V. In this paper, characteristics, such as V_th, R_on, T_don, and T_doff, were compared by applying HEF stress under the same conditions to various Si-based devices as well as SiC MOSFET. The reason for this comparison is to confirm that SiC MOSFET is more susceptible to the gate oxide degradation compared to other Si-based devices. The Si-based devices used for comparison are Si IGBT, Si MOSFET, and Si IGBT with SiC diode. Information on the switching devices used for characteristic comparison is given in

Table 2. Datasheet values of switching devices used in this paper.

	Si IGBT		Si MOSFET		Si IGBT (Hybrid)		SiC MOSFET
	Values	Conditions	Values	Conditions	Values	Conditions	Values	Conditions
Part number	RGT60TS65DGC11		NTHL110N65S3F		IXGH30N60C3C1		SCT3080AL
Voltage	650 V		650 V		600 V		650 V
Current	30 A	Tc = 100 °C	19.5 A	Tc = 100 °C	30 A	Tc = 110 °C	21 A	Tc = 100 °C
Vth	6 V	Vce = 5 V Ice = 21 mA	3~5 V	Vgs = Vds Ids = 0.74 mA	3~5.5 V	Vge = Vce Ice = 0.25 mA	2.7~5.6 V	Vds = 10 V Ids = 5 mA
Ron	55 mΩ	Vge = 15 V, Ice = 30 A	98 mΩ	Vgs = 10 V, Ids = 15 A	130 mΩ	Vge = 15 V, Ice = 20 A	80 mΩ	Vgs = 18 V, Ids = 10 A, Tc = 25 °C
Tdon	29 ns	Vcc = 400 V Ice = 30 A Vge = 15 V RG = 10 Ω	29 ns	Vdd = 400 V Ids = 15 A Vgs = 10 V RG = 4.7 Ω	17 ns	Vcc = 300 V Ice = 20 A Vge = 15 V RG = 5 Ω	16 ns	Vdd = 300 V Ids = 10 A Vgs = 18 V/0 V RL = 30 Ω RG = 0 Ω
Tdoff	100 ns		61 ns		42 ns		27 ns

.

The maximum gate voltages of Si IGBT, Si MOSFET, Si IGBT with SiC diode, and SiC MOSFET, as seen from the datasheet, are −30/+30 V, −30/+30 V, −20/+20 V, and −4/+22 V, respectively. Therefore, it can be inferred from the datasheet that the SiC MOSFET is most vulnerable to the large gate voltage. This paper experimentally checks a low-rated gate voltage of SiC MOSFET by applying the same voltage stress to four types of switching devices and examines a change of electrical characteristics caused by the gate oxide degradation.

4. Investigation of Threshold Voltage and On-Resistance under High Electric Field Stress

This paper investigated V_th and R_on according to HEF stress. The V_th and R_on measurement circuits were configured as shown in Figure 5.

Figure 5 shows the case of Si MOSFET and SiC MOSFET. In the case of Si IGBT and Si IGBT with SiC diode, V_gs and I_ds correspond to gate–emitter voltage (V_ge) and collector–emitter current (I_ce), respectively. Figure 5a shows the V_th measurement circuit.A device under test (DUT) is connected to measure V_th, as shown in Figure 5a.Then, the magnitude of V_gs is gradually raised from 0 V until I_ds is 1 mA. V_gs, when I_ds becomes 1 mA, is V_th [14]. As shown in Table 2, I_ds (or I_ce) used to measure V_th is very small for Si MOSFET and Si IGBT with SiC diode. These values are very small to measure with an oscilloscope. Therefore, I_ds (or I_ce) of 1 mA that can be measured with a small error is selected, and V_th is measured with 1 mA for all four devices.

Figure 5b represents the R_on measurement circuit. To measure R_on, the voltage used to measure R_on in the datasheet of each device is applied to V_gs. That is, V_gs for R_on measurement is 15 V for Si IGBT, 10 V for Si MOSFET, 15 V for Si IGBT with SiC diode, and 18 V for SiC MOSFET. Then, I_ds and V_ds when the switch is fully on are measured with an oscilloscope to eliminate the effect of parasitic components. Meanwhile, R_on varies with respect to the junction temperature.In order to reduce the variation caused by the junction temperature change, the temperature rise of the switch is minimized by applying I_ds (about 2 A) which is much smaller than the rated value of the switch for a short time (about 40 ms). R_on is calculated using the measured V_ds and I_ds as (10):

R_on = V_ds/I_ds

(10)

The measured device characteristics are expressed as the rate of change concerning the initial value as (11):

Variation (%) = (P_aging − P_fresh)/P_fresh·100

(11)

In (11), P_aging represents a characteristic of the aging device. Moreover, P_fresh is a property of the fresh device. In Figure 6, the rules are established to distinguish the devices used in this paper.

Figure 6 shows the device naming rule used in this paper. A device’s name is divided into four parts. The first part indicates the type of switching device. As shown in Figure 6, a number is assigned to each switch type. The second part shows the measured device property. The third part is the type of HEF, and the last part means the device number. The example of Figure 6, 1-Vth-P-1, refers to the first switch among the five switches where PHEF stress is applied to the Si IGBT for the V_th measurement.

4.1. Threshold Voltage Variation under HEF Stress

Figure 7 is the V_th variations in PHEF stress according to the types of the switching device. In Figure 7, Si IGBT with SiC diode is named Si IGBT (hybrid). Figure 7a,b demonstrate that V_th of Si IGBT and Si MOSFET had little change under PHEF stress. For Si IGBT with SiC diode, as shown in Figure 7c, the average value of V_th increased by about 3% compared to the initial value. Figure 7d shows the V_th of SiC MOSFET according to PHEF stress time. In the case of SiC MOSFET, V_th rapidly increases after PHEF stress. After 900 s PHEF stress, the average variation of V_th exceeded 100%. Moreover, the average variation of V_th was 166% when PHEF stress was finished. Consequently, under PHEF stress, the SiC MOSFET’s V_th variation is more significant than Si-based devices. The V_th increment in SiC MOSFET indicates that Q_it occurs relatively more than Q_ot.

A small level change in V_th without a noticeable increase or decrease trend can be regarded as a measurement error by the experimental equipment. Therefore, the V_th change of Si IGBT and Si MOSFET in Figure 7 can be considered as the measurement error. On the other hand, since Si IGBT with SiC diode and SiC MOSFET has a marked increase in V_th, even though considering the measurement error, V_th variations in Si IGBT with SiC diode and SiC MOSFET can be referred to as a permanent shift in V_th.

Figure 8 shows V_th variations in NHEF stress according to the types of the switching device. As demonstrated from Figure 8a, in the case of Si IGBT, there were few changes in V_th after NHEF stress. The average V_th variations of Si MOSFET and Si IGBT with SiC diode after 3600 s NHEF stress were −0.6% and −0.4%, respectively. For SiC MOSFET, the amount of V_th reduction was more significant than that of other types of switching devices. When the NHEP stress time was 900 s, averagely, V_th decreased by about 51% compared to the initial value, and when the stress was finished, V_th decreased by about 69%. The V_th reduction in SiC MOSFET means that Q_ot occurs more than Q_it.

Figure 8 indicates that, in NHEF stress, SiC MOSFET experiences considerable V_th reduction. This means that SiC MOSFETs have a greater risk of being switched on when they should be switched off than other types of switching devices. Therefore, SiC MOSFETs are more vulnerable to NHEF stress than Si-based devices.

4.2. On-Resistance Variation under HEF Stress

Figure 9 shows the changes of R_on in PHEF stress according to the switching device. For Si IGBT, shown in Figure 9a, R_on increased by about 1.3% compared to the initial value when the stress was finished. Furthermore, as shown in Figure 9b, the average R_on variation of Si MOSFET was about 0.3% after PHEF stress. For Si IGBT with SiC diode depicted in Figure 9c, four out of five DUTs showed little change, but 3-Ron-P-1 had a reduction tendency of R_on. From this, it can be seen that in the case of the Si-based device, the change in R_on according to PHEF stress is not significant. However, R_on of SiC MOSFET increased rapidly as PHEF stress progressed, as shown in Figure 9d. After the first 900 s of the stress, R_on increased by about 55% on average, and at the end of the stress, R_on rose to about 100% compared to the initial value. As shown in Figure 7d, V_th of SiC MOSFET in PHEF stress rose, resulting in the reduction of V_over in (3). As explained earlier, R_on of SiC MOSFET is greatly affected by R_ch. Therefore, due to the decrement of V_over, R_on rose. Similar to the V_th trends in Figure 7, the rate of change of SiC MOSFET was the largest in R_on. These results indicate that the SiC MOSFET’s conduction loss can be larger than other Si-based devices in the positive gate oxide degradation that raises V_th.

Figure 10 shows the changes of R_on in NHEF stress according to the switching device. Figure 10a–c describe that R_on of Si IGBT, Si MOSFET, and Si IGBT with SiC diode had no trend according to NHEF stress. R_on of Si IGBT had the variation within about 6% depending on the stress. In the case of Si MOSFET, a device with an increase in R_on, a device with a decrease in R_on, and a device with few changes in R_on appear. R_on of Si IGBT (hybrid) had the slightest change according to NHEF stress. Meanwhile, Figure 10d demonstrates that SiC MOSFETs had a reduction trend of R_on according to NHEF stress. At the end of the stress, the variation in R_on of 4-Ron-N-1 was about −6%, and the variation in R_on of 4-Ron-N-5 was about 18%.

The R_on reduction of SiC MOSFET in the NHEF stress can be explained by the V_th change. As shown in Figure 8d, V_th of SiC MOSFET decreases in NHEF stress. This V_th reduction raises V_over in (3). As a result, R_on decreases.

5. Turn-On and Turn-Off Delay under High Electric Field Stress

Figure 11 represents a double pulse test circuit (DPTC) used to measure T_don and T_doff. Figure 11 shows the DPTC used to measure the T_don and T_doff of the switching devices. A gate driver named SKHI22BR was used in this paper. The gate driver driving pulse in the DPTC was generated through a digital signal processor (DSP). The DSP used in this paper is TI TMS320F28335. Furthermore, UP-3005T was used for DC supply. Figure 11a is the circuit diagram for measuring T_don and T_doff. DUT is located at the bottom, as shown in Figure 11a. A large gate driver resistor was used to easily observe T_don and T_doff characteristics [17,21]. The gate driver resistor R_g for T_don and T_doff is 485 Ω.

5.1. Turn-On Delay Variation under HEF Stress

Figure 12 shows some of the results of the T_don experiment in PHEF stress. T_don in the fresh state and T_don after 3600 s of PHEF stress are displayed together. As shown in Figure 12, in the case of Si-based devices, the difference between before and after PHEF stress is not observed. However, as demonstrated from Figure 12d, T_don of 4-Tdon-P-4, which is SiC MOSFET before the stress was about 232 ns, but T_don measured after the stress was about 414.4 ns. Therefore, the T_don of 4-Tdon-P-4 had an increase of about 79% compared to the initial value. A change in T_don can be explained by V_th variation. As shown in Figure 12, the V_th of Si-based devices hardly changed after PHEF stress. However, in the case of SiC MOSFET, V_th grew significantly after PHEF stress. Therefore, the rise of V_th raised T_don.

Figure 13 shows all of the results of the T_don experiment in PHEF stress according to the type of the switching device. Figure 13a–c indicate that there is no significant increase or decrease in T_don according to PHEF stress for Si-based devices. However, in the case of SiC MOSFETs, an increasing trend of T_don was observed in PHEF stress, similar to V_th in Figure 7d. At 900 s of PHEF stress, T_don rose sharply and continued to increase. In particular, 4-Tdon-P-4 had a very large variation of about 80% in T_don compared to the fresh condition after 3600 s of PHEF stress. Other SiC MOSFETs increased by 40% to 50% compared to the initial value. Based on Figure 12 and Figure 13, it can be seen that SiC MOSFETs have a more considerable T_don increment during PHEF stress compared to Si-based devices.

Figure 14represents some of the results of the T_don experiment in NHEF stress. Figure 14 shows that no significant change in T_don was observed for Si-based devices under NHEF stress. However, the T_don of 4-Tdon-N-2 was reduced after NHEF stress. T_don of 4-Tdon-N-2 in the fresh condition was 293.6 ns. Moreover, 4-Tdon-N-2 after NHEF stress was 248 ns. Therefore, the T_don variation of 4-Tdon-N-2 was −16%. This change is opposite to the trend in the PHEF stress of SiC MOSFET. T_don of 4-Tdon-N-2, a SiC MOSFET, was reduced because V_th decreased after NHEF stress.

Figure 15 shows all the results of the T_don experiment in NHEF stress. Figure 15a–c describe that there was no significant change in T_don of Si IGBT, Si MOSFET, and Si IGBT with SiC diode under NHEF stress. However, in SiC MOSET, Figure 15d shows that T_don decreased as the NHEF stress progressed. After 3600 s of NHEF stress, the average T_don of the five SiC MOSFETs decreased by about 13% compared to the initial value. The T_don of SiC MOSFET decreases with the NHEF stress due to the reduction of V_th. As shown in Figure 2, T_don is reduced as V_th decreases. Figure 8d shows that V_th of SiC MOSFET decreased after NHEF stress. Therefore, the T_don of SiC MOSFET is reduced under NHEF stress.

5.2. Turn-Off Delay Variation under HEF Stress

Figure 16 shows some of the results of the T_doff experiment in PHEF stress. As shown in Figure 16, in the case of 1-Tdoff-P-1, 2-Tdoff-P-2, and 3-Tdoff-P-1, the difference between before and after PHEF stress was not clear. However, T_doff of 4-Tdoff-P-4, as shown in Figure 16d, decreased sharply after PHEF stress. The T_doff variation of 4-Tdoff-P-4 was −42%. This reduction in T_doff can be explained by a change in V_m. Looking at the change in V_m before and after PHEF stress shown in Figure 16d, it can be seen that V_m increased after PHEF stress. Therefore, the T_doff of the SiC MOSFET, 4-Tdoff-P-4, is reduced.

Figure 17 is all the results of the T_doff experiment in PHEF stress. For Si IGBT, Si MOSFET, and Si IGBT with SiC diode, Figure 17a–c demonstrate that there was no clear trend of increase or decrease in T_doff in PHEF stress. However, in the case of SiC MOSFETs, T_doff decreased steadily and sharply under PHEF stress. The average T_doff variation of SiC MOSFET after 3600 s of PHEF stress was −46%. In PHEF stress, as shown in Figure 7d, V_th increases. In addition, Equation (7) indicates that when V_th increases, V_m also increases. The rise of V_m decreases T_doff, as illustrated in Figure 3. Therefore, under PHEF stress, the T_doff of SiC MOSFET is reduced, as shown in Figure 17d. Consequently, the T_doff of SiC MOSFET is significantly reduced under PHEF stress compared to other Si-based devices. Figure 18 is some of the results of the T_doff experiment in NHEF stress. Figure 18a–c indicate that Si-based devices did not have much change in T_doff in NHEF stress. However, T_doff of 4-Tdoff-P-4 had a noticeable difference. T_doff of 4-Tdoff-P-4 in the fresh condition was 452.0 ns. Moreover, the T_doff of 4-Tdoff-P-4 after 3600 s of PHEF stress was 560.8 ns. Therefore, the T_doff variation of 4-Tdoff-P-4 was 24%. Figure 18d demonstrates that V_m decreased after NHEF stress. As shown in Figure 3, decreasing V_m raises T_doff. Therefore, the T_doff of 4-Tdoff-P-4 increased.

Figure 19 represents all the results of the T_doff experiment in NHEF stress. For Si-based devices, no clear trend was observed in NHEF stress. However, as shown in Figure 19d, the T_doff of SiC MOSFETs increased as the NHEF stress continued. The average T_doff of SiC MOSFETs after 3600 s of PHEF stress was 24%. In particular, 4-Tdoff-N-3 showed a significant change as T_doff increased by about 33% compared to the initial value. It was mentioned in the previous discussion that the decrement of V_th raises T_doff. Figure 8d demonstrates that V_th decreases with NHEF stress. Therefore, T_doff rises in NHEF stress.

Table 3. Threshold voltage, on-resistance, turn-on delay, and turn-off delay variations according to switch types under HEF stress.

		Si IGBT	Si MOSFET	Si IGBT with SiCDiode	SiC MOSFET
Vth	PHEF	0%	0%	3%	166%
	NHEF	0%	−1%	0%	−69%
Ron	PHEF	1%	0%	0%	100%
	NHEF	−1%	1%	1%	−12%
Tdon	PHEF	−1%	0%	0%	52%
	NHEF	0%	0%	−1%	−13%
Tdoff	PHEF	−1%	1%	0%	−46%
	NHEF	1%	1%	−3%	24%

summarizes changes in V_th, R_on, T_don, and T_doff under HEF stress according to switch types. The values in Table 3 are results obtained after 3600 s of HEF stress. Table 3 demonstrates that V_th, R_on, T_don, and T_doff variations of SiC MOSFET are larger than those of Si-based devices.

6. Performance of Voltage and Current Source Inverter with Duty Error Changes

The previous experimental results demonstrate that T_don and T_doff change after HEF stress. In other words, it means that the duty error of the converter changes as the gate oxide degradation progresses. This section analyzes the effects of duty error change according to HEF stress on the performance of voltage source and current source inverter. In the characteristic analysis according to HEF stress, a large gate resistance was used to sensitively observe changes in T_don and T_doff. T_don and T_doff of SiC MOSFET using a practical gate resistance of 15 Ω are shown in Figure 20.

Figure 20 shows the turn-on and turn-off waveforms when R_g is 15 Ω. As shown in Figure 20, a smaller R_g results in shorter T_don and T_doff because V_gs changes faster. However, since V_th, which is a parameter that determines T_don and T_doff, is the same regardless of R_g, the ratio of the change in T_don and T_doff according to V_th variation is similar even if R_g is different. Therefore, the rate of change of T_don and T_doff according to the HEF stress time obtained in this paper is applicable even when R_g is 15 Ω. As shown in Figure 20, when R_g is 15 Ω, T_don is 56 ns, and T_doff is 64 ns. In order to calculate the change of duty error according to the HEF stress time, it is necessary to know the rate of change of T_don and T_doff according to the stress time. As shown in Figure 13d, Figure 15d, Figure 17d and Figure 19d, T_don, and T_doff in each condition were obtained using five devices. Using the average value of the five devices, the rate of change of T_don and T_doff in PHEF and NHEF stress can be calculated. Figure 21 shows the rate of change of T_don and T_doff obtained by average values of results in Figure 13d, Figure 15d, Figure 17d and Figure 19d. In Figure 21, Rate_don represents the change rate of T_don according to stress time, and Rate_doff means the change rate of T_doff according to stress time.

6.1. Performance Variation of Grid-Connected Voltage Source Inverter with Duty Error Change Due to Gate Oxide Degradation

This section examines the performance variation of the grid-connected voltage source inverter according to the duty error change due to the gate oxide degradation. Figure 22 shows a typical grid-connected voltage source inverter.

In general, a grid-connected voltage source inverter is controlled with a current alone or a current and power simultaneously [23]. Figure 22 shows a grid-connected voltage source inverter with both current and power controls. In Figure 22, S_v1, S_v2, S_v3, S_v4, S_v5, and S_v6 mean the switches of the voltage source inverter. In addition, V_dc is the inverter input voltage, and C_dc is the inverter input capacitor. R_l and L_l are line resistance and line inductance, respectively. Moreover, L_f and C_f mean the inductance and capacitance of the LC filter of the inverter output, respectively. V_g indicates the grid voltage, and i_g represents the grid current. The voltage source inverter in Figure 22 simultaneously controls the grid current and instantaneous power. For the inverter control, first, the three-phase grid voltage and grid current are converted using abc to αβ transformation. The abc to αβ transformation is as (12). In (12), i_ga, i_gb, and i_gb are a-phase, b-phase, and c-phase grid current, respectively. Moreover, v_ga, v_gb, and v_gb are a-phase, b-phase, and c-phase grid voltages, respectively:

$$\begin{array}{c}\left[\begin{array}{c}{i}_{g\alpha }\\ i_{g\beta }\end{array}\right]=\frac{2}{3}\left[\begin{array}{ccc}1& -0.5& -0.5\\ 0& \sqrt{3}/2& -\sqrt{3}/2\end{array}\right]\left[\begin{array}{c}{i}_{ga}\\ i_{gb}\\ i_{gc}\end{array}\right],\\ \left[\begin{array}{c}{v}_{g\alpha }\\ v_{g\beta }\end{array}\right]=\frac{2}{3}\left[\begin{array}{ccc}1& -0.5& -0.5\\ 0& \sqrt{3}/2& -\sqrt{3}/2\end{array}\right]\left[\begin{array}{c}{v}_{ga}\\ v_{gb}\\ v_{gc}\end{array}\right]\end{array}$$

(12)

Using the α and β values of the three-phase grid voltage and current converted by (12), the instantaneous active power (P) and reactive power (Q) are calculated as in (13):

$$P=1.5\left(v_{g\alpha }{i}_{g\alpha }+v_{g\beta }{i}_{g\beta }\right), Q=1.5\left(v_{g\beta }{i}_{g\alpha }-v_{g\alpha }{i}_{g\beta }\right)$$

(13)

The instantaneous reactive power must be controlled to zero for the unity power factor control. Therefore, the reference of the instantaneous reactive power, denoted by Q^*, is set to zero. Moreover, the reference of the instantaneous active power is applied as a desired value. In Figure 22, P^* means the reference of the instantaneous active power. The instantaneous power calculated by (13) and its reference value are inputs to the PI controller for the power control.

Figure 23 shows the PI controller for the power control. The PI controller for the active power control generates an output value by amplifying and integrating the difference between P* and P, as shown in Figure 23. The output value of the active power becomes $i_{gd}^{*}$. Similarly, for the reactive power control, the output value, $i_{gq}^{*}$, is generated by amplifying and integrating the difference between Q* and Q. $i_{gd}^{*}$ and $i_{gq}^{*}$ mean the reference value of the d and q value of the grid current. K_pp, K_ip, K_pq, and K_iq in Figure 23 represent coefficients used in the PI controller for the power control.

Meanwhile, for the grid current control, the d and q values of the grid current are required. By (14), the d and q values of the grid current are obtained:

$$\left[\begin{array}{c}{i}_{gd}\\ i_{gq}\end{array}\right]=\left[\begin{array}{cc}cos\theta & sin\theta \\ -sin\theta & cos\theta \end{array}\right]\left[\begin{array}{c}{i}_{g\alpha }\\ i_{g\beta }\end{array}\right]$$

(14)

In (14), θ is the phase of the grid voltage and is calculated through a phase-locked loop (PLL). The grid current reference values, which are the output of the PI controller for the power control, and the d and q values of the grid current from (14) are applied as the inputs of the PI controller for the grid current control.

Figure 24 shows the PI controller for the grid current control. As shown in Figure 24, to control the d value of the grid current, the output of the PI controller is generated by amplifying and integrating the difference between the reference value and the actual value of i_gd. The output of the PI controller controlling i_gd is $v_d^{*}$, which is the d value of the voltage source inverter control signal. Similarly, to control the q value of the grid current, the output $v_q^{*}$ is generated by amplifying and integrating the difference between the reference value and the actual value of i_gq. $v_q^{*}$ means the q value of the voltage source inverter control signal. The reference values of i_gd and i_gq, which are expressed as $i_{gd}^{*}$ and $i_{gq}^{*}$ are the output of the PI controller for the power control, shown in Figure 23. K_pgd, K_igd, K_pgq, and K_igq in Figure 24 mean coefficients used in the PI controller for the grid current control.

$v_d^{*}$ and $v_q^{*}$ undergoes dq to αβ conversion and αβ to abc conversion, resulting in $v_a^{*}$, $v_b^{*}$, and $v_c^{*}$.The switching signals of the voltage source inverter are generated using space vector modulation [24]. The space vector modulation is implemented using an offset voltage, as shown in Figure 25 [25].

Figure 25 shows the space vector modulation using the offset voltage. $v_a^{*}$, $v_b^{*}$, and $v_c^{*}$ in Figure 25 are the inverter control signal of a-phase, b-phase, and c-phase, respectively.$v_a^{*}$, $v_b^{*}$, and $v_c^{*}$ are obtained from dq to αβ conversion and αβ to abc conversion of $v_d^{*}$ and $v_q^{*}$. The offset voltage is calculated as follows (15):

$$v_{off}=-0.5·\left(V_{max}+V_{min}\right)$$

(15)

In (15), v_off means the offset voltage for the space vector modulation. Moreover, the largest of $v_a^{*}$, $v_b^{*}$, and $v_c^{*}$ becomes V_max and the smallest becomes V_min. Switching signals are generated by comparing the carrier with the values obtained by adding the offset voltage to $v_a^{*}$, $v_b^{*}$, and $v_c^{*}$. Note that the switching frequency of the inverter is determined by the frequency of the carrier. In the voltage source inverter, the switches of one leg operate complementarily. Since a huge current can flow at the moment when all the switches of one leg of the voltage source inverter are on, the dead-time is set to make all switches of one leg be off when the switching state changes. In addition, the duty of the switch is changed by T_don and T_doff. Figure 26 shows gating signals and the a-phase pole voltage considering the dead time, T_don, and T_doff of S_v1 and S_v4 which are the a-phase switches of the grid-connected voltage source inverter in Figure 22.

In Figure 26, T_d means the dead time. Furthermore, V_aN is the a-phase pole voltage. T_r is the ideal dwelling time of V_aN. T_actp/f is the dwelling time of V_aN considering T_d, T_don, and T_doff when the switching devices are fresh and the pole current (i) is positive. In addition, T_actn/f is the dwelling time of V_aN considering T_d, T_don, and T_doff when the switching devices are fresh and the pole current is negative. T_don/a and T_doff/a denote turn-on delay and turn-off delay in aged condition, respectively. Moreover, T_actp/a is the dwelling time of V_aN considering T_d, T_don, and T_doff when the switching devices are aging and the pole current is positive. In addition, T_actn/a is the dwelling time of V_aN considering T_d, T_don, and T_doff when the switching devices are aging, and the pole current is negative. Figure 26a,b show the current path according to the pole current direction. Figure 26a,b demonstrate that the dwell time of V_aN changes, as shown in Figure 26c, because the path through which the current flows varies according to the sign of the pole current [26]. Equation (16) represents T_actp/f and T_actn/f:

$$\begin{array}{c}{T}_{actp/f}=T_r-T_d-T_{don/f}+T_{doff/f},\\ T_{actn/f}=T_r+T_d-T_{don/f}+T_{doff/f}\end{array}$$

(16)

Equation (16) becomes as (17) when aging is considered:

$$\begin{array}{c}{T}_{actp/a}=T_r-T_d-T_{don/a}+T_{doff/a},\\ T_{actn/a}=T_r+T_d-T_{don/a}+T_{doff/a}. \end{array}$$

(17)

T_don/a and T_doff/a in (17) can be calculated through (18):

$$\begin{array}{c}{T}_{don/a}=T_{don/f}(1 + 0.01{Rate}_{don}),\\ T_{doff/a}=T_{doff/f}(1 + 0.01{Rate}_{doff})\end{array}$$

(18)

In (18), Rate_don and Rate_doff can be obtained from Figure 21. Meanwhile, the duty error due to aging can be calculated as (19) using (17) and the voltage source inverter switching frequency (F_swv):

$$\begin{array}{c}{D}_{epv}=\left(T_{actp/a}-T_r\right)F_{swv}=\left(-T_d-T_{don/a}+T_{doff/a}\right)F_{swv},\\ D_{env}=\left(T_{actn/a}-T_r\right)F_{swv}=\left(+T_d-T_{don/a}+T_{doff/a}\right)F_{swv}. \end{array}$$

(19)

In (19), D_epv means the duty error of the voltage source inverter due to the gate oxide degradation when the pole current is positive. D_env also represents the duty error of the voltage source inverter due to the gate oxide degradation when the pole current is negative. Figure 27 shows the duty error of the voltage source inverter according to the aging stress time.

Figure 27a shows the duty error according to the stress time when the pole current is positive. When the pole current is positive, the duty error increases at PHEF stress and decreases at NHEF stress. Figure 27b shows the duty error according to the stress time when the pole current is negative. When the pole current is negative, the duty error at PHEF stress decreases and the duty error at NHEF stress increases. In this chapter, the effects of the change in the duty error due to the gate oxide degradation on the output of the grid-connected inverter are analyzed through simulation. The parameters of the inverter used in the simulation are summarized in

Table 4. Parameters of grid-connected voltage source inverter.

Parameters	Value
Vdc	700 V
Cdc	550 uF
Lf	3 mH
Cf	20 uF
Rl	0.2 Ω
Ll	0.15 mH
Vg	311.13 V
Switching frequency	20 kHz
Tdp	0.3 us
P*	3 kW
Q*	0

.

Figure 28 shows the simulation results of the grid-connected voltage source inverter according to HEF stress. Figure 28a–c are simulation results when using the duty error calculated from the fresh condition, PHEF stress during 3600 s, and NHEF stress during 3600 s, respectively. Figure 28 demonstrates that the THD of the grid current is the highest when the NHEF stress is applied for 3600 s. In addition, the peak-to-peak value of P is the largest in the case of PHEF stress. Moreover, the peak-to-peak value of Q is the largest in the case of NHEF stress.

Figure 29 showsgraphs summarizing the THD of the grid current and the peak-to-peak values of the instantaneous power according to the stress time. Figure 29 indicates that as the gate oxide degradation progresses, the quality of the grid current and the reference tracking ability of the voltage source inverter deteriorates.

Figure 30 shows experiment waveforms of a three-phase voltage source inverter with RL load. A-phase of the inverter in Figure 30 was composed of SiC MOSFETs aged with PHEF stress. In addition, the remaining phases were composed of fresh SiC MOSFETs. Figure 30a represents the waveforms when the upper switch of a-phase is turned on. In Figure 30a, V_{ds_Sau} means the V_ds of the upper switch of a-phase. Furthermore, V_{gs_Sau} represents the V_gs of the upper switch of a-phase. Moreover, I_{ds_Sau} is the I_ds of the upper switch of a-phase. Figure 30a shows that the turn-on delay of the a-phase upper switch is 60 ns. Figure 30b is the three-phase current waveform of the inverter. In Figure 30b, i_La, i_Lb, and i_Lc represent the a-phase, b-phase, and c-phase inverter currents, respectively. Figure 30b demonstrates that the shape of the waveform hardly changes even when a-phase is aged.Therefore, Figure 30b shows that the aging degree of the inverter cannot be monitored by the load current shape.

6.2. Performance Variation of Current Source Inverter with Duty Error Change Due to Gate Oxide Degradation

This section examines the performance variation of the current source inverter (CSI) according to the duty error change due to the gate oxide degradation. Figure 31 shows a three-phase CSI.

In Figure 31, S_c1, S_c2, S_c3, S_c4, S_c5, and S_c6 represent the switches of the CSI. Additionally, R_c and L_c are the load resistor and inductor, respectively. Moreover, i_c means the output current of the current source inverter. I_dc is the input DC current supplied by the current source which can be expressed as a voltage source (V) and an inductor (L_dc) connected in series. L_dc represents the DC link inductor. C_c is the output capacitor required to drive the current source inverter. The current source inverter is usually controlled by space vector modulation [27].

In the CSI, I_dc on the input side must flow without interruption. If the path through which I_dc can flow disappears, an overvoltage is induced in L_dc. The voltage induced by the variation of I_dc is expressed by (20). In (20), V_Ldc denotes a voltage induced in L_dc. Therefore, in the current source inverter, the overvoltage in L_dc is prevented by setting the overlap time when the switching state changes:

$$V_{Ldc}=L_{dc}\frac{d{I}_{dc}}{dt}$$

(20)

Figure 32 represents the gating signals of the CSI in Figure 30.

In Figure 32, T_ov means the overlap-time set in advance when outputting the switching signals. In addition, T_or/f means the dwelling time of the switching signal considering T_ov, T_don, and T_doff in the fresh state. Moreover, T_or/a represents the dwelling time of the switching signal considering T_ov, T_don, and T_doff in the aged state. T_rc indicates the dwelling time of the switching signal under ideal conditions. T_or/f and T_or/a are calculated through (21):

$$\begin{array}{c}{T}_{or/f}=T_{rc}+T_{ov}-T_{don/f}+T_{doff/f},\\ T_{or/a}=T_{rc}+T_{ov}-T_{don/a}+T_{doff/a}\end{array}$$

(21)

T_don/a and T_doff/a in (21) are calculated by (18). From (21), the duty error of the CSI when it is aged can be obtained as (22):

$$D_{ec}=\left(T_{or/a}-T_{rc}\right)F_{swc}=\left(T_{ov}-T_{don/a}+T_{doff/a}\right)F_{swc}$$

(22)

In (22), D_ec means the duty error of the CSI according to aging. Moreover, F_swc represents the switching frequency of the CSI. Figure 33 shows the duty error of the CSI according to the HEF stress time. As shown in Figure 33, the duty error decreases under PHEF stress and increases under NHEF stress.

A simulation was conducted to find out the effect of the change in duty error due to the gate oxide degradation on the CSI output current THD. Using the simulation, the THD of the output current of the CSI according to the duty error is examined. The CSI is controlled through space vector modulation, and open-loop control is performed. The parameters of the CSI used in the simulation are shown in

Table 5. Parameters of CSI.

Parameters	Value
Idc	10 A
Rc	10 Ω
Lc	1 mH
Cf	20 uF
Switching frequency	5 kHz
Tov	0.3 us
Modulation index	0.2

.

Figure 34 shows the simulation results of the CSI according to HEF stress. i_ca, i_cb, and i_cc in Figure 34 represent the a, b, and c-phase output currents of the CSI, respectively. Figure 34 demonstrates that simulation results at PHEF stress have the smallest THD of the output current. In addition, the output current quality at NHEF stress is the worst.

Figure 35 summarizes the average of the three-phase output current of the CSI according to the stress time. Figure 35 shows that in the case of PHEF stress, where the duty error decreases with the stress time, the THD of the three-phase output current is reduced as the stress time increases. However, in the case of NHEF stress, the THD of the output current slightly increases because the duty error rises with the stress time.

7. Conclusions

This paper conducted studies on the changes in T_don and T_doff of SiC MOSFETs due to the gate oxide degradation. In addition, the performance variations of voltage and current source inverters due to changes in T_don and T_doff were examined. As a result, it was confirmed that T_don and T_doff of SiC MOSFETs significantly changed compared to other Si-based devices under the gate oxide degradation. In addition, variations in T_don and T_doff due to the gate oxide degradation worsened the output performance of the voltage source inverter. Moreover, changes in T_don and T_doff due to the negative gate oxide degradation reducing V_th declined the output performance of the current source inverter. These results indicate that the output performances of the SiC MOSFET-based voltage and current source inverter deteriorate under gate oxide degradation.