Impacts of SiC-MOSFET Gate Oxide Degradation on Three-Phase Voltage and Current Source Inverters

In this paper, the performance variations of SiC MOSFET-based voltage and current source inverters under gate oxide degradation are studied. It is confirmed that the turn-on and turn-off delays of SiC MOSFETs change significantly by high electric field stress, which accelerates the gate oxide degradation. Variations in the turn-on and turn-off delays of switching devices extend or reduce the duty error of voltage source inverters and current source inverters. The performance variations of the voltage and current source inverter due to the duty error changes caused by the gate oxide degradation are analyzed through simulations. As a result, the gate oxide degradation worsens the performance of the voltage source inverter. Furthermore, the negative gate oxide degradation, which lowers the threshold voltage, decreases the performance of the current source inverter.


Introduction
Along with gallium nitride (GaN) field effect transistor (FET), silicon carbide (SiC) metal-oxide-semiconductor field (MOSFET), a wide bandgap (WBG) device, is attracting attention as a next-generation power switching device due to its high efficiency and power density [1,2]. In particular, SiC MOSFET is increasingly used in systems close to human life, such as electric vehicles [3]. As a result, the reliability of SiC MOSFET is becoming more important.
A gate oxide degradation is a major aging phenomenon that affects the reliability of SiC MOSFET along with a package degradation [4]. The package degradation is caused by thermomechanical stress caused by temperature change [5]. If the package degradation continues, phenomena, such as bond wire crack and lift-off, occur, leading to a switching device failure [6,7]. Meanwhile, SiC MOSFET has a thin gate oxide layer, so electrons can be injected into the oxide layer by the Fowler-Nordheim tunneling current. Moreover, there are more interface trapped charges on the SiC/SiO 2 interface than Si MOSFET [8,9]. In particular, the interface trapped charge reduces the effective channel-carrier mobility and changes the threshold voltage (V th ). The reduced effective channel-carrier mobility eventually increases the on-resistance (R on ) of the switch. The shift direction of the V th is determined by the sum of the oxide trapped charge and the interface trapped charge. These charges are changed more significantly by the gate oxide degradation. An increase in V th causes an increase in conduction losses. Moreover, a decrease in V th increases the risk of the switch being turned on undesirably [10,11]. If the gate oxide degradation continues, the gate insulation is eventually destroyed, and the control ability of the gate to switch is lost [12].
The gate oxide degradation is accelerated under high electric field (HEF) stress or high-temperature stress [13]. HEF stress is divided into positive HEF (PHEF) stress applying a positive voltage to the gate, and negative HEF (NHEF) stress using a negative voltage. Characteristic changes during the gate oxide degradation of SiC MOSFETs have been studied through muchresearch [8,10,[13][14][15][16][17], and Table 1 summarizes the previous research about the characteristics of SiC MOSFETs under gate oxide degradation. In Table 1, characteristics covered by the study were marked with an O, and properties not investigated by the analysis were marked with an X. Furthermore, the characteristics measured when the switching state is fixed are defined as stationary properties, and the properties measured when the switching state changes are defined as transient properties. The stationary properties are V th , R on , gate-drain capacitance (C gd ), gate-source capacitance (C gs ), and body diode forward voltage (V sd ). Moreover, the transient properties are Miller plateau voltage (V m ), Miller plateau time (T m ), gate charge time (T gc ), turn-on delay (T don ), and turn-off delay (T doff ). As shown in Table 1, previous studies dealt with the SiC MOSFET's stationary properties under gate oxide degradation. However, research about transient characteristics of SiC MOSFET has not been conducted much. Especially, except for T don in [13], no studies on T don and T doff under gate oxide degradation were conducted in previous studies. T don and T doff can impact the performance of voltage and current source converters. The voltage source converter has a dead time to prevent a short circuit accident when one leg's switches are turned on simultaneously [18]. The dead time causes a duty error in the voltage vector. In addition to the dead time, T don and T doff introduce duty errors. These duty errors change the output quality of the voltage source converter. Furthermore, an overlap time is required in the current source converter to prevent an overvoltage of the DC link inductor from occurring when all upper or lower switches are turned off simultaneously [19]. Like the voltage source converter, the overlap time, T don , and T doff generate the duty errors in the current vector, resulting in changes in the output quality of the current source converter. Therefore, studies on changes in T don and T doff under gate oxide degradation are necessary.
In this paper, the changes of T don and T doff of SiC MOSFET in the gate oxide degradation are examined. In addition, the effects of T don and T doff variations caused by the gate oxide degradation on the performance of voltage and current source inverters are studied.
The structure of this paper is as follows. Section 1 is the introduction. Section 2 analyzes the effects of V th on R on , T don , and T doff . Section 3 describes HEF stress to accelerate the gate oxide degradation. Section 4 compares V th and R on changes of SiC MOSFET under HEF stress with those of Si-based devices. Section 5 compares the changes in T don and T doff of SiC MOSFET under HEF stress with those of Si-based devices. In Section 6, the performance variations of voltage and current source inverters according to the duty error changes due to the gate oxide degradation are examined by the simulation. Section 7 is the conclusion.

Gate Oxide Degradation
Gate oxide degradation is aging occurring in the gate oxide layer. Furthermore, it is one of the major degradations of MOSFETs, like package degradation. As the gate oxide degradation progresses, there is a change in V th , and this change can be explained by the oxide trapped charge and the interface trapped charge in the gate oxide layer. Figure 1 is a structure of the MOSFET and the gate oxide layer.
Machines 2022, 10, x FOR PEER REVIEW 3 of 30 changes due to the gate oxide degradation are examined by the simulation. Section 7 is the conclusion.

Gate Oxide Degradation
Gate oxide degradation is aging occurring in the gate oxide layer. Furthermore, it is one of the major degradations of MOSFETs, like package degradation. As the gate oxide degradation progresses, there is a change in Vth, and this change can be explained by the oxide trapped charge and the interface trapped charge in the gate oxide layer. Figure 1 is a structure of the MOSFET and the gate oxide layer. In Figure 1, Qot denotes the oxide trapped charge, and Qit means the interface trapped charge. By the gate oxide degradation, Qot is generated inside the oxide layer, and Qit is generated on the surface of the oxide layer. Vth can be expressed as (1) using Qot and Qit [20]: In (1), Vth0 means Vth in a fresh condition where the gate oxide degradation does not proceed. Cox represents the gate oxide capacitance per unit area. Furthermore, q stands for the electric charge. Moreover, Nit and Not mean the interface trap density and the oxide trap density, respectively. When the gate oxide degradation proceeds, Qit and Qot are generated. Vth increases or decreases depending on which charge is more generated relatively. As seen from (1), when Qit occurs relatively significantly, Vth rises. On the other hand, when Qot is relatively large, Vth decreases. The gate oxide degradation is accelerated by HEF stress. In general, in PHEF stress where a positive voltage is applied to the gate voltage, Qit is generated significantly to increase Vth. Meanwhile, in NHEF stress where a negative voltage is applied to the gate voltage, Qot is generated relatively significantly, and Vth decreases.

On-Resistance Variation Caused by Threshold Voltage
Ron can be subdivided into several types of resistances as follows (2) [8]: In (2), Rch is the channel resistance, RA is the accumulation resistance, RJFET is the JFET region resistance, Rd is the drift region resistance, and Rsub is the substrate resistance. In the case of SiC MOSFETs, among the five resistance types, Rch is the most dominant [8]. Rch can be expressed as (3) [8]:  In Figure 1, Q ot denotes the oxide trapped charge, and Q it means the interface trapped charge. By the gate oxide degradation, Q ot is generated inside the oxide layer, and Q it is generated on the surface of the oxide layer. V th can be expressed as (1) using Q ot and Q it [20]: In (1), V th0 means V th in a fresh condition where the gate oxide degradation does not proceed. C ox represents the gate oxide capacitance per unit area. Furthermore, q stands for the electric charge. Moreover, N it and N ot mean the interface trap density and the oxide trap density, respectively. When the gate oxide degradation proceeds, Q it and Q ot are generated. V th increases or decreases depending on which charge is more generated relatively. As seen from (1), when Q it occurs relatively significantly, V th rises. On the other hand, when Q ot is relatively large, V th decreases. The gate oxide degradation is accelerated by HEF stress. In general, in PHEF stress where a positive voltage is applied to the gate voltage, Q it is generated significantly to increase V th . Meanwhile, in NHEF stress where a negative voltage is applied to the gate voltage, Q ot is generated relatively significantly, and V th decreases.

On-Resistance Variation Caused by Threshold Voltage
R on can be subdivided into several types of resistances as follows (2) [8]: In (2), R ch is the channel resistance, R A is the accumulation resistance, R JFET is the JFET region resistance, R d is the drift region resistance, and R sub is the substrate resistance. In the case of SiC MOSFETs, among the five resistance types, R ch is the most dominant [8]. R ch can be expressed as (3) [8]: In (3), L ch means the channel length, and W ch represents the channel width. In addition, µ and V over represent the channel mobility and the overdrive voltage, respectively. V over is expressed as the difference between the gate-source voltage (V gs ) and V th . As seen from (3), the variation of V over changes R ch . Therefore, when V th changes, R ch also changes. When V th increases, V over decreases, and R ch increases. When V th decreases, V over increases, and R ch decreases. As a result, R on increases when V th increases, and R on decreases when V th decreases.

Turn-On Delay Variation Caused by Threshhold Voltage
A definition of T don is the time from when V gs starts to rise to when the drain-source current (I ds ) starts to increase [21]. V th is related to T don because V th is the voltage at which I ds starts flowing through the switch. Figure 2 shows V gs and I ds waveforms when the switch is turned on. In (3), Lch means the channel length, and Wch represents the channel width. In addition, μ and Vover represent the channel mobility and the overdrive voltage, respectively. Vover is expressed as the difference between the gate-source voltage (Vgs) and Vth. As seen from (3), the variation of Vover changes Rch. Therefore, when Vth changes, Rch also changes. When Vth increases, Vover decreases, and Rch increases. When Vth decreases, Vover increases, and Rchdecreases. As a result, Ron increases when Vth increases, and Ron decreases when Vth decreases.

Turn-On Delay Variation Caused by Threshhold Voltage
A definition of Tdon is the time from when Vgs starts to rise to when the drain-source current (Ids) starts to increase [21]. Vth is related to Tdon because Vth is the voltage at which Ids starts flowing through the switch. Figure 2 shows Vgs and Ids waveforms when the switch is turned on. In Figure 2, t0 means the time when Vgs starts to increase to turn on the switch. In addition, tthf indicates the time when Ids in the fresh condition begin to rise. tthn and tthp denote a time at which Ids start to grow when Vth is negatively shifted and positively shifted, respectively. Vth and Ids in the fresh condition are expressed as Vthf and Idsf, respectively. Furthermore, Vth and Ids in the negative Vth shift are described as Vthn and Idsn, respectively. Moreover, Vth and Ids in the positive Vth shift are denoted as Vthp and Idsp, respectively. As shown in Figure 2, Ids starts to flow when Vgs becomes greater than Vth. Tdon of the fresh state, the negative Vth shift, and the positive Vth shift can be expressed by (4), respectively: Tdonf, Tdonn, and Tdonp in (4) mean Tdon in fresh condition, negative Vth shift, and positive Vth shift, respectively. As shown in Figure 2, comparisons of Tdonf, Tdonn, and Tdonp are expressed as (5). Therefore, as Vth increases, Tdon increases:

Turn-Off Delay Caused by Threshold Voltage
A definition of Tdoff is the time from when Vgs starts to decrease to when the drain-source voltage (Vds) begins to grow [22]. The point at which Vds increases in the off transition is when Vgs enters Vm [22]. Therefore, the change in Tdoff can be explained by Vm. The relationship between Vm and Vth can be expressed by (6) [20]: Partial differentiation of (6) with respect to Not and Nit gives the following (7) [20]:  In Figure 2, t 0 means the time when V gs starts to increase to turn on the switch. In addition, t thf indicates the time when I ds in the fresh condition begin to rise. t thn and t thp denote a time at which I ds start to grow when V th is negatively shifted and positively shifted, respectively. V th and I ds in the fresh condition are expressed as V thf and I dsf , respectively. Furthermore, V th and I ds in the negative V th shift are described as V thn and I dsn , respectively. Moreover, V th and I ds in the positive V th shift are denoted as V thp and I dsp , respectively. As shown in Figure 2, I ds starts to flow when V gs becomes greater than V th . T don of the fresh state, the negative V th shift, and the positive V th shift can be expressed by (4), respectively: T donf , T donn , and T donp in (4) mean T don in fresh condition, negative V th shift, and positive V th shift, respectively. As shown in Figure 2, comparisons of T donf , T donn , and T donp are expressed as (5). Therefore, as V th increases, T don increases:

Turn-Off Delay Caused by Threshold Voltage
A definition of T doff is the time from when V gs starts to decrease to when the drainsource voltage (V ds ) begins to grow [22]. The point at which V ds increases in the off transition is when V gs enters V m [22]. Therefore, the change in T doff can be explained by V m . The relationship between V m and V th can be expressed by (6) [20]: Partial differentiation of (6) with respect to N ot and N it gives the following (7) [20]: Machines 2022, 10, 1194 From (7), it can be seen that an increase in V th increases V m and vice versa. Figure 3 shows the relationship between the change in V m and T doff .
Machines 2022, 10, x FOR PEER REVIEW 5 of 30 From (7), it can be seen that an increase in Vth increases Vm and vice versa. Figure 3 shows the relationship between the change in Vm and Tdoff. In Figure 3, Vmp, Vmf, and Vmn mean Vm in positive Vth shift, fresh state, and negative Vth shift, respectively. In addition, tmp, tmf, and tmn indicate a time when Vds increases in positive Vth shift, fresh state, and negative Vth shift, respectively. tm0 is the point at which Vgs begins to decrease to turn off the switch. Figure 3 indicates that the time at which Vds increases is faster as Vm increases. Therefore, as Vm increases, Tdoff decreases and vice versa. Tdoff can be expressed as (8): In (8), Tdoffp, Tdofff, and Tdoffn denote Tdoff in a positive Vth shift, fresh state, and negative Vth shift, respectively. The magnitudes of Tdoffp, Tdofff, and Tdoffn can be expressed as (9):

High Electric Field Stress
As shown in Figure 4, The HEF stress circuit was constructed to accelerate the gate oxide degradation. The fabricated circuit was configured to apply HEF stress to five devices simultaneously. The drain and source or collector and emitter of the switching device were shorted to be connected to the ground. A resistor of 200 Ω was inserted to alleviate the overshoot of the gate current when HEF stress was applied to the gate side [8]. HEF stress was applied for 3600 s at room temperature, and the switching devices were disconnected from the HEF stress circuit every 900 s to measure Vth, Ron, Tdon, and Tdoff of the switching devices. The gate bias value used for HEF stress should be the proper value for accelerating the gate oxide degradation and preventing the gate insulation destruction. For this, 50 V was used as the gate bias value in PHEF. In the case of NHEF, the gate bias value was set to −38 V. In this paper, characteristics, such as Vth, Ron, Tdon, and Tdoff, were compared by applying HEF stress under the same conditions to various Si-based In Figure 3, V mp , V mf , and V mn mean V m in positive V th shift, fresh state, and negative V th shift, respectively. In addition, t mp , t mf , and t mn indicate a time when V ds increases in positive V th shift, fresh state, and negative V th shift, respectively. t m0 is the point at which V gs begins to decrease to turn off the switch. Figure 3 indicates that the time at which V ds increases is faster as V m increases. Therefore, as V m increases, T doff decreases and vice versa. T doff can be expressed as (8): In (8), T doffp , T dofff , and T doffn denote T doff in a positive V th shift, fresh state, and negative V th shift, respectively. The magnitudes of T doffp , T dofff , and T doffn can be expressed as (9):

High Electric Field Stress
As shown in Figure 4, The HEF stress circuit was constructed to accelerate the gate oxide degradation. The fabricated circuit was configured to apply HEF stress to five devices simultaneously. The drain and source or collector and emitter of the switching device were shorted to be connected to the ground. A resistor of 200 Ω was inserted to alleviate the overshoot of the gate current when HEF stress was applied to the gate side [8]. HEF stress was applied for 3600 s at room temperature, and the switching devices were disconnected from the HEF stress circuit every 900 s to measure V th , R on , T don , and T doff of the switching devices. The gate bias value used for HEF stress should be the proper value for accelerating the gate oxide degradation and preventing the gate insulation destruction. For this, 50 V was used as the gate bias value in PHEF. In the case of NHEF, the gate bias value was set to −38 V. In this paper, characteristics, such as V th , R on , T don , and T doff , were compared by applying HEF stress under the same conditions to various Si-based devices as well as SiC MOSFET. The reason for this comparison is to confirm that SiC MOSFET is more susceptible to the gate oxide degradation compared to other Si-based devices. The Si-based devices used for comparison are Si IGBT, Si MOSFET, and Si IGBT with SiC diode. Information on the switching devices used for characteristic comparison is given in Table 2.  The maximum gate voltages of Si IGBT, Si MOSFET, Si IGBT with SiC diode, and SiC MOSFET, as seen from the datasheet, are −30/+30 V, −30/+30 V, −20/+20 V, and −4/+22 V, respectively. Therefore, it can be inferred from the datasheet that the SiC MOSFET is most vulnerable to the large gate voltage. This paper experimentally checks a low-rated gate voltage of SiC MOSFET by applying the same voltage stress to four types of switching devices and examines a change of electrical characteristics caused by the gate oxide degradation.

Investigation of Threshold Voltage and On-resistance under High Electric Field Stress
This paper investigated Vth and Ron according to HEF stress. The Vth and Ron measurement circuits were configured as shown in Figure 5.   The maximum gate voltages of Si IGBT, Si MOSFET, Si IGBT with SiC diode, and SiC MOSFET, as seen from the datasheet, are −30/+30 V, −30/+30 V, −20/+20 V, and −4/+22 V, respectively. Therefore, it can be inferred from the datasheet that the SiC MOSFET is most vulnerable to the large gate voltage. This paper experimentally checks a low-rated gate voltage of SiC MOSFET by applying the same voltage stress to four types of switching devices and examines a change of electrical characteristics caused by the gate oxide degradation.

Investigation of Threshold Voltage and On-Resistance under High Electric Field Stress
This paper investigated V th and R on according to HEF stress. The V th and R on measurement circuits were configured as shown in Figure 5. Figure 5 shows the case of Si MOSFET and SiC MOSFET. In the case of Si IGBT and Si IGBT with SiC diode, V gs and I ds correspond to gate-emitter voltage (V ge ) and collectoremitter current (I ce ), respectively. Figure 5a shows the V th measurement circuit.A device under test (DUT) is connected to measure V th , as shown in Figure 5a.Then, the magnitude of V gs is gradually raised from 0 V until I ds is 1 mA. V gs , when I ds becomes 1 mA, is V th [14]. Table 2, I ds (or I ce ) used to measure V th is very small for Si MOSFET and Si IGBT with SiC diode. These values are very small to measure with an oscilloscope. Therefore, I ds (or I ce ) of 1 mA that can be measured with a small error is selected, and V th is measured with 1 mA for all four devices.  Figure 5 shows the case of Si MOSFET and SiC MOSFET. In the case of Si IGBT and Si IGBT with SiC diode, Vgsand Idscorrespond to gate-emitter voltage (Vge) and collector-emitter current (Ice), respectively. Figure 5a shows the Vth measurement circuit.A device under test (DUT) is connected to measure Vth, as shown in Figure 5a.Then, the magnitude of Vgs is gradually raised from 0 V until Ids is 1 mA.Vgs, when Ids becomes 1 mA, is Vth [14]. As shown in Table 2, Ids (or Ice) used to measure Vth is very small for Si MOSFET and Si IGBT with SiC diode. These values are very small to measure with an oscilloscope. Therefore, Ids (or Ice) of 1 mA that can be measured with a small error is selected, and Vth is measured with 1 mA for all four devices. Figure 5b represents the Ron measurement circuit. To measure Ron, the voltage used to measure Ron in the datasheet of each device is applied to Vgs. That is, Vgs for Ron measurement is 15 V for Si IGBT, 10 V for Si MOSFET, 15 V for Si IGBT with SiC diode, and 18 V for SiC MOSFET. Then, Ids and Vds when the switch is fully on are measured with an oscilloscope to eliminate the effect of parasitic components. Meanwhile, Ron varies with respect to the junction temperature.In order to reduce the variation caused by the junction temperature change, the temperature rise of the switch is minimized by applying Ids (about 2 A) which is much smaller than the rated value of the switch for a short time (about 40 ms). Ron is calculated using the measured Vds and Ids as (10):

As shown in
The measured device characteristics are expressed as the rate of change concerning the initial value as (11): In (11), Paging represents a characteristic of the aging device. Moreover, Pfresh is a property of the fresh device. In Figure 6, the rules are established to distinguish the devices used in this paper.  Figure 5. Measurement circuits (a) V th (b) R on . Figure 5b represents the R on measurement circuit. To measure R on , the voltage used to measure R on in the datasheet of each device is applied to V gs . That is, V gs for R on measurement is 15 V for Si IGBT, 10 V for Si MOSFET, 15 V for Si IGBT with SiC diode, and 18 V for SiC MOSFET. Then, I ds and V ds when the switch is fully on are measured with an oscilloscope to eliminate the effect of parasitic components. Meanwhile, R on varies with respect to the junction temperature.In order to reduce the variation caused by the junction temperature change, the temperature rise of the switch is minimized by applying I ds (about 2 A) which is much smaller than the rated value of the switch for a short time (about 40 ms). R on is calculated using the measured V ds and I ds as (10):

DUT
The measured device characteristics are expressed as the rate of change concerning the initial value as (11): Variation (%) = (P aging − P fresh )/P fresh ·100 (11) In (11), P aging represents a characteristic of the aging device. Moreover, P fresh is a property of the fresh device. In Figure 6, the rules are established to distinguish the devices used in this paper.  Figure 5 shows the case of Si MOSFET and SiC MOSFET. In the case of Si IGBT and Si IGBT with SiC diode, Vgsand Idscorrespond to gate-emitter voltage (Vge) and collector-emitter current (Ice), respectively. Figure 5a shows the Vth measurement circuit.A device under test (DUT) is connected to measure Vth, as shown in Figure 5a.Then, the magnitude of Vgs is gradually raised from 0 V until Ids is 1 mA.Vgs, when Ids becomes 1 mA, is Vth [14]. As shown in Table 2, Ids (or Ice) used to measure Vth is very small for Si MOSFET and Si IGBT with SiC diode. These values are very small to measure with an oscilloscope. Therefore, Ids (or Ice) of 1 mA that can be measured with a small error is selected, and Vth is measured with 1 mA for all four devices. Figure 5b represents the Ron measurement circuit. To measure Ron, the voltage used to measure Ron in the datasheet of each device is applied to Vgs. That is, Vgs for Ron measurement is 15 V for Si IGBT, 10 V for Si MOSFET, 15 V for Si IGBT with SiC diode, and 18 V for SiC MOSFET. Then, Ids and Vds when the switch is fully on are measured with an oscilloscope to eliminate the effect of parasitic components. Meanwhile, Ron varies with respect to the junction temperature.In order to reduce the variation caused by the junction temperature change, the temperature rise of the switch is minimized by applying Ids (about 2 A) which is much smaller than the rated value of the switch for a short time (about 40 ms). Ron is calculated using the measured Vds and Ids as (10): The measured device characteristics are expressed as the rate of change concerning the initial value as (11): In (11), Paging represents a characteristic of the aging device. Moreover, Pfresh is a property of the fresh device. In Figure 6, the rules are established to distinguish the devices used in this paper.    Figure 6. Device naming rule in this paper. Figure 6 shows the device naming rule used in this paper. A device's name is divided into four parts. The first part indicates the type of switching device. As shown in Figure 6, a number is assigned to each switch type. The second part shows the measured device property. The third part is the type of HEF, and the last part means the device number. The example of Figure 6, 1-Vth-P-1, refers to the first switch among the five switches where PHEF stress is applied to the Si IGBT for the V th measurement. Figure 7 is the V th variations in PHEF stress according to the types of the switching device. In Figure 7, Si IGBT with SiC diode is named Si IGBT (hybrid). Figure 7a,b demonstrate that V th of Si IGBT and Si MOSFET had little change under PHEF stress. For Si IGBT with SiC diode, as shown in Figure 7c, the average value of V th increased by about 3% compared to the initial value. Figure 7d shows the V th of SiC MOSFET according to PHEF stress time. In the case of SiC MOSFET, V th rapidly increases after PHEF stress. After 900 s PHEF stress, the average variation of V th exceeded 100%. Moreover, the average variation of V th was 166% when PHEF stress was finished. Consequently, under PHEF stress, the SiC MOSFET's V th variation is more significant than Si-based devices. The V th increment in SiC MOSFET indicates that Q it occurs relatively more than Q ot .

Threshold Voltage Variation under HEF Stress
Machines 2022, 10, x FOR PEER REVIEW 8 of 30 Figure 6 shows the device naming rule used in this paper. A device's name is divided into four parts. The first part indicates the type of switching device. As shown in Figure 6, a number is assigned to each switch type. The second part shows the measured device property. The third part is the type of HEF, and the last part means the device number. The example of Figure 6, 1-Vth-P-1, refers to the first switch among the five switches where PHEF stress is applied to the Si IGBT for the Vth measurement. Figure 7 is the Vth variations in PHEF stress according to the types of the switching device. In Figure 7, Si IGBT with SiC diode is named Si IGBT (hybrid). Figure 7a,b demonstrate that Vth of Si IGBT and Si MOSFET had little change under PHEF stress. For Si IGBT with SiC diode, as shown in Figure 7c, the average value of Vth increased by about 3% compared to the initial value. Figure 7d shows the Vth of SiC MOSFET according to PHEF stress time. In the case of SiC MOSFET, Vth rapidly increases after PHEF stress. After 900 s PHEF stress, the average variation of Vth exceeded 100%. Moreover, the average variation of Vth was 166% when PHEF stress was finished. Consequently, under PHEF stress, the SiC MOSFET's Vth variation is more significant than Si-based devices. The Vth increment in SiC MOSFET indicates that Qit occurs relatively more than Qot. A small level change in Vth without a noticeable increase or decrease trend can be regarded as a measurement error by the experimental equipment. Therefore, the Vth change of Si IGBT and Si MOSFET in Figure 7 can be considered as the measurement error. On the other hand, since Si IGBT with SiC diode and SiC MOSFET has a marked increase in Vth, even though considering the measurement error, Vth variations in Si IGBT with SiC diode and SiC MOSFET can be referred to as a permanent shift in Vth. Figure 8 shows Vth variations in NHEF stress according to the types of the switching device. As demonstrated from Figure 8a, in the case of Si IGBT, there were few changes in Vth after NHEF stress. The average Vth variations of Si MOSFET and Si IGBT with SiC diode after 3600 s NHEF stress were −0.6% and −0.4%, respectively. For SiC MOSFET, the amount of Vth reduction was more significant than that of other types of switching de- A small level change in V th without a noticeable increase or decrease trend can be regarded as a measurement error by the experimental equipment. Therefore, the V th change of Si IGBT and Si MOSFET in Figure 7 can be considered as the measurement error. On the other hand, since Si IGBT with SiC diode and SiC MOSFET has a marked increase in V th , even though considering the measurement error, V th variations in Si IGBT with SiC diode and SiC MOSFET can be referred to as a permanent shift in V th . Figure 8 shows V th variations in NHEF stress according to the types of the switching device. As demonstrated from Figure 8a, in the case of Si IGBT, there were few changes in V th after NHEF stress. The average V th variations of Si MOSFET and Si IGBT with SiC diode after 3600 s NHEF stress were −0.6% and −0.4%, respectively. For SiC MOSFET, the amount of V th reduction was more significant than that of other types of switching devices. When the NHEP stress time was 900 s, averagely, V th decreased by about 51% compared to the initial value, and when the stress was finished, V th decreased by about 69%. The V th reduction in SiC MOSFET means that Q ot occurs more than Q it .

Threshold Voltage Variation under HEF Stress
vices. When the NHEP stress time was 900 s, averagely, Vth decreased by about 51% compared to the initial value, and when the stress was finished, Vth decreased by about 69%. The Vth reduction in SiC MOSFET means that Qot occurs more than Qit.  Figure 8 indicates that, in NHEF stress, SiC MOSFET experiences considerable Vth reduction. This means that SiC MOSFETs have a greater risk of being switched on when they should be switched off than other types of switching devices. Therefore, SiC MOSFETs are more vulnerable to NHEF stress than Si-based devices. Figure 9 shows the changes of Ron in PHEF stress according to the switching device. For Si IGBT, shown in Figure 9a, Ron increased by about 1.3% compared to the initial value when the stress was finished. Furthermore, as shown in Figure 9b, the average Ron variation of Si MOSFET was about 0.3% after PHEF stress. For Si IGBT with SiC diode depicted in Figure 9c, four out of five DUTs showed little change, but 3-Ron-P-1 had a reduction tendency of Ron. From this, it can be seen that in the case of the Si-based device, the change in Ron according to PHEF stress is not significant. However, Ron of SiC MOSFET increased rapidly as PHEF stress progressed, as shown in Figure 9d. After the first 900 s of the stress, Ron increased by about 55% on average, and at the end of the stress, Ron rose to about 100% compared to the initial value. As shown in Figure 7d, Vth of SiC MOSFET in PHEF stress rose, resulting in the reduction of Vover in (3). As explained earlier, Ron of SiC MOSFET is greatly affected by Rch. Therefore, due to the decrement of Vover, Ron rose. Similar to the Vth trends in Figure 7, the rate of change of SiC MOSFET was the largest in Ron. These results indicate that the SiC MOSFET's conduction loss can be larger than other Si-based devices in the positive gate oxide degradation that raises Vth.  Figure 8 indicates that, in NHEF stress, SiC MOSFET experiences considerable V th reduction. This means that SiC MOSFETs have a greater risk of being switched on when they should be switched off than other types of switching devices. Therefore, SiC MOSFETs are more vulnerable to NHEF stress than Si-based devices. Figure 9 shows the changes of R on in PHEF stress according to the switching device. For Si IGBT, shown in Figure 9a, R on increased by about 1.3% compared to the initial value when the stress was finished. Furthermore, as shown in Figure 9b, the average R on variation of Si MOSFET was about 0.3% after PHEF stress. For Si IGBT with SiC diode depicted in Figure 9c, four out of five DUTs showed little change, but 3-Ron-P-1 had a reduction tendency of R on . From this, it can be seen that in the case of the Si-based device, the change in R on according to PHEF stress is not significant. However, R on of SiC MOSFET increased rapidly as PHEF stress progressed, as shown in Figure 9d. After the first 900 s of the stress, R on increased by about 55% on average, and at the end of the stress, R on rose to about 100% compared to the initial value. As shown in Figure 7d, V th of SiC MOSFET in PHEF stress rose, resulting in the reduction of V over in (3). As explained earlier, R on of SiC MOSFET is greatly affected by R ch . Therefore, due to the decrement of V over , R on rose. Similar to the V th trends in Figure 7, the rate of change of SiC MOSFET was the largest in R on . These results indicate that the SiC MOSFET's conduction loss can be larger than other Si-based devices in the positive gate oxide degradation that raises V th . Figure 10 shows the changes of R on in NHEF stress according to the switching device. Figure 10a-c describe that R on of Si IGBT, Si MOSFET, and Si IGBT with SiC diode had no trend according to NHEF stress. R on of Si IGBT had the variation within about 6% depending on the stress. In the case of Si MOSFET, a device with an increase in R on , a device with a decrease in R on , and a device with few changes in R on appear. R on of Si IGBT (hybrid) had the slightest change according to NHEF stress. Meanwhile, Figure 10d demonstrates that SiC MOSFETs had a reduction trend of R on according to NHEF stress. At the end of the stress, the variation in R on of 4-Ron-N-1 was about −6%, and the variation in R on of 4-Ron-N-5 was about 18%.      The R on reduction of SiC MOSFET in the NHEF stress can be explained by the V th change. As shown in Figure 8d, V th of SiC MOSFET decreases in NHEF stress. This V th reduction raises V over in (3). As a result, R on decreases. Figure 11 represents a double pulse test circuit (DPTC) used to measure T don and T doff . Figure 11 shows the DPTC used to measure the T don and T doff of the switching devices. A gate driver named SKHI22BR was used in this paper. The gate driver driving pulse in the DPTC was generated through a digital signal processor (DSP). The DSP used in this paper is TI TMS320F28335. Furthermore, UP-3005T was used for DC supply. Figure 11a is the circuit diagram for measuring T don and T doff . DUT is located at the bottom, as shown in Figure 11a. A large gate driver resistor was used to easily observe T don and T doff characteristics [17,21]. The gate driver resistor R g for T don and T doff is 485 Ω. The Ron reduction of SiC MOSFET in the NHEF stress can be explained by the Vth change. As shown in Figure 8d, Vth of SiC MOSFET decreases in NHEF stress. This Vth reduction raises Vover in (3). As a result, Ron decreases. Figure 11 represents a double pulse test circuit (DPTC) used to measure Tdon and Tdoff. Figure 11 shows the DPTC used to measure the Tdon and Tdoff of the switching devices. A gate driver named SKHI22BR was used in this paper. The gate driver driving pulse in the DPTC was generated through a digital signal processor (DSP). The DSP used in this paper is TI TMS320F28335. Furthermore, UP-3005T was used for DC supply. Figure 11a is the circuit diagram for measuring Tdon and Tdoff. DUT is located at the bottom, as shown in Figure 11a. A large gate driver resistor was used to easily observe Tdon and Tdoff characteristics [17,21]. The gate driver resistor Rg for Tdon and Tdoff is 485 Ω.  Figure 12 shows some of the results of the Tdon experiment in PHEF stress. Tdon in the fresh state and Tdon after 3600 s of PHEF stress are displayed together. As shown in Figure  12, in the case of Si-based devices, the difference between before and after PHEF stress is not observed. However, as demonstrated from Figure 12d, Tdon of 4-Tdon-P-4, which is SiC MOSFET before the stress was about 232 ns, but Tdon measured after the stress was about 414.4 ns. Therefore, the Tdon of 4-Tdon-P-4 had an increase of about 79% compared to the initial value. A change in Tdon can be explained by Vth variation. As shown in Figure  12, the Vth of Si-based devices hardly changed after PHEF stress. However, in the case of SiC MOSFET, Vth grew significantly after PHEF stress. Therefore, the rise of Vth raised Tdon.  Figure 12 shows some of the results of the T don experiment in PHEF stress. T don in the fresh state and T don after 3600 s of PHEF stress are displayed together. As shown in Figure 12, in the case of Si-based devices, the difference between before and after PHEF stress is not observed. However, as demonstrated from Figure 12d, T don of 4-Tdon-P-4, which is SiC MOSFET before the stress was about 232 ns, but T don measured after the stress was about 414.4 ns. Therefore, the T don of 4-Tdon-P-4 had an increase of about 79% compared to the initial value. A change in T don can be explained by V th variation. As shown in Figure 12, the V th of Si-based devices hardly changed after PHEF stress. However, in the case of SiC MOSFET, V th grew significantly after PHEF stress. Therefore, the rise of V th raised T don .   Figure 13 shows all of the results of the Tdon experiment in PHEF stress according to the type of the switching device. Figure 13a-c indicate that there is no significant increase or decrease in Tdon according to PHEF stress for Si-based devices. However, in the case of SiC MOSFETs, an increasing trend of Tdonwas observed in PHEF stress, similar to Vth in Figure 7d. At 900 s of PHEF stress, Tdon rose sharply and continued to increase. In particular, 4-Tdon-P-4 had a very large variation of about 80% in Tdon compared to the fresh condition after 3600 s of PHEF stress. Other SiC MOSFETs increased by 40% to 50% compared to the initial value. Based on Figures 12 and 13, it can be seen that SiC MOSFETs have a more considerable Tdon increment during PHEF stress compared to Si-based devices.  Figure 13 shows all of the results of the T don experiment in PHEF stress according to the type of the switching device. Figure 13a-c indicate that there is no significant increase or decrease in T don according to PHEF stress for Si-based devices. However, in the case of SiC MOSFETs, an increasing trend of T don was observed in PHEF stress, similar to V th in Figure 7d. At 900 s of PHEF stress, T don rose sharply and continued to increase. In particular, 4-Tdon-P-4 had a very large variation of about 80% in T don compared to the fresh condition after 3600 s of PHEF stress. Other SiC MOSFETs increased by 40% to 50% compared to the initial value. Based on Figures 12 and 13, it can be seen that SiC MOSFETs have a more considerable T don increment during PHEF stress compared to Si-based devices.  Figure 13 shows all of the results of the Tdon experiment in PHEF stress according to the type of the switching device. Figure 13a-c indicate that there is no significant increase or decrease in Tdon according to PHEF stress for Si-based devices. However, in the case of SiC MOSFETs, an increasing trend of Tdonwas observed in PHEF stress, similar to Vth in Figure 7d. At 900 s of PHEF stress, Tdon rose sharply and continued to increase. In particular, 4-Tdon-P-4 had a very large variation of about 80% in Tdon compared to the fresh condition after 3600 s of PHEF stress. Other SiC MOSFETs increased by 40% to 50% compared to the initial value. Based on Figures 12 and 13, it can be seen that SiC MOSFETs have a more considerable Tdon increment during PHEF stress compared to Si-based devices.   Figure  14 shows that no significant change in Tdon was observed for Si-based devices under NHEF stress. However, the Tdon of 4-Tdon-N-2 was reduced after NHEF stress. Tdonof 4-Tdon-N-2 in the fresh condition was 293.6 ns. Moreover, 4-Tdon-N-2 after NHEF stress   Figure 14 shows that no significant change in T don was observed for Si-based devices under NHEF stress. However, the T don of 4-Tdon-N-2 was reduced after NHEF stress. T don of 4-Tdon-N-2 in the fresh condition was 293.6 ns. Moreover, 4-Tdon-N-2 after NHEF stress was 248 ns. Therefore, the T don variation of 4-Tdon-N-2 was −16%. This change is opposite to the trend in the PHEF stress of SiC MOSFET. T don of 4-Tdon-N-2, a SiC MOSFET, was reduced because V th decreased after NHEF stress.

Turn-On Delay Variation under HEF Stress
(c) (d)  Figure  14 shows that no significant change in Tdon was observed for Si-based devices under NHEF stress. However, the Tdon of 4-Tdon-N-2 was reduced after NHEF stress. Tdonof 4-Tdon-N-2 in the fresh condition was 293.6 ns. Moreover, 4-Tdon-N-2 after NHEF stress was 248 ns. Therefore, the Tdon variation of 4-Tdon-N-2 was −16%. This change is opposite to the trend in the PHEF stress of SiC MOSFET. Tdon of 4-Tdon-N-2, a SiC MOSFET, was reduced because Vth decreased after NHEF stress.  Figure 15 shows all the results of the Tdon experiment in NHEF stress. Figure 15a-c describe that there was no significant change in Tdon of Si IGBT, Si MOSFET, and Si IGBT with SiC diode under NHEF stress. However, in SiC MOSET, Figure 15d shows that Tdon decreased as the NHEF stress progressed. After 3600 s of NHEF stress, the average Tdon of the five SiC MOSFETs decreased by about 13% compared to the initial value. The Tdon of  Figure 15 shows all the results of the T don experiment in NHEF stress. Figure 15a-c describe that there was no significant change in T don of Si IGBT, Si MOSFET, and Si IGBT with SiC diode under NHEF stress. However, in SiC MOSET, Figure 15d shows that T don decreased as the NHEF stress progressed. After 3600 s of NHEF stress, the average T don of the five SiC MOSFETs decreased by about 13% compared to the initial value. The T don of SiC MOSFET decreases with the NHEF stress due to the reduction of V th . As shown in Figure 2, T don is reduced as V th decreases. Figure 8d shows that V th of SiC MOSFET decreased after NHEF stress. Therefore, the T don of SiC MOSFET is reduced under NHEF stress.

1-Tdon
(c) (d) Figure 14. Turn on waveforms in NHEF stress: (a) 1-Tdon-P-1, (b) 2-Tdon-P-2, (c) 3-Tdon-P-1, and (d) 4-Tdon-P-4. Figure 15 shows all the results of the Tdon experiment in NHEF stress. Figure 15a-c describe that there was no significant change in Tdon of Si IGBT, Si MOSFET, and Si IGBT with SiC diode under NHEF stress. However, in SiC MOSET, Figure 15d shows that Tdon decreased as the NHEF stress progressed. After 3600 s of NHEF stress, the average Tdon of the five SiC MOSFETs decreased by about 13% compared to the initial value. The Tdon of SiC MOSFET decreases with the NHEF stress due to the reduction of Vth. As shown in Figure 2, Tdon is reduced as Vth decreases. Figure 8d shows that Vth of SiC MOSFET decreased after NHEF stress. Therefore, the Tdon of SiC MOSFET is reduced under NHEF stress.  Figure 16 shows some of the results of the Tdoff experiment in PHEF stress. As shown in Figure 16, in the case of 1-Tdoff-P-1, 2-Tdoff-P-2, and 3-Tdoff-P-1, the difference between before and after PHEF stress was not clear. However, Tdoff of 4-Tdoff-P-4, as shown in Figure 16d, decreased sharply after PHEF stress. The Tdoff variation of 4-Tdoff-P-4 was −42%. This reduction in Tdoff can be explained by a change in Vm. Looking at the change in  Figure 16 shows some of the results of the T doff experiment in PHEF stress. As shown in Figure 16, in the case of 1-Tdoff-P-1, 2-Tdoff-P-2, and 3-Tdoff-P-1, the difference between before and after PHEF stress was not clear. However, T doff of 4-Tdoff-P-4, as shown in Figure 16d, decreased sharply after PHEF stress. The T doff variation of 4-Tdoff-P-4 was −42%. This reduction in T doff can be explained by a change in V m . Looking at the change in V m before and after PHEF stress shown in Figure 16d, it can be seen that V m increased after PHEF stress. Therefore, the T doff of the SiC MOSFET, 4-Tdoff-P-4, is reduced. Vm before and after PHEF stress shown in Figure 16d, it can be seen that Vm increased after PHEF stress. Therefore, the Tdoff of the SiC MOSFET, 4-Tdoff-P-4, is reduced.

3-Tdoff-P-1 4-Tdoff-P-4
(c) (d)   Figure 7d, Vth increases. In addition, Equation (7) indicates that when Vth increases, Vm also increases.   Figure 7d, V th increases. In addition, Equation (7) indicates that when V th increases, V m also increases. The rise of V m decreases T doff , as illustrated in Figure 3. Therefore, under PHEF stress, the T doff of SiC MOSFET is reduced, as shown in Figure 17d. Consequently, the T doff of SiC MOSFET is significantly reduced under PHEF stress compared to other Si-based devices. Figure 18 is some of the results of the T doff experiment in NHEF stress. Figure 18a-c indicate that Si-based devices did not have much change in T doff in NHEF stress. However, T doff of 4-Tdoff-P-4 had a noticeable difference. T doff of 4-Tdoff-P-4 in the fresh condition was 452.0 ns. Moreover, the T doff of 4-Tdoff-P-4 after 3600 s of PHEF stress was 560.8 ns. Therefore, the T doff variation of 4-Tdoff-P-4 was 24%. Figure 18d demonstrates that V m decreased after NHEF stress. As shown in Figure 3, decreasing V m raises T doff . Therefore, the T doff of 4-Tdoff-P-4 increased.
The rise of Vm decreases Tdoff, as illustrated in Figure 3. Therefore, under PHEF stress, the Tdoff of SiC MOSFET is reduced, as shown in Figure 17d. Consequently, the Tdoff of SiC MOSFET is significantly reduced under PHEF stress compared to other Si-based devices. Figure 18 is some of the results of the Tdoff experiment in NHEF stress. Figure 18a-c indicate that Si-based devices did not have much change in Tdoff in NHEF stress. However, Tdoff of 4-Tdoff-P-4 had a noticeable difference. Tdoff of 4-Tdoff-P-4 in the fresh condition was 452.0 ns. Moreover, the Tdoff of 4-Tdoff-P-4 after 3600 s of PHEF stress was 560.8 ns. Therefore, the Tdoff variation of 4-Tdoff-P-4 was 24%. Figure 18d demonstrates that Vm decreased after NHEF stress. As shown in Figure 3, decreasing Vm raises Tdoff. Therefore, the Tdoff of 4-Tdoff-P-4 increased. The rise of Vm decreases Tdoff, as illustrated in Figure 3. Therefore, under PHEF stress, the Tdoff of SiC MOSFET is reduced, as shown in Figure 17d. Consequently, the Tdoff of SiC MOSFET is significantly reduced under PHEF stress compared to other Si-based devices. Figure 18 is some of the results of the Tdoff experiment in NHEF stress. Figure 18a-c indicate that Si-based devices did not have much change in Tdoff in NHEF stress. However, Tdoff of 4-Tdoff-P-4 had a noticeable difference. Tdoff of 4-Tdoff-P-4 in the fresh condition was 452.0 ns. Moreover, the Tdoff of 4-Tdoff-P-4 after 3600 s of PHEF stress was 560.8 ns. Therefore, the Tdoff variation of 4-Tdoff-P-4 was 24%. Figure 18d demonstrates that Vm decreased after NHEF stress. As shown in Figure 3, decreasing Vm raises Tdoff. Therefore, the Tdoff of 4-Tdoff-P-4 increased.

3-Tdoff-N-1 4-Tdoff-N-2
(c) (d)  Figure 19 represents all the results of the Tdoff experiment in NHEF stress. For Si-based devices, no clear trend was observed in NHEF stress. However, as shown in Figure 19d, the Tdoff of SiC MOSFETs increased as the NHEF stress continued. The average Tdoff of SiC MOSFETs after 3600 s of PHEF stress was 24%. In particular, 4-Tdoff-N-3 showed a significant change as Tdoff increased by about 33% compared to the initial value. It was mentioned in the previous discussion that the decrement of Vth raises Tdoff. Figure 8d demonstrates that Vth decreases with NHEF stress. Therefore, Tdoff rises in NHEF stress. Table 3 summarizes changes in Vth, Ron, Tdon, and Tdoff under HEF stress according to switch types. The values in Table 3 are results obtained after 3600 s of HEF stress. Table 3 demonstrates that Vth, Ron, Tdon, and Tdoff variations of SiC MOSFET are larger than those of Si-based devices.  Figure 19 represents all the results of the T doff experiment in NHEF stress. For Si-based devices, no clear trend was observed in NHEF stress. However, as shown in Figure 19d, the T doff of SiC MOSFETs increased as the NHEF stress continued. The average T doff of SiC MOSFETs after 3600 s of PHEF stress was 24%. In particular, 4-Tdoff-N-3 showed a significant change as T doff increased by about 33% compared to the initial value. It was mentioned in the previous discussion that the decrement of V th raises T doff . Figure 8d demonstrates that V th decreases with NHEF stress. Therefore, T doff rises in NHEF stress. Table 3 summarizes changes in V th , R on , T don , and T doff under HEF stress according to switch types. The values in Table 3 are results obtained after 3600 s of HEF stress. Table 3 demonstrates that V th , R on , T don , and T doff variations of SiC MOSFET are larger than those of Si-based devices.  Figure 19 represents all the results of the Tdoff experiment in NHEF stress. For Si-based devices, no clear trend was observed in NHEF stress. However, as shown in Figure 19d, the Tdoff of SiC MOSFETs increased as the NHEF stress continued. The average Tdoff of SiC MOSFETs after 3600 s of PHEF stress was 24%. In particular, 4-Tdoff-N-3 showed a significant change as Tdoff increased by about 33% compared to the initial value. It was mentioned in the previous discussion that the decrement of Vth raises Tdoff. Figure  8d demonstrates that Vth decreases with NHEF stress. Therefore, Tdoff rises in NHEF stress. Table 3 summarizes changes in Vth, Ron, Tdon, and Tdoff under HEF stress according to switch types. The values in Table 3 are results obtained after 3600 s of HEF stress. Table 3 demonstrates that Vth, Ron, Tdon, and Tdoff variations of SiC MOSFET are larger than those of Si-based devices.

Performance of Voltage and Current Source Inverter with Duty Error Changes
The previous experimental results demonstrate that Tdon and Tdoff change after HEF stress. In other words, it means that the duty error of the converter changes as the gate oxide degradation progresses. This section analyzes the effects of duty error change according to HEF stress on the performance of voltage source and current source inverter. In the characteristic analysis according to HEF stress, a large gate resistance was used to sensitively observe changes in Tdon and Tdoff. Tdon and Tdoff of SiC MOSFET using a practical gate resistance of 15 Ω are shown in Figure 20.  Figure 20 shows the turn-on and turn-off waveforms when Rg is 15 Ω. As shown in Figure 20, a smaller Rg results in shorter Tdon and Tdoff because Vgs changes faster. However, since Vth, which is a parameter that determines Tdon and Tdoff, is the same regardless of Rg, the ratio of the change in Tdon and Tdoff according to Vth variation is similar even if Rg is different. Therefore, the rate of change of Tdon and Tdoff according to the HEF stress time obtained in this paper is applicable even when Rg is 15 Ω. As shown in Figure 20, when Rgis 15 Ω, Tdon is 56 ns, and Tdoff is 64 ns. In order to calculate the change of duty error ac-

Performance of Voltage and Current Source Inverter with Duty Error Changes
The previous experimental results demonstrate that T don and T doff change after HEF stress. In other words, it means that the duty error of the converter changes as the gate oxide degradation progresses. This section analyzes the effects of duty error change according to HEF stress on the performance of voltage source and current source inverter. In the characteristic analysis according to HEF stress, a large gate resistance was used to sensitively observe changes in T don and T doff . T don and T doff of SiC MOSFET using a practical gate resistance of 15 Ω are shown in Figure 20.

Performance of Voltage and Current Source Inverter with Duty Error Changes
The previous experimental results demonstrate that Tdon and Tdoff change after HEF stress. In other words, it means that the duty error of the converter changes as the gate oxide degradation progresses. This section analyzes the effects of duty error change according to HEF stress on the performance of voltage source and current source inverter. In the characteristic analysis according to HEF stress, a large gate resistance was used to sensitively observe changes in Tdon and Tdoff. Tdon and Tdoff of SiC MOSFET using a practical gate resistance of 15 Ω are shown in Figure 20.  Figure 20 shows the turn-on and turn-off waveforms when Rg is 15 Ω. As shown in Figure 20, a smaller Rg results in shorter Tdon and Tdoff because Vgs changes faster. However, since Vth, which is a parameter that determines Tdon and Tdoff, is the same regardless of Rg, the ratio of the change in Tdon and Tdoff according to Vth variation is similar even if Rg is different. Therefore, the rate of change of Tdon and Tdoff according to the HEF stress time obtained in this paper is applicable even when Rg is 15 Ω. As shown in Figure 20, when Rgis 15 Ω, Tdon is 56 ns, and Tdoff is 64 ns. In order to calculate the change of duty error ac-  Figure 20 shows the turn-on and turn-off waveforms when R g is 15 Ω. As shown in Figure 20, a smaller R g results in shorter T don and T doff because V gs changes faster. However, since V th , which is a parameter that determines T don and T doff , is the same regardless of R g , the ratio of the change in T don and T doff according to V th variation is similar even if R g is different. Therefore, the rate of change of T don and T doff according to the HEF stress time obtained in this paper is applicable even when R g is 15 Ω. As shown in Figure 20, when R g is 15 Ω, T don is 56 ns, and T doff is 64 ns. In order to calculate the change of duty error according to the HEF stress time, it is necessary to know the rate of change of T don and T doff according to the stress time. As shown in Figures 13d, 15d, 17d and 19d, T don, and T doff in each condition were obtained using five devices. Using the average value of the five devices, the rate of change of T don and T doff in PHEF and NHEF stress can be calculated. Figure 21 shows the rate of change of T don and T doff obtained by average values of results in Figures 13d, 15d, 17d and 19d. In Figure 21, Rate don represents the change rate of T don according to stress time, and Rate doff means the change rate of T doff according to stress time.
Machines 2022, 10, x FOR PEER REVIEW 19 of 30 cording to the HEF stress time, it is necessary to know the rate of change of Tdon and Tdoff according to the stress time. As shown in Figures 13d, 15d, 17d and 19d, Tdon, and Tdoff in each condition were obtained using five devices. Using the average value of the five devices, the rate of change of Tdon and Tdoff in PHEF and NHEF stress can be calculated. Figure 21 shows the rate of change of Tdon and Tdoff obtained by average values of results in Figures 13d, 15d, 17d and 19d. In Figure 21, Ratedon represents the change rate of Tdon according to stress time, and Ratedoff means the change rate of Tdoff according to stress time.

Performance Variation of Grid-connected Voltage Source Inverter with Duty Error Change due to Gate Oxide Degradation
This section examines the performance variation of the grid-connected voltage source inverter according to the duty error change due to the gate oxide degradation. Figure 22 shows a typical grid-connected voltage source inverter. In general, a grid-connected voltage source inverter is controlled with a current alone or a current and power simultaneously [23]. Figure 22 shows a grid-connected voltage source inverter with both current and power controls. In Figure 22, Sv1, Sv2, Sv3, Sv4, Sv5, and Sv6 mean the switches of the voltage source inverter. In addition, Vdc is the

Performance Variation of Grid-Connected Voltage Source Inverter with Duty Error Change Due to Gate Oxide Degradation
This section examines the performance variation of the grid-connected voltage source inverter according to the duty error change due to the gate oxide degradation. Figure 22 shows a typical grid-connected voltage source inverter.
Machines 2022, 10, x FOR PEER REVIEW 19 of 30 cording to the HEF stress time, it is necessary to know the rate of change of Tdon and Tdoff according to the stress time. As shown in Figures 13d, 15d, 17d and 19d, Tdon, and Tdoff in each condition were obtained using five devices. Using the average value of the five devices, the rate of change of Tdon and Tdoff in PHEF and NHEF stress can be calculated. Figure 21 shows the rate of change of Tdon and Tdoff obtained by average values of results in Figures 13d, 15d, 17d and 19d. In Figure 21, Ratedon represents the change rate of Tdon according to stress time, and Ratedoff means the change rate of Tdoff according to stress time.

Performance Variation of Grid-connected Voltage Source Inverter with Duty Error Change due to Gate Oxide Degradation
This section examines the performance variation of the grid-connected voltage source inverter according to the duty error change due to the gate oxide degradation. Figure 22 shows a typical grid-connected voltage source inverter. In general, a grid-connected voltage source inverter is controlled with a current alone or a current and power simultaneously [23]. Figure 22 shows a grid-connected voltage source inverter with both current and power controls. In Figure 22, Sv1, Sv2, Sv3 Figure 22. Grid-connected voltage source inverter.
In general, a grid-connected voltage source inverter is controlled with a current alone or a current and power simultaneously [23]. Figure 22 shows a grid-connected voltage source inverter with both current and power controls. In Figure 22, S v1 , S v2 , S v3 , S v4 , S v5 , and S v6 mean the switches of the voltage source inverter. In addition, V dc is the inverter input voltage, and C dc is the inverter input capacitor. R l and L l are line resistance and line inductance, respectively. Moreover, L f and C f mean the inductance and capacitance of the LC filter of the inverter output, respectively. V g indicates the grid voltage, and i g represents the grid current. The voltage source inverter in Figure 22 simultaneously controls the grid current and instantaneous power. For the inverter control, first, the three-phase grid voltage and grid current are converted using abc to αβ transformation. The abc to αβ transformation is as (12). In (12), i ga , i gb , and i gb are a-phase, b-phase, and c-phase grid current, respectively. Moreover, v ga , v gb , and v gb are a-phase, b-phase, and c-phase grid voltages, respectively: Using the α and β values of the three-phase grid voltage and current converted by (12), the instantaneous active power (P) and reactive power (Q) are calculated as in (13): The instantaneous reactive power must be controlled to zero for the unity power factor control. Therefore, the reference of the instantaneous reactive power, denoted by Q * , is set to zero. Moreover, the reference of the instantaneous active power is applied as a desired value. In Figure 22, P * means the reference of the instantaneous active power. The instantaneous power calculated by (13) and its reference value are inputs to the PI controller for the power control. Figure 23 shows the PI controller for the power control. The PI controller for the active power control generates an output value by amplifying and integrating the difference between P* and P, as shown in Figure 23. The output value of the active power becomes i * gd . Similarly, for the reactive power control, the output value, i * gq , is generated by amplifying and integrating the difference between Q* and Q. i * gd and i * gq mean the reference value of the d and q value of the grid current. K pp , K ip , K pq , and K iq in Figure 23 represent coefficients used in the PI controller for the power control. inverter input voltage, and Cdc is the inverter input capacitor. Rl and Ll are line resistance and line inductance, respectively. Moreover, Lf and Cf mean the inductance and capacitance of the LC filter of the inverter output, respectively. Vg indicates the grid voltage, and ig represents the grid current. The voltage source inverter in Figure 22 simultaneously controls the grid current and instantaneous power. For the inverter control, first, the three-phase grid voltage and grid current are converted using abc to αβ transformation. The abc to αβ transformation is as (12). In (12), iga, igb, and igb are a-phase, b-phase, and c-phase grid current, respectively. Moreover, vga, vgb, and vgb are a-phase, b-phase, and c-phase grid voltages, respectively: Using the α and β values of the three-phase grid voltage and current converted by (12), the instantaneous active power (P) and reactive power (Q) are calculated as in (13): The instantaneous reactive power must be controlled to zero for the unity power factor control. Therefore, the reference of the instantaneous reactive power, denoted by Q * , is set to zero. Moreover, the reference of the instantaneous active power is applied as a desired value. In Figure 22, P * means the reference of the instantaneous active power. The instantaneous power calculated by (13) and its reference value are inputs to the PI controller for the power control. Figure 23 shows the PI controller for the power control. The PI controller for the active power control generates an output value by amplifying and integrating the difference between P* and P, as shown in Figure 23. The output value of the active power becomes * . Similarly, for the reactive power control, the output value, * , is generated by amplifying and integrating the difference between Q* and Q. * and * mean the reference value of the d and q value of the grid current. Kpp, Kip, Kpq, and Kiq in Figure 23 represent coefficients used in the PI controller for the power control. Meanwhile, for the grid current control, the d and q values of the grid current are required. By (14), the d and q values of the grid current are obtained: In (14), θ is the phase of the grid voltage and is calculated through a phase-locked loop (PLL). The grid current reference values, which are the output of the PI controller for the power control, and the d and q values of the grid current from (14) are applied as the inputs of the PI controller for the grid current control. Meanwhile, for the grid current control, the d and q values of the grid current are required. By (14), the d and q values of the grid current are obtained: In (14), θ is the phase of the grid voltage and is calculated through a phase-locked loop (PLL). The grid current reference values, which are the output of the PI controller for the power control, and the d and q values of the grid current from (14) are applied as the inputs of the PI controller for the grid current control. Figure 24 shows the PI controller for the grid current control. As shown in Figure 24, to control the d value of the grid current, the output of the PI controller is generated by amplifying and integrating the difference between the reference value and the actual value of i gd . The output of the PI controller controlling i gd is v * d , which is the d value of the voltage source inverter control signal. Similarly, to control the q value of the grid current, the output v * q is generated by amplifying and integrating the difference between the reference value and the actual value of i gq . v * q means the q value of the voltage source inverter control signal. The reference values of i gd and i gq , which are expressed as i * gd and i * gq are the output of the PI controller for the power control, shown in Figure 23. K pgd , K igd , K pgq , and K igq in Figure 24 mean coefficients used in the PI controller for the grid current control.
Machines 2022, 10, x FOR PEER REVIEW 21 of 30 Figure 24 shows the PI controller for the grid current control. As shown in Figure 24, to control the d value of the grid current, the output of the PI controller is generated by amplifying and integrating the difference between the reference value and the actual value of igd. The output of the PI controller controlling igd is * , which is the d value of the voltage source inverter control signal. Similarly, to control the q value of the grid current, the output * is generated by amplifying and integrating the difference between the reference value and the actual value of igq. * means the q value of the voltage source inverter control signal. The reference values of igd and igq, which are expressed as * and * are the output of the PI controller for the power control, shown in Figure 23. Kpgd, Kigd, Kpgq, and Kigq in Figure 24 mean coefficients used in the PI controller for the grid current control. * and * undergoes dq to αβ conversion and αβ to abc conversion, resulting in * , * , and * .The switching signals of the voltage source inverter are generated using space vector modulation [24]. The space vector modulation is implemented using an offset voltage, as shown in Figure 25 [25].   Figure 25 shows the space vector modulation using the offset voltage. * , * , and * in Figure 25 are the inverter control signal of a-phase, b-phase, and c-phase, respectively. * , * , and * are obtained from dq to αβ conversion and αβ to abc conversion of * and * . The offset voltage is calculated as follows (15): In (15), voff means the offset voltage for the space vector modulation. Moreover, the largest of * , * , and * becomes Vmax and the smallest becomes Vmin. Switching signals are generated by comparing the carrier with the values obtained by adding the offset voltage to * , * , and * . Note that the switching frequency of the inverter is determined by the frequency of the carrier. In the voltage source inverter, the switches of one leg operate complementarily. Since a huge current can flow at the moment when all the switches of one leg of the voltage source inverter are on, the dead-time is set to make all switches of one leg be off when the switching state changes. In addition, the duty of the v * d and v * q undergoes dq to αβ conversion and αβ to abc conversion, resulting in v * a , v * b , and v * c .The switching signals of the voltage source inverter are generated using space vector modulation [24]. The space vector modulation is implemented using an offset voltage, as shown in Figure 25 [25].
Machines 2022, 10, x FOR PEER REVIEW 21 of 30 Figure 24 shows the PI controller for the grid current control. As shown in Figure 24, to control the d value of the grid current, the output of the PI controller is generated by amplifying and integrating the difference between the reference value and the actual value of igd. The output of the PI controller controlling igd is * , which is the d value of the voltage source inverter control signal. Similarly, to control the q value of the grid current, the output * is generated by amplifying and integrating the difference between the reference value and the actual value of igq. * means the q value of the voltage source inverter control signal. The reference values of igd and igq, which are expressed as * and * are the output of the PI controller for the power control, shown in Figure 23. Kpgd, Kigd, Kpgq, and Kigq in Figure 24 mean coefficients used in the PI controller for the grid current control. * and * undergoes dq to αβ conversion and αβ to abc conversion, resulting in * , * , and * .The switching signals of the voltage source inverter are generated using space vector modulation [24]. The space vector modulation is implemented using an offset voltage, as shown in Figure 25 [25].   Figure 25 shows the space vector modulation using the offset voltage. * , * , and * in Figure 25 are the inverter control signal of a-phase, b-phase, and c-phase, respectively. * , * , and * are obtained from dq to αβ conversion and αβ to abc conversion of * and * . The offset voltage is calculated as follows (15): In (15), voff means the offset voltage for the space vector modulation. Moreover, the largest of * , * , and * becomes Vmax and the smallest becomes Vmin. Switching signals are generated by comparing the carrier with the values obtained by adding the offset voltage to * , * , and * . Note that the switching frequency of the inverter is determined by the frequency of the carrier. In the voltage source inverter, the switches of one leg operate complementarily. Since a huge current can flow at the moment when all the switches of one leg of the voltage source inverter are on, the dead-time is set to make all switches of one leg be off when the switching state changes. In addition, the duty of the  Figure 25 shows the space vector modulation using the offset voltage. v * a , v * b , and v * c in Figure 25 are the inverter control signal of a-phase, b-phase, and c-phase, respectively.v * a , v * b , and v * c are obtained from dq to αβ conversion and αβ to abc conversion of v * d and v * q . The offset voltage is calculated as follows (15): In (15), v off means the offset voltage for the space vector modulation. Moreover, the largest of v * a , v * b , and v * c becomes V max and the smallest becomes V min . Switching signals are generated by comparing the carrier with the values obtained by adding the offset voltage to v * a , v * b , and v * c . Note that the switching frequency of the inverter is determined by the frequency of the carrier. In the voltage source inverter, the switches of one leg operate complementarily. Since a huge current can flow at the moment when all the switches of one leg of the voltage source inverter are on, the dead-time is set to make all switches of one leg be off when the switching state changes. In addition, the duty of the switch is changed by T don and T doff . Figure 26 shows gating signals and the a-phase pole voltage considering the dead time, T don , and T doff of S v1 and S v4 which are the a-phase switches of the grid-connected voltage source inverter in Figure 22.  Figure 26a,b show the current path according to the pole current direction. Figure 26a,b demonstrate that the dwell time of VaN changes, as shown in Figure 26c, because the path through which the current flows varies according to the sign of the pole current [26]. Equation (16) represents Tactp/f and Tactn/f: / = − − / + / , Equation (16) becomes as (17) when aging is considered: Tdon/a and Tdoff/ain (17) can be calculated through (18):  In Figure 26, T d means the dead time. Furthermore, V aN is the a-phase pole voltage. T r is the ideal dwelling time of V aN . T actp/f is the dwelling time of V aN considering T d , T don , and T doff when the switching devices are fresh and the pole current (i) is positive. In addition, T actn/f is the dwelling time of V aN considering T d , T don , and T doff when the switching devices are fresh and the pole current is negative. T don/a and T doff/a denote turn-on delay and turn-off delay in aged condition, respectively. Moreover, T actp/a is the dwelling time of V aN considering T d , T don , and T doff when the switching devices are aging and the pole current is positive. In addition, T actn/a is the dwelling time of V aN considering T d , T don , and T doff when the switching devices are aging, and the pole current is negative. Figure 26a,b show the current path according to the pole current direction. Figure 26a,b demonstrate that the dwell time of V aN changes, as shown in Figure 26c, because the path through which the current flows varies according to the sign of the pole current [26]. Equation (16) represents T actp/f and T actn/f : Equation (16) becomes as (17) when aging is considered: T don/a and T doff/a in (17) can be calculated through (18): , In (18), Rate don and Rate doff can be obtained from Figure 21. Meanwhile, the duty error due to aging can be calculated as (19) using (17) and the voltage source inverter switching frequency (F swv ): In (19), D epv means the duty error of the voltage source inverter due to the gate oxide degradation when the pole current is positive. D env also represents the duty error of the voltage source inverter due to the gate oxide degradation when the pole current is negative. Figure 27 shows the duty error of the voltage source inverter according to the aging stress time.
Machines 2022, 10, x FOR PEER REVIEW 23 of 30 In (18), Ratedon and Ratedoff can be obtained from Figure 21. Meanwhile, the duty error due to aging can be calculated as (19) using (17) In (19), Depv means the duty error of the voltage source inverter due to the gate oxide degradation when the pole current is positive. Denv also represents the duty error of the voltage source inverter due to the gate oxide degradation when the pole current is negative. Figure 27 shows the duty error of the voltage source inverter according to the aging stress time.  Figure 27a shows the duty error according to the stress time when the pole current is positive. When the pole current is positive, the duty error increases at PHEF stress and decreases at NHEF stress. Figure 27b shows the duty error according to the stress time when the pole current is negative. When the pole current is negative, the duty error at PHEF stress decreases and the duty error at NHEF stress increases. In this chapter, the effects of the change in the duty error due to the gate oxide degradation on the output of the grid-connected inverter are analyzed through simulation. The parameters of the inverter used in the simulation are summarized in Table 4.   Figure 27a shows the duty error according to the stress time when the pole current is positive. When the pole current is positive, the duty error increases at PHEF stress and decreases at NHEF stress. Figure 27b shows the duty error according to the stress time when the pole current is negative. When the pole current is negative, the duty error at PHEF stress decreases and the duty error at NHEF stress increases. In this chapter, the effects of the change in the duty error due to the gate oxide degradation on the output of the grid-connected inverter are analyzed through simulation. The parameters of the inverter used in the simulation are summarized in Table 4. Figure 28 shows the simulation results of the grid-connected voltage source inverter according to HEF stress. Figure 28a-c are simulation results when using the duty error calculated from the fresh condition, PHEF stress during 3600 s, and NHEF stress during 3600 s, respectively. Figure 28 demonstrates that the THD of the grid current is the highest when the NHEF stress is applied for 3600 s. In addition, the peak-to-peak value of P is the largest in the case of PHEF stress. Moreover, the peak-to-peak value of Q is the largest in the case of NHEF stress.  Figure 28 shows the simulation results of the grid-connected voltage source inverter according to HEF stress. Figure 28a-c are simulation results when using the duty error calculated from the fresh condition, PHEF stress during 3600 s, and NHEF stress during 3600 s, respectively. Figure 28 demonstrates that the THD of the grid current is the highest when the NHEF stress is applied for 3600 s. In addition, the peak-to-peak value of P is the largest in the case of PHEF stress. Moreover, the peak-to-peak value of Q is the largest in the case of NHEF stress.  Figure 29 showsgraphs summarizing the THD of the grid current and the peak-to-peak values of the instantaneous power according to the stress time. Figure 29 indicates that as the gate oxide degradation progresses, the quality of the grid current and the reference tracking ability of the voltage source inverter deteriorates.  Figure 29 showsgraphs summarizing the THD of the grid current and the peak-to-peak values of the instantaneous power according to the stress time. Figure 29 indicates that as the gate oxide degradation progresses, the quality of the grid current and the reference tracking ability of the voltage source inverter deteriorates.  Figure 30 shows experiment waveforms of a three-phase voltage source inverter with RL load. A-phase of the inverter in Figure 30 was composed of SiC MOSFETs aged with PHEF stress. In addition, the remaining phases were composed of fresh SiC MOSFETs. Figure 30a represents the waveforms when the upper switch of a-phase is turned on. In Figure 30a, Vds_Sau means the Vds of the upper switch of a-phase. Furthermore, Vgs_Sau represents the Vgs of the upper switch of a-phase. Moreover, Ids_Sau is the Ids of the upper switch of a-phase. Figure 30a shows that the turn-on delay of the a-phase upper switch is 60 ns. Figure 30b is the three-phase current waveform of the inverter. In Figure 30b, iLa, iLb, and iLc represent the a-phase, b-phase, and c-phase inverter currents, respectively. Figure 30b demonstrates that the shape of the waveform hardly changes even when a-phase is aged.Therefore, Figure 30b shows that the aging degree of the inverter cannot be monitored by the load current shape.  Figure 30 shows experiment waveforms of a three-phase voltage source inverter with RL load. A-phase of the inverter in Figure 30 was composed of SiC MOSFETs aged with PHEF stress. In addition, the remaining phases were composed of fresh SiC MOSFETs. Figure 30a represents the waveforms when the upper switch of a-phase is turned on. In Figure 30a, V ds_Sau means the V ds of the upper switch of a-phase. Furthermore, V gs_Sau represents the V gs of the upper switch of a-phase. Moreover, I ds_Sau is the I ds of the upper switch of a-phase. Figure 30a shows that the turn-on delay of the a-phase upper switch is 60 ns. Figure 30b is the three-phase current waveform of the inverter. In Figure 30b, i La , i Lb , and i Lc represent the a-phase, b-phase, and c-phase inverter currents, respectively. Figure 30b demonstrates that the shape of the waveform hardly changes even when aphase is aged.Therefore, Figure 30b shows that the aging degree of the inverter cannot be monitored by the load current shape.  Figure 30 shows experiment waveforms of a three-phase voltage source inverter with RL load. A-phase of the inverter in Figure 30 was composed of SiC MOSFETs aged with PHEF stress. In addition, the remaining phases were composed of fresh SiC MOSFETs. Figure 30a represents the waveforms when the upper switch of a-phase is turned on. In Figure 30a, Vds_Sau means the Vds of the upper switch of a-phase. Furthermore, Vgs_Sau represents the Vgs of the upper switch of a-phase. Moreover, Ids_Sau is the Ids of the upper switch of a-phase. Figure 30a shows that the turn-on delay of the a-phase upper switch is 60 ns. Figure 30b is the three-phase current waveform of the inverter. In Figure 30b, iLa, iLb, and iLc represent the a-phase, b-phase, and c-phase inverter currents, respectively. Figure 30b demonstrates that the shape of the waveform hardly changes even when a-phase is aged.Therefore, Figure 30b shows that the aging degree of the inverter cannot be monitored by the load current shape.

Performance Variation of Current Source Inverter with Duty Error Change due to Gate Oxide Degradation
This section examines the performance variation of the current source inverter (CSI) according to the duty error change due to the gate oxide degradation. Figure 31 shows a three-phase CSI. In Figure 31, Sc1, Sc2, Sc3, Sc4, Sc5, and Sc6 represent the switches of the CSI. Additionally,Rc and Lc are the load resistor and inductor, respectively. Moreover,ic means the output current of the current source inverter.Idc is the input DC current supplied by the current source which can be expressed as a voltage source (V) and an inductor (Ldc) connected in series. Ldc represents the DC link inductor. Cc is the output capacitor required to drive the current source inverter. The current source inverter is usually controlled by space vector modulation [27].
In the CSI, Idc on the input side must flow without interruption. If the path through which Idc can flow disappears, an overvoltage is induced in Ldc. The voltage induced by the variation of Idc is expressed by (20). In (20), VLdc denotes a voltage induced in Ldc. Therefore, in the current source inverter, the overvoltage in Ldc is prevented by setting the overlap time when the switching state changes: = (20) Figure 32 represents the gating signals of the CSI in Figure 30. Figure 30. Experiment waveforms of three-phase voltage source inverter with RL load: (a) turn-on waveform of aged a-phase upper switch, and (b) three-phase load current with aged a-phase.

Performance Variation of Current Source Inverter with Duty Error Change Due to Gate Oxide Degradation
This section examines the performance variation of the current source inverter (CSI) according to the duty error change due to the gate oxide degradation. Figure 31 shows a three-phase CSI.

Performance Variation of Current Source Inverter with Duty Error Change due to Gate Oxide Degradation
This section examines the performance variation of the current source inverter (CSI) according to the duty error change due to the gate oxide degradation. Figure 31 shows a three-phase CSI. In Figure 31, Sc1, Sc2, Sc3, Sc4, Sc5, and Sc6 represent the switches of the CSI. Additionally,Rc and Lc are the load resistor and inductor, respectively. Moreover,ic means the output current of the current source inverter.Idc is the input DC current supplied by the current source which can be expressed as a voltage source (V) and an inductor (Ldc) connected in series. Ldc represents the DC link inductor. Cc is the output capacitor required to drive the current source inverter. The current source inverter is usually controlled by space vector modulation [27].
In the CSI, Idc on the input side must flow without interruption. If the path through which Idc can flow disappears, an overvoltage is induced in Ldc. The voltage induced by the variation of Idc is expressed by (20). In (20), VLdc denotes a voltage induced in Ldc. Therefore, in the current source inverter, the overvoltage in Ldc is prevented by setting the overlap time when the switching state changes: = (20) Figure 32 represents the gating signals of the CSI in Figure 30. In Figure 31, S c1 , S c2 , S c3 , S c4 , S c5 , and S c6 represent the switches of the CSI. Additionally, R c and L c are the load resistor and inductor, respectively. Moreover, i c means the output current of the current source inverter. I dc is the input DC current supplied by the current source which can be expressed as a voltage source (V) and an inductor (L dc ) connected in series. L dc represents the DC link inductor. C c is the output capacitor required to drive the current source inverter. The current source inverter is usually controlled by space vector modulation [27].
In the CSI, I dc on the input side must flow without interruption. If the path through which I dc can flow disappears, an overvoltage is induced in L dc . The voltage induced by the variation of I dc is expressed by (20). In (20), V Ldc denotes a voltage induced in L dc . Therefore, in the current source inverter, the overvoltage in L dc is prevented by setting the overlap time when the switching state changes: V Ldc = L dc dI dc dt (20) Figure 32 represents the gating signals of the CSI in Figure 30. Tdon/a and Tdoff/ain (21) are calculated by (18). From (21), the duty error of the CSI when it is aged can be obtained as (22): In (22), Dec means the duty error of the CSI according to aging. Moreover, Fswc represents the switching frequency of the CSI. Figure 33 shows the duty error of the CSI according to the HEF stress time. As shown in Figure 33, the duty error decreases under PHEF stress and increases under NHEF stress.  In Figure 32, T ov means the overlap-time set in advance when outputting the switching signals. In addition, T or/f means the dwelling time of the switching signal considering T ov , T don , and T doff in the fresh state. Moreover, T or/a represents the dwelling time of the switching signal considering T ov , T don , and T doff in the aged state. T rc indicates the dwelling time of the switching signal under ideal conditions. T or/f and T or/a are calculated through (21): T or/ f = T rc + T ov − T don/ f + T do f f / f , T or/a = T rc + T ov − T don/a + T do f f /a (21) T don/a and T doff/a in (21) are calculated by (18). From (21), the duty error of the CSI when it is aged can be obtained as (22): D ec = (T or/a − T rc )F swc = T ov − T don/a + T do f f /a F swc (22) In (22), D ec means the duty error of the CSI according to aging. Moreover, F swc represents the switching frequency of the CSI. Figure 33 shows the duty error of the CSI according to the HEF stress time. As shown in Figure 33, the duty error decreases under PHEF stress and increases under NHEF stress. Tdon/a and Tdoff/ain (21) are calculated by (18). From (21), the duty error of the CSI when it is aged can be obtained as (22): In (22), Dec means the duty error of the CSI according to aging. Moreover, Fswc represents the switching frequency of the CSI. Figure 33 shows the duty error of the CSI according to the HEF stress time. As shown in Figure 33, the duty error decreases under PHEF stress and increases under NHEF stress.  A simulation was conducted to find out the effect of the change in duty error due to the gate oxide degradation on the CSI output current THD. Using the simulation, the THD of the output current of the CSI according to the duty error is examined. The CSI is controlled through space vector modulation, and open-loop control is performed. The parameters of the CSI used in the simulation are shown in Table 5.  Figure 34 shows the simulation results of the CSI according to HEF stress. i ca , i cb , and i cc in Figure 34 represent the a, b, and c-phase output currents of the CSI, respectively. Figure 34 demonstrates that simulation results at PHEF stress have the smallest THD of the output current. In addition, the output current quality at NHEF stress is the worst.
Machines 2022, 10, x FOR PEER REVIEW 28 of 30 A simulation was conducted to find out the effect of the change in duty error due to the gate oxide degradation on the CSI output current THD. Using the simulation, the THD of the output current of the CSI according to the duty error is examined. The CSI is controlled through space vector modulation, and open-loop control is performed. The parameters of the CSI used in the simulation are shown in Table 5.  Figure 34 shows the simulation results of the CSI according to HEF stress. ica, icb, and icc in Figure 34 represent the a, b, and c-phase output currents of the CSI, respectively. Figure 34 demonstrates that simulation results at PHEF stress have the smallest THD of the output current. In addition, the output current quality at NHEF stress is the worst.  Figure 35 summarizes the average of the three-phase output current of the CSI according to the stress time. Figure 35 shows that in the case of PHEF stress, where the duty error decreases with the stress time, the THD of the three-phase output current is reduced as the stress time increases. However, in the case of NHEF stress, the THD of the output current slightly increases because the duty error rises with the stress time.  Figure 35 summarizes the average of the three-phase output current of the CSI according to the stress time. Figure 35 shows that in the case of PHEF stress, where the duty error decreases with the stress time, the THD of the three-phase output current is reduced as the stress time increases. However, in the case of NHEF stress, the THD of the output current slightly increases because the duty error rises with the stress time.