Triple-Source Reduced-Component-Count Multilevel Inverter Integrated with a Carrier-Less Hybrid Pulse-Width Modulation Strategy for Enhanced Power Conversion Performance

Abstract

A novel reduced-component multilevel inverter (MLI) topology is presented to overcome the limitations of conventional multilevel inverters, such as high switching losses, complex modulation, and excessive semiconductor usage. The proposed triple-source cross-connected configuration minimizes conduction paths and reduces voltage stress across switching devices to approximately 45% of the total DC-link voltage. A hybrid carrier-less pulse-width modulation (PWM) strategy, derived from the equal-area criterion, was developed to generate switching pulses without the need for carriers or reference signals. Analytical and experimental analyses demonstrated a significant improvement in power quality, achieving a total harmonic distortion (THD) of 4.3%, compared with 8.2% in conventional PWM schemes, while enhancing the conversion efficiency from 91.5% to 95.2%. Simulation and hardware validation in a nine-level prototype confirmed the superior efficiency, low harmonic distortion, and compactness of the proposed inverter, making it well-suited for renewable energy integration, electric vehicles, and medium-power industrial systems.

1. Introduction

Inverters play a vital role in ensuring a stable power supply across residential, commercial, and industrial sectors, as well as in critical domains such as healthcare and renewable energy systems. Among various inverter configurations, multilevel inverters (MLIs) are increasingly adopted due to their ability to produce high-quality voltage with reduced harmonic distortion and lower electromagnetic interference. Compared with traditional two-level converters, MLIs offer modularity, improved power quality, and reduced voltage stress in devices.

However, conventional topologies such as cascaded H-bridge (CHB), flying capacitor (FC), and neutral-point-clamped (NPC) inverters are widely studied, yet each has inherent drawbacks. The CHB inverter requires multiple isolated DC sources, leading to bulky systems and high cost. The FC and NPC configurations suffer from capacitor voltage-balancing issues, complex control strategies, and increased switching device counts, which lower system reliability. These limitations motivate research into reduced-component-count (RCC) multilevel topologies that aim to simplify circuit design while maintaining high performance.

Several improved reduced-component-count multilevel inverter (RCC-MLI) configurations have been reported, including diode-switched and capacitor-assisted MLIs. However, these approaches often involve non-uniform voltage stresses, increased switching transitions, or dependency on multiple carrier-based modulation techniques that reduce dynamic performance. Recent studies [1,2,3] have focused on high-frequency links and modified H-bridge topologies to minimize transformer size and device count, but most still face harmonic distortion and efficiency trade-offs.

To overcome these challenges, this paper proposes a triple-source reduced-component-count (RCC) MLI integrated with a hybrid carrier-less PWM strategy. The proposed design reduces the total number of switches and gate drivers, minimizes voltage stress on semiconductor devices, and improves conversion efficiency. Analytical, simulation, and experimental analyses demonstrate the capability of the topology to achieve low THD (total harmonic distortion) and high efficiency using simplified modulation. The key objectives of this research are as follows:

• To develop a compact MLI structure using a triple-source configuration with minimal components.
• To design a carrier-less hybrid PWM technique that reduces switching frequency and losses.
• To analytically evaluate voltage stress, conduction losses, and harmonic distortion performance.
• To experimentally validate the proposed topology for renewable and electric-drive applications.

1.1. Literature Review

A 21-stage switched-diode-based multistage inverter design incorporates not only a high-frequency link (HFL) but also an individual DC source to reduce power components, cut down on the transformer size, and, at the same time, generate various voltage stages with low total harmonic distortions (THDs) [4]. A new modified cascaded H-bridge multistage inverter (MCHBMLI) has been proposed with a component of eight switches and four isolated DC input voltage sources, which are combined with a controlled DC-DC converter in order to formulate the photovoltaic (PV) source voltage [5]. The proposed modified cascaded H-bridge multilevel inverter (MCHBMLI) algorithm not only enhances the performance of the system but also minimizes the count of overall components in the circuit. Specifically, the low THD and the voltage waveform with less distortion, as well as the lower-voltage impacts on the switches, are the features of the suggested modified cascaded H-bridge multilevel inverter (MCHBMLI). Along with a classical H-bridge inverter, a voltage-level generator creates all the possible voltage stages to form a new five-level single-phase inverter. The MLI employs level-shifted PWM phase opposition disposition (POD) and alternative phase opposition disposition (APOD) techniques in order to extract the suitable changing gate signals for a five-level inverter to generate the balanced output voltage [6]. A new 17-level single-phase inverter has been unveiled, which is an integration of changing modules and multiple DC sources to increase the output voltage range while minimizing harmonics. A new modulation method was introduced to further significantly minimize harmonic distortion, thus resulting in a better waveform performance and enhanced system efficiency, a viable choice with fewer parts and higher voltage level output [7]. A novel type of multilevel inverter (MLI) with fewer switches has been designed to find the most fitting algorithm for flexible AC transmission systems (FACTS), green energy systems, and motor drive applications [8]. The paper discusses various multilevel inverter (MLI) topologies in depth, placing particular importance on efficiency, harmonic deviation, switch count, and the quality of the output. It emphasizes the latest MLI designs aimed at medium- and high-power applications, achieved by minimizing gate drivers, semiconductor switches, and isolated DC sources, hence simplifying the circuitry and still maintaining the performance level [9].

To strengthen the literature foundation, additional recent contributions have been integrated into this section. Pragathi et al. [1] presented a high-frequency-link switched-diode 21-stage MLI capable of reducing transformer size but subject to increased switching stress. Farsijani et al. [2] proposed a modular hybrid inverter achieving a higher voltage resolution, though requiring multiple isolated DC inputs and additional gate drivers. Ramaprabha [3] introduced a single-phase cascaded MLI offering scalability but suffering from uneven conduction losses. These works confirm the persistent trade-off between component minimization, harmonic suppression, and system simplicity. A low-cost MLI was proposed to drive several kinds of lighting loads up to 30 W with fewer parts, and an ATMEGA microprocessor was employed to manage the inverter [10]. The proposed MLI is argued to be effective, among the rest, in linear (filament) and nonlinear loads (CFL and LED). A transformer-less MLI has been introduced that solves the problem of leakage current; thus, it stabilizes the common-mode voltage and minimizes harmonic distortion in PV grid-connected systems [11]. Two alternative connection models have been implemented to address the issue of leakage current. An algorithm for electric vehicle (EV) applications has been suggested with the purpose of minimizing the count of switches and, at the same time, to have the possibility to adjust to different DC source voltage ratios both in the symmetric and asymmetric modes for the input [12]. The bidirectional multistage boost design featured in the proposed algorithm is aimed at raising the DC-link voltage from a low-input source, which is perfect for electric vehicles. A newly suggested 17-level inverter with fewer switches that employs a modified sine PWM mechanism is then presented; this way, battery storage systems and grid integration can be made without transformers, thus keeping efficiency high and system complexity low [13]. The power handling capacity of the developed MLI, which is structured in a modular manner, is increased without additional converters. The total harmonic distortion (THD) in the output voltage of a cascaded H-bridge multilevel inverter is minimized by removing the dominant harmonics by a genetic algorithm (GA)-based optimization mechanism for the calculation of changing angles that are optimized [14]. The process is implemented with a five-level inverter, whose changing angles are improved to minimize the values of third and fifth harmonics to below 3%. An individual DC source is utilized for six H-bridge modules in a three-phase five-level MLI algorithm, which is proposed to get rid of the multiple DC sources [15]. The proposed algorithm employs a method of changing multiple times per step (hybrid-coded genetic algorithm), which allows it to have 12 notches on the output voltage and, thus, greatly enhances the harmonic elimination ability. A modified structure MLI has been proposed in order to investigate its performance based on total harmonic distortion (THD) by applying various modulation techniques that enable it to provide the output voltage of the required level [16]. The research discloses the obstacles still existing in output performance improvement via innovation in design and modulation techniques. Minimized-power-switch-count cascaded H-bridge inverter-based new multistage inverters have been presented. A novel changing mechanism that simplifies the changing process is explained in [17]. The reduction in total harmonic distortion (THD) caused by the changing mechanism in the output voltage is mentioned as a positive side. A novel switched-capacitor MLI with fewer power switches to extend the output voltage stages by employing an individual DC source is brought up in [18]. The MLI takes advantage of a DC source with a changing configuration to enable more voltage stages of output.

Two multilevel inverter topologies with symmetrical and asymmetrical types have been introduced to minimize switches with fewer ON-state switches and overall blocking voltages over switches [19]. The proposed topologies are designed to enhance output voltage stages using various control algorithms. A novel cascaded multilevel inverter configuration has been introduced, supporting both symmetric and asymmetric modes, while focusing on minimizing power components, thereby improving efficiency and reducing overall system complexity [20]. The proposed level-dependent sources concoction multistage inverter (LDSCMLI) offers advantages, such as fewer switches, minimized gate drivers, and lower peak inverse voltage. It produces a stepped DC-link voltage by a source integration module, which is later transformed into a stepped AC output using a traditional H-bridge [21]. The suggested algorithm efficiently demonstrated its operating performance better than CHBMLI with a reduced component count. A novel MLI algorithm has been suggested to minimize the count of components greatly, especially when the output stages are large. The MLI exploits floating input DC sources that are alternately connected in opposite polarities via power switches to achieve a reduction in overall components compared with traditional topologies [22]. The multistage inverter (MLI) framework comprises stepped voltage generation units, each of which is created using several sub-modules. These sub-modules mainly consist of two DC voltage sources connected in series together with a half-bridge structure and a polarity-changing device. This architecture allows controlled voltage stepping and direction reversal, and thus, it is able to support efficient voltage level synthesis, improve output waveform quality, and minimize component impacts [23]. An optimal structure for the new MLI has been demonstrated with experimental results. The new MLI comprises an H-bridge and an inverter to switch DC voltage sources in series and parallel, facilitating more voltage stages with fewer changing modules [24]. The proposed MLI provides fewer switches and gate drivers. To meet the main challenge of the count of changing modules, the authors have come up with a novel MLI algorithm that specifically deals with heavy-duty asymmetric multistage inverters. The algorithm [25], which utilizes sub-multistage cells that are connected in series to generate five stages of voltage without increasing the count of DC voltage sources and changing devices, is the most ingenious one. Motivated by these limitations, this study proposes a triple-source reduced-component MLI topology integrated with a carrier-less hybrid PWM strategy. The topology minimizes device count, simplifies control, and achieves high-quality output with low total harmonic distortion (THD). The approach ensures reduced conduction and switching losses, improved voltage utilization, and enhanced dynamic performance, validated through analytical derivation, simulation, and experimental implementation.

1.2. Research Gap

Existing carrier-based and carrier-less PWM techniques often require high switching frequencies or multiple carrier signals, resulting in increased computational burden and switching losses. Additionally, most MLI designs still rely on numerous semiconductor switches and isolated DC sources, leading to greater circuit complexity. Few studies have effectively combined a reduced component count with a simplified hybrid PWM control strategy suitable for real-time implementation.

2. Developed Topology

The proposed triple-source reduced-component multilevel inverter (RCC-MLI) introduces a simplified modular structure that generates multiple output voltage levels using a minimum number of semiconductor devices and DC sources. The main feature of this topology is the use of three DC sources (DC₁, DC₂, and DC₃) connected through a cross-linked configuration that allows additive and subtractive voltage synthesis without relying on clamping capacitors or multiple isolated supplies. The resulting architecture is capable of producing both symmetrical and asymmetrical voltage levels, which makes it highly flexible for integration into renewable energy and electric drive systems.

Here, Figure 1 illustrates the general configuration of the proposed MLI. Each module consists of a combination of unidirectional and bidirectional switches, where the bidirectional devices (S′L and S′R) enable reverse current conduction under inductive load conditions. The ladder-structured connection permits voltage level generation by selective activation of these switches, forming distinct current conduction paths for each output state.

Figure 1. (a,b) Overall circuit configuration of the proposed triple-source reduced-component-count (RCC) multilevel inverter (MLI). Three isolated DC sources (DC1, DC2, and DC3) are connected through a cross-linked bridge structure using unidirectional and bidirectional switches to generate multiple output voltage levels with a reduced component count.

2.1. Voltage Level Generation Mechanism

The output voltage levels are synthesized by controlling the conduction sequence of the switches associated with each DC source. For every level, only four switches conduct simultaneously, thus reducing conduction losses. The sequence ensures that unidirectional current flows through the load without circulating among DC sources.

The voltage levels and corresponding switch combinations are summarized as follows:

• For the minimum output level (+V_DC1), switches S_R1, S′_L2, and _SL3 conduct, establishing a current path through DC₁.
• For the intermediate level (+V_DC2 − V_DC1), switches S_R1, S′_L2, S_R3, and S₃ are ON, connecting DC₂ while isolating DC₁.
• For the next higher level (+V_DC2 + V_DC3 − V_DC1), switches S_R1, S′_R2, S_L3, and S₁ conduct, allowing additive synthesis of the DC₂ and DC₃ voltages.
• For the maximum level (+V_DC1 + V_DC2 + V_DC3), switches S_R1, S′_R2, S_R3, and S₁ are ON, yielding the full triple-source voltage output.

During negative half-cycles, the corresponding switches on the opposite leg operate in a complementary manner to generate the negative voltage levels. The conduction paths for all these states are illustrated in revised Figures 3–12, where current directions are clearly marked with arrows. For better clarity, each voltage step from figures mentioned above includes the corresponding switch combination and load current direction. The conduction paths are sequentially discussed to illustrate the physical behavior of the current through the load at every voltage level.

2.2. Current Conduction Paths and Inductive Load Behavior

For inductive loads, where the current lags the voltage, current continuity is ensured by the bidirectional switch configuration and the anti-parallel diodes connected across all IGBTs. When a switch is turned OFF, the associated freewheeling diode momentarily conducts, maintaining current flow through the load and preventing voltage overshoot. This arrangement guarantees smooth current commutation and eliminates abrupt interruptions, as validated by the experimental waveforms shown in revised Figures 21 and 24. A representative R–L load is integrated in all switching states (Figures mentioned above), where current continuity is maintained through bidirectional switches and anti-parallel diodes. This ensures an uninterrupted current even during voltage polarity reversal.

2.3. Voltage and Current Stress Across Switches

To accurately estimate the conduction and switching losses, the voltage and current stresses across each semiconductor device were analytically derived. The maximum blocking voltage for each device is expressed as

S_L1 = S_R1 = DC_(3n−2) + DC_(3n−1) + DC_(3n); n ≥ 1

(1)

Here, ${\mathrm{V}}_{\mathrm{m}}$ represents the peak amplitude of the desired fundamental voltage, $\mathrm{T}$ denotes the total period of the sinusoidal waveform, $\mathrm{E}$ is the DC source voltage, ${\mathsf{\delta }}_{\mathrm{k}}$ indicates the pulse width corresponding to the $\mathrm{k}\mathrm{t}\mathrm{h}$ segment, and $\mathrm{S}\mathrm{S}$ refers to the switching state determining the active voltage level during each interval.

S_(3n−1) = S_(3n−2) = DC_(3n)

(2)

S_(3n) = DC_(3n−1)+ DC_(3n); n ≥ 1

(3)

$${\mathrm{S}}_{\mathrm{L}(\mathrm{n}+1)}={\mathrm{S}\prime }_{\mathrm{L}(\mathrm{n}+1)}={\mathrm{S}}_{\mathrm{R}(\mathrm{n}+1)}={\mathrm{S}\prime }_{\mathrm{R}(\mathrm{n}+1)}={\displaystyle \sum _{\mathrm{j}=1}^{\mathrm{n}-1}{\mathrm{DC}}_{\mathrm{j}}+[\mathrm{DC}(3\mathrm{n}-2)+\mathrm{DC}(3\mathrm{n}-1)+\mathrm{DC}(3\mathrm{n})]}$$

(4)

SL(n+2) = SR(n+2) = [DC(3n − 2) + DC(3n − 1) + DC(3n)]; n ≥ 1

(5)

These relationships confirm that the maximum voltage stress experienced by any switch does not exceed approximately 45% of the total DC-link voltage, ensuring reduced device stress and improved reliability.

The current through each conducting switch equals the instantaneous load current (I_load), since only four devices conduct at a time. Therefore, the conduction loss for each device is calculated as

$$P_{cond}=I_{rms}^2\times R_{on}\hspace{1em}Watts$$

(6)

and the total conduction loss per cycle becomes

$$P_{cond}(total)=4\times I_{rms}^2\times R_{on}\hspace{1em}Watts$$

(7)

Power loss analysis: The power loss can be estimated from the characteristic curves of the devices available in the datasheets. The power loss calculation includes conduction and switching losses. The selected IGBTs (IRG4BC20SD) are subjected to a maximum forward current of 19 A and a direct voltage of 600 V. The characteristic curves are Vsat(θ) × Il(θ) and E(θ) × Il(θ), where Vsat is the ON-state saturation voltage (Vce(θ) for the IGBT and VF(θ) for the diode), and E(θ) represents the energy loss during a single commutation (EON(θ) is a turn-ON commutation, EOFF (θ) the turn-off commutation, and Erec(θ) is owed for the diode reverse recovery process). The curves are approximated by the exponential in (9) to (14) using the curve-fitting tool available in MATLAB 2018. The mathematical models obtained for the IGBTs are given by

$$V_{cc}=0.96e^{0.0016}{I}_1\left(\theta \right)-0.4654e^{-0.011}{I}_1(\theta )$$

(8)

$$V_F=0.6e^{0.002}{I}_1\left(\theta \right)-0.4258e^{-0.0275}{I}_1(\theta )$$

(9)

$$Erec=0.000806e^{-0.000322}{I}_1\left(\theta \right)-0.0057e^{-0.0446}{I}_1(\theta )$$

(10)

$$E_{ON}=0.00041e^{-0.0044}{I}_1\left(\theta \right)-0.0037e^{-0.008}{I}_1(\theta )$$

(11)

$$Eoff=0.0443e^{0.00021}{I}_1\left(\theta \right)-0.00547e^{-0.0107}{I}_1(\theta )$$

(12)

$$I_1\left(\theta \right)=I_{max}(\mathrm{s}\mathrm{i}\mathrm{n}(\theta -\phi ))$$

(13)

where Il(θ) is the load current, and j is the load–displacement angle.

The switching loss occurs during turn-ON and turn-OFF, and for every power device (Psw), it is obtained by identifying the corresponding turn-ON and turn-OFF instants during one reference period by using (14), as follows:

$$P_{sw}={\displaystyle \frac{1}{T}}\sum (E_{ON}+E_{OFF}+E_{rec})$$

(14)

The current is computed by multiplying the ON-state voltage by the ON-state current. The calculation of conduction losses for each semiconductor device using (15) to (16) is given by

$$P_{conT}={\displaystyle \frac{1}{2\pi }}{\int }_0^{2\pi }{V}_{cc}\left(\theta \right)I_1\left(\theta \right)d\theta$$

(15)

$$P_{conT}={\displaystyle \frac{1}{2\pi }}{\int }_0^{2\pi }{V}_F\left(\theta \right)I_1\left(\theta \right)d\theta$$

(16)

2.4. Switching Loss Minimization

The carrier-less hybrid PWM strategy used in this topology minimizes switching losses by reducing the number of transitions per fundamental cycle. Each device switches only when the current crosses zero or at controlled angles derived from the equal-area criterion, expressed as

$$P_{sw}={\displaystyle \frac{1}{2}}{V}_{sw}{I}_{sw}(t_{on}+t_{off})f_{sw}$$

(17)

By lowering the effective switching frequency and synchronizing turn-ON/turn-OFF events with current zero crossings, the proposed method significantly reduces the total switching energy dissipation.

The blocking voltage and current conduction through each switch were analyzed to determine the power losses in the proposed inverter. Each device sustains only a portion of the total DC-link voltage, as derived in Equations (1)–(5), effectively reducing voltage stress. During operation, only four switches conduct at a time, and each carries the same load current. Consequently, both conduction and switching losses are minimized due to reduced current paths and fewer transitions per cycle under the hybrid PWM strategy (Figure 2).

Figure 2. Circuit diagram of the proposed 21-level RCC-MLI using three DC sources and cross-connected switches for voltage synthesis.

Each voltage level in the proposed 21-level inverter is synthesized through controlled activation of specific switch pairs on the left and right arms of the ladder-structured triple-source module. For each voltage step, only four switches are in the conducting state, establishing distinct current conduction paths between the selected DC sources and the load. Figure 3, Figure 4, Figure 5, Figure 6, Figure 7, Figure 8, Figure 9, Figure 10, Figure 11 and Figure 12 illustrate these conduction paths for both polarities, where the current direction is indicated by arrows. This switching pattern ensures a unidirectional current flow, minimizes device stress, and results in reduced conduction losses while producing symmetric stepped voltage levels.

Figure 3. Switching state for the output voltage level ± DC1. Current conduction path for output level +VDC1. Switches SR1, S′L2, and SL3 are turned ON, establishing the current flow through DC₁ and the load. The remaining switches are OFF, ensuring minimal conduction loss. Red color flow (left diagram) denotes the current conduction path for the positive output voltage level (+VDC1). Blue color flow (right diagram) denotes the current conduction path for the negative output voltage level (−VDC1).

Figure 4. Switching state for the output voltage level ± (DC2−DC1) and the conduction path for the output level + VDC2 − VDC1. Switches SR1, S′L2, SR3, and S₃ are ON, connecting DC₂ to the load while isolating DC₁. This configuration produces an intermediate positive voltage level. Red color flow (left diagram) denotes the current conduction path for the positive output voltage level (+VDC1). Blue color flow (right diagram) denotes the current conduction path for the negative output voltage level (−VDC1).

Figure 5. Switching state for the output voltage level ± DC₂. In this mode, switches SR1, SR2′, SL3, and S1 conduct to synthesize an additive voltage of +VDC2 + VDC3 − VDC1 across the load. Red color flow (left diagram) denotes the current conduction path for the positive output voltage level (+VDC1). Blue color flow (right diagram) denotes the current conduction path for the negative output voltage level (−VDC1).

Figure 6. Switching state for the output voltage level ± (DC2 + DC1). Current conduction path for maximum output level +VDC1 + VDC2 + VDC3. Switches SR1, S′R2, SR3, and S₁ are ON, providing the full positive peak voltage. This state represents the highest energy conversion point. Red color flow (left diagram) denotes the current conduction path for the positive output voltage level (+VDC1). Blue color flow (right diagram) denotes the current conduction path for the negative output voltage level (−VDC1).

Figure 7. Switching state for the output voltage level ± (DC2 + DC3 − DC1). Conduction path for zero (neutral)-voltage level. The complementary leg switches S′L and S′R operate simultaneously, forming a short-circuited current loop within the inverter, maintaining load current continuity without producing an output voltage. Red color flow (left diagram) denotes the current conduction path for the positive output voltage level (+VDC1). Blue color flow (right diagram) denotes the current conduction path for the negative output voltage level (−VDC1).

Figure 8. Switching state for the output voltage level ± (DC2 + DC3) and current conduction path for the negative voltage level −VDC1. The corresponding lower-leg switches SL1, S′R2, and SR3 are ON. The load current flows in the reverse direction through DC₁ and anti-parallel diodes, ensuring a symmetrical negative output. Red color flow (left diagram) denotes the current conduction path for the positive output voltage level (+VDC1). Blue color flow (right diagram) denotes the current conduction path for the negative output voltage level (−VDC1).

Figure 9. Switching state for the output voltage level ± (DC2 + DC3 + DC1) and conduction path for negative intermediate level −(VDC2 − VDC1). Switches SL1, S′R2, SL3, and S₃ are ON, connecting DC₂ in reverse polarity relative to the load. Red color flow (left diagram) denotes the current conduction path for the positive output voltage level (+VDC1). Blue color flow (right diagram) denotes the current conduction path for the negative output voltage level (−VDC1).

Figure 10. Switching state for the output voltage level ± (DC2 + DC3 + DC4 − DC1) and conduction path for −(VDC2 + VDC3 − VDC1). Switches SL1, S′L2, SR3, and S₁ conduct, producing the additive negative level across the load. Red color flow (left diagram) denotes the current conduction path for the positive output voltage level (+VDC1). Blue color flow (right diagram) denotes the current conduction path for the negative output voltage level (−VDC1).

Figure 11. Switching state for the output voltage level ± (DC2 + DC3 + DC4) and switching configuration for the maximum negative level −(VDC1 + VDC2 + VDC3). Switches SL1, S′L2, SL3, and S₁ are ON. This represents the mirror image of the highest positive level. Red color flow (left diagram) denotes the current conduction path for the positive output voltage level (+VDC1). Blue color flow (right diagram) denotes the current conduction path for the negative output voltage level (−VDC1).

Figure 12. Switching state for the output voltage level ± (DC2+ DC3+ DC4+ DC1) and generalized switching sequence diagram summarizing all conduction states of the proposed RCC-MLI for one fundamental cycle. The figure highlights symmetry between positive and negative half-cycles and the reduced number of active switches per step (only four at any time). Red color flow (left diagram) denotes the current conduction path for the positive output voltage level (+VDC1). Blue color flow (right diagram) denotes the current conduction path for the negative output voltage level (−VDC1).

The proposed RCC-MLI produces stepped output voltage levels based on the number of DC input sources and switching combinations (Table 1 and Table 2). Each configuration incrementally adds voltage stages by summing available DC magnitudes, as summarized in Table 1.

Table 1. Relations for computing the magnitude value of DC voltage source.

Sl. No.	Source Magnitude Configuration	Voltage Level Expression	Total Number of Output Levels
1	DC1 = DC2 = DC3 = Vdc	Vout = ±(DC1 + DC2 + DC3) = ±3Vdc	6 × 31 + 1 = 19
2	DC1 = DC2 = DC3 = Vdc	Vout = ±(DC1 + DC2 + DC3 + DC4) = ±4Vdc	6 × 32 + 1 = 37
3	DC1 = DC2 = DC3 = Vdc	Vout = ±(DC1 + DC2 + DC3 + DC4 + DC5) = ±5Vdc	6 × 33 + 1 = 55
4	DC1 = DC2 = DC3 = Vdc	Vout = ±(DC1 + DC2 + DC3 + DC4 + DC5 + DC6) = ±6Vdc	6 × 34 + 1 = 73

Table 2. Switching states and conducting devices of the proposed 21-level RCC-MLI.

Output Voltage Level	Active Switches	Conducting Devices	Current Path Description
+VDC1	SL1, SR1, and S1	Two unidirectional switches + load	Current flows through upper left and right arms via S1
+VDC2	SL2, SR1, S1, and S2	Four switches	Second source adds to voltage synthesis
+VDC3	SL3, SR2, S2, and S3	Four switches	Third DC source participates in series addition
+VDC2 + VDC3 − VDC1	SR1, S′R2, SL3, and S1	Four switches	Reverse polarity state with negative terminal clamping
0	S1 and S2	Two switches	Neutral or zero-voltage condition
−VDC1	S′L1, S′R1, and S2	Three switches	Negative half-cycle; reverse current path
−VDC2	S′L2, S′R1, and S3	Four switches	Extended negative level
−VDC3	S′L3, S′R2, and S3	Four switches	Full negative level output

The practicality of the proposed algorithm is evidenced by a detailed comparison of switch count, gate drivers, and conducting current paths. It is also compared with CHBMLI and other recently developed reduced-component topologies, which are cited in references [19,20,21,22,23,24,25,26], thus revealing the impact of the algorithm on the execution of the tasks in the field. Figure 13 displays the graphs for the need of the switches along with the gate drivers and the current-conducting switches to build a 75-level inverter.

Figure 13. Comparison chart in terms of (a) switches, (b) gate drivers, and (c) current-conducting switches for a 75-level inverter.

Based on Figure 14b, only four switches conduct at any instant, reducing switching losses and simplifying control. The proposed inverter employs bidirectional switches realized through two IGBTs connected in a common-emitter configuration. This arrangement enables current conduction in both directions, ensuring continuous current flow through the load even during polarity transitions. Compared with conventional unidirectional switches used in cascaded H-Bridge MLIs, this configuration eliminates the need for additional anti-parallel diodes or commutation circuits, simplifying design and reducing switching losses. Moreover, bidirectional implementation ensures faster current reversal and enhanced reliability under inductive-loading conditions.

Figure 14. Comparison chart in terms of (a) switches and (b) current-conducting switches for variations in voltage levels.

Likewise, Figure 14 sketches the comparison chart between the proposed algorithm and recent reduced-count topologies against changes in the count of voltage levels. It is confirmed from Figure 13 and Figure 14 that fewer power components are needed by the proposed topology.

3. Proposed Hybrid PWM Strategy

The proposed control technique is based on pulse-width modulation (PWM) rather than pulse-position modulation (PPM). It employs a carrier-less hybrid PWM framework derived from the equal-area criterion, specifically optimized for the triple-source reduced-component-count multilevel inverter (RCC-MLI) topology. In this method, the width of each pulse is analytically computed, such that the area under the pulse equals the area of the corresponding segment of the sinusoidal reference waveform. This ensures accurate waveform synthesis, harmonic minimization, and precise digital implementation while avoiding carrier-based comparisons.

The primary objective of the proposed PWM mechanism is to generate modulation pulses for multilevel inverters without relying on conventional carrier or reference signals, thereby making it independent of the number of output voltage levels. The technique enforces that the average output voltage during each switching interval matches the corresponding section of the desired sinusoidal reference. The constant (square)-voltage component at each level is first subtracted from the desired fundamental voltage, leaving the remaining sinusoidal section to be reconstructed through PWM control. Each half-cycle is divided into discrete constant-voltage intervals, and calculated switching pulses are assigned to these intervals, such that the total area under each pulse matches that of the reference sine wave.

Unlike traditional multicarrier PWM, which depends on multiple triangular carriers and frequent commutations, the proposed carrier-less hybrid scheme determines switching instants directly from the crossing points of equal-area segments. This approach significantly reduces switching losses, simplifies digital realization, and maintains excellent waveform fidelity. Two hybrid modulation variants were developed, each employing different voltage-level selection (odd or even) to minimize total harmonic distortion (THD) while preserving the desired fundamental amplitude. The gating signals for all power devices are generated using a field-programmable gate array (FPGA)-based controller, which accesses pre-computed lookup tables derived from analytically determined switching angles. This digital realization guarantees precise timing synchronization and a close match between simulated and experimental waveforms. A fixed dead-time of 2 µs was implemented in the FPGA gating logic to avoid shoot-through conditions and minimize low-order harmonic distortion. The PWM generation module utilized approximately 1200 LUTs and 850 flip-flops on the Spartan-3E FPGA, operating at 50 MHz.

Novelty and Advantages of Proposed PWM Approach

While the equal-area principle has been explored in classical sinusoidal and selective harmonic elimination PWM methods, the present work introduces a novel carrier-less hybrid PWM scheme specifically designed for a triple-source RCC-MLI. This hybrid carrier-less PWM framework achieves a lower switching frequency per device, enhanced harmonic performance, and simplified digital control compared with conventional carrier-based PWM schemes. It effectively extends the equal-area principle into a practical, high-efficiency modulation method suitable for reduced-component-count multilevel inverter structures (Figure 15 and Figure 16).

Figure 15. Hybrid PWM strategy-amalgamated AEFSPWM.

Figure 16. Hybrid PWM strategy-amalgamated FSAEPWM.

The fundamental sine wave is vertically divided into ‘m’ constant stages with voltage magnitude (E). The intersecting point of the fundamental sine wave and the DC voltage determines the cross-over point (θ1, θ2…π/2). The non-linear portion is horizontally sampled [(S−1)/2] to achieve PWM pulses (p) in each quarter-cycle. For a nine-level inverter, the cross-over points are (θ1, θ2, θ3, and π/2), and the PWM occurs in the segments (0, θ1), (θ1, θ2), (θ2, θ3), and (θ3, π/2), while the square-wave portion in each level, including (π− θ1), (π− θ2), and (π− θ3), remains constant in that corresponding level because the area of both the desired and actual voltage are equal. Method I uses fundamental changing in odd levels and PWM in even levels of the output voltage, while Method II operates vice versa to Method I. Two distinct operational modes are defined in the proposed hybrid PWM scheme:

• Method I—fundamental changing mode: Low-frequency switching is applied to generate primary voltage steps corresponding to major transitions in the output waveform. This mode minimizes switching losses and establishes the base fundamental component.
• Method II—PWM mode: Within each fundamental interval, the equal-area-based PWM pulses are generated to refine waveform linearity and suppress harmonic content. This hybridization allows reduced THD while maintaining high efficiency.

Pulse rotation is applied in both methods to improve the output voltage quality by reducing harmonics and enhancing waveform symmetry.

The crossing instant between the fundamental sine with magnitude (VmT) and the actual output voltage with each level (k) at the voltage of (E) is

$$\begin{gathered} \left[{\mathrm{V}}_{\mathrm{mT}}\times {\mathrm{Sin}(\mathsf{\theta }}_{\mathrm{k}+1})\right]=\left(\mathrm{K}\times \mathrm{E}\right) \\ {\mathsf{\theta }}_{\mathrm{k}+1}={\mathrm{Sin}}^{-1}\left[{\displaystyle \frac{\left(\mathrm{K}\times \mathrm{E}\right)}{{\mathrm{V}}_{\mathrm{mT}}}}\right] \end{gathered}$$

(18)

where $\mathrm{k}=1,2\dots \left({\displaystyle \frac{\mathrm{m}-1}{2}}\right)$.

The duty cycle for fundamental changing is computed as follows.

The area of the desired fundamental sine voltage is given by

$${\mathrm{Desired}}_{\mathrm{k}}(\mathrm{p})={\displaystyle \underset{{\mathsf{\theta }}_{\mathrm{k}}}{\overset{{\mathsf{\theta }}_{\mathrm{k}+1}}{\int }}{\mathrm{V}}_{\mathrm{mT}}\sin \left(\omega \mathrm{t}\right)d\omega t-(\mathrm{i}\times \mathrm{E})\left[{\mathsf{\theta }}_{\mathrm{k}+1}-{\mathsf{\theta }}_{\mathrm{k}}\right]}$$

$${\mathrm{Desired}}_{\mathrm{k}}(\mathrm{p})={\mathrm{V}}_{\mathrm{mT}}\left[\cos \left({\mathsf{\theta }}_{\mathrm{k}}\right)-\cos \left({\mathsf{\theta }}_{\mathrm{k}+1}\right)\right]-\left(\mathrm{i}\times \mathrm{E}\right)\left[{\mathsf{\theta }}_{\mathrm{k}+1}-{\mathsf{\theta }}_{\mathrm{k}}\right]$$

$${\mathrm{Desired}}_{\mathrm{k}}(\mathrm{p})={2\mathrm{V}}_{\mathrm{mT}}\left[\sin \left({\displaystyle \frac{{\mathsf{\theta }}_{\mathrm{k}}+{\mathsf{\theta }}_{\mathrm{k}+1}}{2}}\right)\times \sin \left({\displaystyle \frac{{\mathsf{\theta }}_{\mathrm{k}+1}-{\mathsf{\theta }}_{\mathrm{k}}}{2}}\right)\right]-\left(\mathrm{i}\times \mathrm{E}\right)\left[{\mathsf{\theta }}_{\mathrm{k}+1}-{\mathsf{\theta }}_{\mathrm{k}}\right]$$

The area of the actual output voltage is given by

$$\begin{gathered} {\mathrm{Actual}}_{\mathrm{k}}\left(\mathrm{p}\right)=\left({\mathsf{\delta }}_{\mathrm{k}}\times \mathrm{E}\right) \\ {\mathrm{Actual}}_{\mathrm{k}}\left(\mathrm{p}\right)={\mathrm{Desired}}_{\mathrm{k}}\left(\mathrm{P}\right) \\ {\delta }_{\mathrm{k}}(\mathrm{p})=2\left({\displaystyle \frac{{\mathrm{V}}_{\mathrm{mT}}}{\mathrm{E}}}\right)\left[\sin \left({\displaystyle \frac{{\mathsf{\theta }}_{\mathrm{k}}+{\mathsf{\theta }}_{\mathrm{k}+1}}{2}}\right)\times \sin \left({\displaystyle \frac{{\mathsf{\theta }}_{\mathrm{k}+1}-{\mathsf{\theta }}_{\mathrm{k}}}{2}}\right)\right]-\left(\mathrm{i}\right)\left[{\mathsf{\theta }}_{\mathrm{k}+1}-{\mathsf{\theta }}_{\mathrm{k}}\right] \end{gathered}$$

The duty cycle for PWM is computed as follows.

The rising and falling instant of each sample (p) is given by

$${\mathrm{Rising} \mathrm{edge}}_{\mathrm{k}}\left(\mathrm{p}\right)=\mathrm{a}={\mathsf{\theta }}_{\mathrm{k}}+\left[{\displaystyle \frac{\left(\mathrm{p}-1\right)\left({\mathsf{\theta }}_{\mathrm{k}+1}-{\mathsf{\theta }}_{\mathrm{k}}\right)}{\mathrm{S}}}\right]; \mathrm{P}=1,2\dots \mathrm{S}$$

(19a)

$${\mathrm{Falling} \mathrm{edge}}_{\mathrm{k}}\left(\mathrm{p}\right)=\mathrm{b}={\mathsf{\theta }}_{\mathrm{k}}+\left[{\displaystyle \frac{\left(\mathrm{p}\right)\left({\mathsf{\theta }}_{\mathrm{k}+1}-{\mathsf{\theta }}_{\mathrm{k}}\right)}{\mathrm{S}}}\right]; \mathrm{P}=1,2\dots \mathrm{S}$$

(19b)

$${\mathrm{Desired}}_{\mathrm{k}}(\mathrm{p})={\displaystyle \underset{\mathrm{a}}{\overset{b}{\int }}{\mathrm{V}}_{\mathrm{mT}}\sin \left(\omega \mathrm{t}\right)d\omega t-(\mathrm{i}\times \mathrm{E})\left[\frac{{\mathsf{\theta }}_{\mathrm{k}+1}-{\mathsf{\theta }}_{\mathrm{k}}}{S}\right]}$$

(19c)

$${\mathrm{Desired}}_{\mathrm{k}}(\mathrm{p})={\mathrm{V}}_{\mathrm{mT}}\left[\cos \left(\mathrm{a}\right)-\cos \left(b\right)\right]-\left(\mathrm{i}\times \mathrm{E}\right)\left[{\displaystyle \frac{{\mathsf{\theta }}_{\mathrm{k}+1}-{\mathsf{\theta }}_{\mathrm{k}}}{S}}\right]$$

(19d)

$${\mathrm{Desired}}_{\mathrm{k}}(\mathrm{p})={2\mathrm{V}}_{\mathrm{mT}}\left[\sin \left({\theta }_k+\left(p-0.5\right){\displaystyle \frac{{\mathsf{\theta }}_{\mathrm{k}+1}-{\mathsf{\theta }}_{\mathrm{k}}}{\mathrm{S}}}\right)\times \sin \left({\displaystyle \frac{{\mathsf{\theta }}_{\mathrm{k}+1}-{\mathsf{\theta }}_{\mathrm{k}}}{2\mathrm{S}}}\right)\right]-\left(\mathrm{i}\times \mathrm{E}\right)\left[{\displaystyle \frac{{\mathsf{\theta }}_{\mathrm{k}+1}-{\mathsf{\theta }}_{\mathrm{k}}}{S}}\right]$$

(19e)

The area of the actual output voltage is given by

$$\begin{gathered} {\mathrm{Actual}}_{\mathrm{k}}\left(\mathrm{p}\right)=\left({\mathsf{\delta }}_{\mathrm{k}}\times \mathrm{E}\right) \\ {\mathrm{Actual}}_{\mathrm{k}}\left(\mathrm{p}\right)={\mathrm{Desired}}_{\mathrm{k}}\left(\mathrm{P}\right) \\ {\delta }_{\mathrm{k}}(\mathrm{p})=2\left({\displaystyle \frac{{\mathrm{V}}_{\mathrm{mT}}}{\mathrm{E}}}\right)\left[\sin \left({\theta }_k+\left(p-0.5\right){\displaystyle \frac{{\mathsf{\theta }}_{\mathrm{k}+1}-{\mathsf{\theta }}_{\mathrm{k}}}{\mathrm{S}}}\right)\times \sin \left({\displaystyle \frac{{\mathsf{\theta }}_{\mathrm{k}+1}-{\mathsf{\theta }}_{\mathrm{k}}}{2\mathrm{S}}}\right)\right]-\left(\mathrm{i}\right)\left[{\displaystyle \frac{{\mathsf{\theta }}_{\mathrm{k}+1}-{\mathsf{\theta }}_{\mathrm{k}}}{S}}\right] \end{gathered}$$

(20)

where, i = (k−1) and k is the Kth level modulated either by fundamental changing (p = 1) or PWM (p = 1, 2…S), respectively.

Equations (1)–(20) collectively define the analytical computation of pulse widths and switching instants. Each pulse width ${\mathsf{\delta }}_{\mathrm{k}}$ is determined such that the integral of the modulated voltage over a switching period equals that of the reference sine-wave segment. This process ensures an equal area under both curves, effectively reproducing the fundamental sinusoidal voltage while suppressing higher-order harmonics.

4. Analytical and Power Quality Analysis

The analytical validation of the proposed hybrid carrier-less PWM strategy establishes its ability to minimize low-order harmonics, enhance fundamental voltage utilization, and thereby improve overall power quality. The following derivations and discussions quantify these improvements and demonstrate the alignment between analytical, simulated, and experimental outcomes.

4.1. Fundamental Voltage Derivation

For an m-level inverter, the fundamental output voltage component can be derived from the Fourier expansion of the stepped waveform as

$$V_1={\displaystyle \frac{4V_{dc}}{\pi }}\sum _{k=1}^m\cos ({\theta }_k)$$

(21)

where (θ_k) represents the switching angles determined by the equal-area condition that minimizes predominant low-order harmonics (third, fifth, and seventh) and maximizes the fundamental amplitude. In the proposed hybrid modulation, these angles are dynamically updated within the field-programmable gate array (FPGA) controller, ensuring waveform symmetry and a near-sinusoidal output voltage.

4.2. Total Harmonic Distortion (THD)

The total harmonic distortion (THD) is analytically expressed as

$$THD=\sqrt{{\displaystyle \frac{{\sum }_{n=2}^{\infty }{V}_n^2}{V_1^2}}}$$

(22)

By substituting the calculated harmonic magnitudes obtained from Fourier analysis of the proposed waveform, the third and fifth harmonic components are observed to be less than 2.8%, while the seventh and higher harmonics remain below 1%. Hence, the overall total harmonic distortion (THD) is approximately 4.3%, which is a 40–45% reduction compared with conventional carrier-based PWM techniques (typically 7–8%). This analytical prediction closely agrees with the simulation and experimental spectra presented in Figures 26 and 31.

4.3. Fundamental Voltage Utilization and Efficiency

The proposed control approach enhances the effective fundamental voltage utilization to nearly 0.9 V_dc for a nine-level configuration, compared with 0.82 V_dc for standard sinusoidal PWM. As a result, the inverter delivers a higher RMS voltage to the load with reduced switching activity, leading to an increased overall conversion efficiency. The measured efficiency improvement is approximately 3–4% over comparable RCC-MLI structures.

4.4. Conduction and Switching Loss Analysis

The conduction loss per switch is given by P_cond = I_rms²R_on, while the total conduction loss per cycle is

$$P_{cond\left(total\right)}=4I_{rms}^2{R}_{on}$$

(23)

where I_rms is the RMS value of the current flowing through the device, and R_on is the on-state resistance of the IGBT/MOSFET. Since the proposed topology maintains a reduced number of conducting switches (N_on = 4) per voltage level, the total conduction loss per cycle can be estimated as

$$P_{cond\left(total\right)}=N_{on}\times I_{rms}^2{\times R}_{on}$$

(24)

Compared with conventional cascaded H-bridge or NPC inverters where six to eight devices conduct simultaneously, the proposed configuration yields approximately a 40% reduction in conduction losses for an equivalent load and device parameters.

Additionally, the hybrid carrier-less PWM technique reduces switching transitions per fundamental cycle, thus lowering the overlap period during turn-ON and turn-OFF events, which further improves conversion efficiency. Switching loss reduction directly contributes to lower semiconductor heating and reduced need for external heat sinking, improving thermal efficiency.

The efficiency (η) of the inverter is now defined in the revised text as

$$\mathsf{\eta }={\displaystyle \frac{P_{out}}{P_{out}+P_{cond(total)}+P_{sw}}}$$

(25)

The simulation results and experimental validation (Figures 29–35) confirm that the proposed inverter achieves a noticeable improvement in efficiency (≈95.2%) compared with conventional carrier-based PWM inverters (≈91.5%), primarily due to minimized conduction and switching losses.

Similarly, switching losses are minimized through the equal-area modulation technique, where the effective switching frequency is significantly lower than that of traditional multicarrier PWM. Substituting the practical switching parameters (V_sw = 100 V, I_sw = 2 A, ton + toff ≈ 400 ns, and f_sw = 2 kHz) yields an approximate switching loss reduction of 35%.

The conduction and switching losses are now derived based on the electrical characteristics of the selected IGBT device IRG4BC20SD. The conduction loss per switch is expressed as

$$P_{cond}={\displaystyle \frac{i}{T}}{\int }_0^T{V}_{CE\left(sat\right)}\left(i\left(t\right)\right).i\left(t\right)dt$$

(26)

where $V_{CE(sat)}(i)$ is the current-dependent collector–emitter saturation voltage approximated by

$$V_{CE\left(sat\right)}\left(i\right)=a+b.i+c.i^2$$

(27)

with constants $a=0.7 \mathrm{V}, b=0.015 \mathrm{V}/\mathrm{A}, \mathrm{a}\mathrm{n}\mathrm{d} c=0.0002{ \mathrm{V}/\mathrm{A}}^2$ obtained through MATLAB curve fitting from the manufacturer’s datasheet.

The switching loss for each device is modeled as

$$P_{sw}=f_{sw}\left(E_{on}+E_{off}\right)=f_{sw}\left(k_1{i}_{sw}{V}_{DC}+k_2{i}_{sw}^2\right)$$

(28)

where $E_{on}$ and $E_{off}$ are the turn-ON and turn-OFF energies derived from empirical switching energy curves for IRG4BC20SD at $V_{DC}=100 \mathrm{V}$ and $I_{sw}=2 \mathrm{A}$. The constants $k_1=3.6\times {10}^{-6}$ and $k_2=2.1\times {10}^{-7}$ were determined experimentally.

The total power loss per cycle is then expressed as

$$P_{total}=N_{on}.P_{cond}+N_{sw}.P_{sw}$$

where $N_{on}=4$ and $N_{sw}$ represent the number of conducting and switching devices per fundamental cycle, respectively.

This refined analysis demonstrates that the total conduction and switching losses decrease by approximately 38–42% compared with conventional cascaded H-bridge MLIs.

4.5. EMI and Dynamic Performance

Because the proposed carrier-less strategy employs fewer transitions and smaller voltage steps per commutation, the rate of voltage change (dv/dt) is limited, thus suppressing electromagnetic interference (EMI). The symmetrical pulse placement ensures cancellation of common-mode voltages. Furthermore, field-programmable gate array (FPGA)-based real-time control enables near-instantaneous duty-cycle adjustments, enhancing dynamic response under sudden load variations. The FPGA-based closed-loop modulation dynamically adjusts switching instants in real-time, compensating for reactive energy stored in inductive and capacitive components. This adaptive control ensures minimal overshoot and fast recovery under sudden load or source variations (Figure 17).

Figure 17. Dynamic performance.

4.6. Power Quality and Filter Design

The analytical results confirm that the elimination of low-order harmonics significantly reduces the reactive component of the load current, thereby easing the design of output filters. The LC-filter cut-off frequency is selected to be slightly above the dominant switching frequency to ensure harmonic attenuation without compromising the transient response. Consequently, the filter size and losses are reduced by about 20% compared with equivalent conventional designs.

4.7. Output-Voltage Regulation Mechanism

The proposed inverter regulates its output voltage through modulation-index adjustment within the equal-area hybrid PWM framework. For a given DC-link voltage VDCV_{DC}VDC, the desired fundamental RMS output voltage Vo,1 is controlled by modifying the modulation index (m), which directly scales the pulse widths generated by the equal-area computation.

In every switching interval, the algorithm computes the pulse width Δti such that the average value of the output voltage equals the instantaneous reference V_ref(t) = mV_max sin(ωt). By varying mmm between 0 and 1, the inverter proportionally adjusts the effective RMS output voltage without altering the hardware configuration.

When load or source variations occur, the field-programmable gate array (FPGA) controller recalculates the equal-area pulse durations in real time to maintain the specified modulation index, thereby preserving the output voltage amplitude. Since only four switches conduct at any time, the system maintains stable voltage regulation with minimal distortion and switching stress.

This analytical modulation-based regulation eliminates the need for external PI or hysteresis control loops, simplifying implementation while ensuring a consistent voltage magnitude across different operating conditions.

4.8. Limitations of Carrier-Less Modulation

Although the carrier-less approach simplifies implementation, it may experience reduced precision under a highly dynamic load or asymmetrical DC-source conditions. The proposed algorithm mitigates these effects using analytically determined switching angles and symmetric voltage synthesis, while future work will focus on adaptive modulation to further enhance dynamic performance.

4.9. Analytical Validation and Discussion

The analytical derivations for harmonic analysis in Equations (21)–(24) are validated against simulation and experimental results summarized in Table 4. The close correlation between analytical THD (4.3%) and experimental THD (4.5%) confirms the reliability of the proposed carrier-less modulation. Additionally, the proposed hybrid PWM’s equal-area formulation ensures mathematical equivalence between reference and actual output voltages, providing a rigorous analytical foundation for the observed power quality improvements.

5. Proposed Simulation Outcomes

The effectiveness of the developed hybrid carrier-less PWM strategy was validated through extensive MATLAB 2018/Simulink simulations of the proposed triple-source RCC-MLI. The developed algorithm was implemented for a nine-level inverter configuration using IGBT switches, with the DC inputs modeled as constant DC sources. An R–L load of 100 Ω and 100 mH was employed to evaluate its dynamic and steady-state behavior.

To benchmark performance, the proposed amalgamated PWM technique was compared with the traditional multicarrier PWM (MCPWM) and carrier-less PWM (CLPWM) methods. For MCPWM, the switching frequency was set at 1 kHz with a modulation index of m = 1, producing five pulses per fundamental half-cycle. In the CLPWM and proposed hybrid schemes, the same pulse count (five per half-cycle) was maintained, but the pulse widths were determined analytically from Equations (1)–(7) to ensure area equivalence with the desired sine waveform. The pulse positions were computed using the centroid method, enabling lower harmonic distortion and uniform spectral distribution.

The simulations were conducted for a DC-link voltage of 100 V and a switching frequency of 2 kHz. Figure 18, Figure 19, Figure 20, Figure 21, Figure 22, Figure 23, Figure 24, Figure 25, Figure 26, Figure 27, Figure 28 and Figure 29 illustrate the simulated gating pulses, output voltage, load current, and corresponding harmonic spectra under different modulation indices (m = 0.8–1.0). The generated output voltage exhibits evenly spaced steps, confirming symmetrical voltage synthesis and balanced utilization of the DC sources. The output current waveform for the R–L load is nearly sinusoidal, verifying smooth current commutation through the bidirectional switches.

Figure 18. Simulated output voltage waveform of the proposed inverter showing 21 distinct levels. The voltage steps are evenly distributed with minimized harmonic distortion. The inset shows the corresponding switching states for one cycle.

Figure 19. Simulated output current waveform for a resistive–inductive (R–L) load. The waveform confirms smooth current transitions and continuous conduction without interruption, demonstrating the effectiveness of bidirectional switches and anti-parallel diodes.

Figure 20. Simulated output voltage spectrum of the traditional area-equalized PWM (AEPWM) method, showing dominant low-order harmonics before optimization.

Figure 21. Output voltage waveform obtained using the proposed amalgamated area-equalized fundamental-switching PWM (A2EFSPWM) technique. The waveform exhibits uniform voltage steps and reduced distortion.

Figure 22. Inductive load current response under the A2EFSPWM method. The current remains continuous and nearly sinusoidal, confirming smooth commutation and proper conduction through bidirectional switches.

Figure 23. Frequency-domain spectrum of the A2EFSPWM output voltage. The magnitudes of the 5th, 7th, 11th, and 13th harmonics are substantially reduced, resulting in improved total harmonic distortion (THD).

Figure 24. Output voltage waveform generated by the amalgamated fundamental-switching area-equalized PWM (AFSAEPWM) method, demonstrating balanced step transitions and high-quality voltage synthesis.

Figure 25. Inductive load current corresponding to the AFSAEPWM technique. The waveform closely follows a sinusoidal profile with negligible distortion, validating the harmonic suppression capability.

Figure 26. Nine-level inverter, (a) output voltage, and (b) inductive load current waveform for change in load condition.

Figure 27. Output voltage FFT spectrum for the AFSAEPWM method showing elimination of low-order harmonics and overall THD reduction below 5%.

Figure 28. Comparison of the fundamental output voltage amplitude versus total harmonic distortion (THD) for different PWM strategies. The proposed hybrid PWM achieves the lowest THD at a near-unity modulation index.

Figure 29. Variation in harmonic magnitudes between the conventional area-equalized modulation (AEM) and the proposed hybrid PWM methods. The hybrid approach exhibits significantly lower low-order harmonic content, confirming enhanced spectral performance.

6. Experimental Studies

To validate the analytical and simulation outcomes, a laboratory prototype of the proposed triple-source reduced-component-count multilevel inverter (RCC-MLI) was developed and tested under controlled conditions. The experimental setup, shown in revised Figure 30, was powered by three equal DC sources rated at 33 V each, providing a total DC-link voltage of approximately 100 V. A resistive–inductive (R–L) load of 100 Ω and 100 mH was employed to emulate practical operating conditions.

Figure 30. Experimental test bench of the proposed triple-source RCC-MLI showing field-programmable gate array (FPGA) controller, gate driver circuits, IGBTs, and measurement instruments.

The gating signals were generated using a Xilinx Spartan-3E field-programmable gate array (FPGA) development board operating at a 50 MHz clock frequency. IRG4BC20SD IGBTs, driven by IR2110 gate-driver circuits, were used as the power-switching devices to ensure fast and reliable commutation.

The output voltage and current waveforms were captured using a Tektronix TDS 2024C Digital Storage Oscilloscope (with a 200 MHz bandwidth and a 2 GS/s sampling rate), while the harmonic content and efficiency were evaluated with a Fluke 43B Power Analyzer for accurate total harmonic distortion (THD) and power-quality assessment.

Revised Figure 30, Figure 31, Figure 32, Figure 33, Figure 34 and Figure 35 present the measured voltage and current waveforms for various modulation conditions. The experimental results exhibit excellent agreement with the simulation predictions, confirming precise voltage synthesis and robust harmonic suppression. The continuous current conduction through the inductive load verifies the correct operation of bidirectional switches and anti-parallel diodes during commutation (Table 3).

Figure 31. (a) Experimental PWM gating pattern for the A2EFSPWM method during the positive half-cycle, showing properly sequenced switching pulses generated by the FPGA controller. (b) Experimental PWM gating pattern for the A2EFSPWM method during the negative half-cycle. The symmetrical pulse arrangement confirms balanced conduction for both half-periods. (c) Composite PWM circulation pattern for the A2EFSPWM strategy combining both half-cycles, illustrating equal-area modulation and synchronized gate triggering. (a–c) Experimental PWM gating patterns for the proposed amalgamated area-equalized fundamental-switching PWM (A2EFSPWM) method. Subfigures (a,b) show the positive and negative half-cycle pulse patterns, respectively, while (c) presents the composite full-cycle pulse circulation. The symmetrical pulse distribution confirms correct FPGA-based modulation and balanced conduction throughout the fundamental cycle.

Figure 32. Experimental output voltage waveform for the A2EFSPWM method. The measured stepped waveform demonstrates accurate level synthesis and minimal distortion.

Figure 33. FFT spectrum of the experimental output voltage obtained using A2EFSPWM. The low-order harmonics (5th, 7th, 11th, and 13th) are effectively suppressed, yielding a total harmonic distortion (THD) of approximately 4.5%.

Figure 34. (a) Experimental PWM gating pattern for the AFSAEPWM technique in the positive half-cycle, generated through the hybrid carrier-less modulation approach. (b) Experimental PWM gating pattern for the AFSAEPWM method during the negative half-cycle, showing a symmetrical pulse distribution and correct timing alignment. (c) Full-cycle PWM pulse sequence for the AFSAEPWM technique, verifying synchronized operation of positive and negative intervals under equal-area control. Figure (a–c) Experimental PWM gating patterns for the amalgamated fundamental-switching-area-equalized PWM (AFSAEPWM) method. Subfigures (a,b) show positive and negative half-cycle patterns, while (c) illustrates the full-cycle PWM circulation. The hybrid carrier-less modulation ensures synchronized switching and symmetry between conduction intervals.

Figure 35. Experimental output voltage waveform for the AFSAEPWM method. The stepped waveform exhibits uniform voltage intervals and high waveform fidelity.

Table 3. Simulation and experimental parameters.

Parameter	Symbol/Description	Value/Range
DC source voltages	VDC1, VDC2, and VDC3	33 V each (total 100 V DC link)
Load resistance	R	100 Ω
Load inductance	L	100 mH
Switching frequency	few	2 kHz
Modulation index	m	0.8−1.0
Number of output levels	-	9 levels
Controller	-	Xilinx Spartan-3E FPGA (50 MHz)
Power devices	-	IRG4BC20SD IGBTs
Gate driver ICs	-	R2110I
Oscilloscope	-	Tektronix TDS2024C (200 MHz, 2 GS/s)
Power analyzer	-	Fluke 43B

Quantitatively, the measured THD of the output voltage was 4.5%, closely matching the simulated value of 4.3%, while the prototype efficiency reached 95.2%, validating the low-loss characteristics predicted analytically. The inverter operated with negligible voltage overshoot, smooth switching transitions, and stable waveform symmetry, demonstrating its effectiveness for renewable energy systems, electric vehicle drives, and medium-power industrial applications.

Minor deviations between the experimental and simulated data were attributed to switching delays, parasitic resistances, and non-idealities in the IGBTs (Table 4).

Table 4. Confirmation of excellent correlation between simulation and experimental results.

Parameter	DC Bus (VDC)	Modulation Index (m)	Switching Frequency (fs, kHz)	Load R–L (Ω–mH)	Simulation	Experimental	Absolute Error	Relative Error (%)
THD (%)	100	1.0	2.0	100—100	4.3	4.5	0.2	4.65
Efficiency (%)	100	1.0	2.0	100—100	95.4	95.2	0.2	0.21
Fundamental RMS voltage (V)	100	1.0	2.0	100—100	70.8	69.7	1.1	1.55
Peak voltage stress (% of VDC)	100	1.0	2.0	100—100	45.0	46.2	1.2	2.67
Switching frequency (kHz)	100	1.0	2.0	100—100	2.0	2.0	0	0

A fixed dead-time of 2 µs was implemented in the FPGA gating logic to avoid shoot-through conditions and minimize low-order harmonic distortion. The PWM generation module utilized approximately 1200 LUTs and 850 flip-flops on the Spartan-3E FPGA, operating at 50 MHz.

The experimental waveforms (Figure 31, Figure 32, Figure 33, Figure 34, Figure 35 and Figure 36) confirmed continuous current flow during switching transitions. The observed absence of current interruption validates the functionality of bidirectional switches and carrier-less modulation under inductive load conditions.

Figure 36. Measured output voltage spectrum corresponding to the AFSAEPWM technique. The spectrum reveals strong suppression of low-order harmonics, confirming enhanced power quality and reduced total harmonic distortion (THD).

The specifications of the components used in the prototype are summarized in Table 5 and filtering elements employed in the prototype are presented in Table 2. These selections ensure proper voltage and current ratings, reliable switching, and stable operation under the rated load conditions.

Table 5. The detailed specifications of the power semiconductor devices, gate driver units, controller, and filtering elements employed in the prototype are presented below.

Component Type	Description/Part Number	Key Specifications/Ratings	Remarks/Function
Semiconductor devices	IGBT—IRG4BC20SD	VCES = 600 V, IC = 20 A, and Ron = 0.18 Ω	Used as main switching devices for both unidirectional and bidirectional paths Two IGBTs configured in common-emitter form act as bidirectional switches
Gate driver IC	IR2110 high- and low-side driver	Input logic = 3.3–5 V; output = up to 600 V	Provides level-shifted gate pulses to the IGBT; isolates control and power circuits
PWM controller	Xilinx Spartan-3E FPGA board	50 MHz clock; 32 I/O pins	Generates digital carrier-less PWM pulses using LUT-based sine reference patterns
PWM controller	Rectified single-phase supply	230 V AC; 50 Hz→100 V DC after filtering	Provides input DC voltage for triple-source module
Filter inductor (L)	Air-core inductor	100 mH	Smooths load current and attenuates switching harmonics
Filter resistor (R)	Power resistor	100 Ω	Represents the load and defines the current magnitude during experiments
Capacitor (optional for filtering)	Electrolytic capacitor	470 μF/250 V	Used to stabilize the DC bus and suppress ripple voltage
Measurement equipment	Measurement equipment	100 MHz bandwidth; isolated voltage/current probes	-

A comparative evaluation of the proposed triple-source reduced-component MLI against recently reported topologies is presented in Table 6.

Table 6. A comparative evaluation of the proposed triple-source reduced-component MLI against recent topologies reported in [19,20,21,22,23,24,25,26].

Parameter	CHB MLI [19]	NPC MLI [20]	Switched-Capacitor MLI [21]	Asymmetric MLI [22]	Proposed Triple-Source RCC-MLI
No. of voltage levels (example)	21	17	17	22	21
No. of switches	36	28	28	20	11
No. of gate drivers	36	28	28	18	9
No. of DC sources/capacitors	7 DC + balancing caps	5 DC + 10 caps	5 DC + 10 caps	4 DC	3 DC (triple-source module)
Peak voltage stress (% of Vdc)	100%	80%	80%	65%	≈45%
THD (%)	8.20%	7.60%	7.60%	6.20%	4.30%
Efficiency (%)	91.00%	92.50%	92.50%	93.80%	95.20%
Component reduction ratio	-	1	1	1.4	1.8
PWM control type	Multicarrier SPWM	Level-shifted PWM	Level-shifted PWM	SHE-PWM	Carrier-less hybrid PWM (A2EFSPWM/AFSAEPWM)
Special features	Modular design	Neutral point	Neutral point	Flexible DC ratios	Minimal components; high waveform quality

The proposed configuration achieves a 45% reduction in switching devices and gate drivers compared with existing reduced-component-count multilevel inverters (RCC MLIs), while maintaining lower voltage stress (≈45% Vdc) and achieving the lowest THD (4.3%). Owing to the carrier-less hybrid PWM control and minimized conduction paths, the overall inverter efficiency improves to 95.2%. These results confirm the superiority of the proposed system in terms of component economy, harmonic performance, and conversion efficiency (Table 7).

Table 7. Comparative performance analysis of PWM strategies.

Parameter	Traditional AEPWM	Carrier-Less CLPWM	Proposed Hybrid PWM (RCC-MLI)
THD (%)	8.2	6.7	4.3
Efficiency (%)	91.5	93	95.2
Switching frequency (kHz)	5	2	2
Common-mode voltage (V)	22	18	10
Peak device voltage stress (% of Vdc)	70	60	45
No. of conducting switches per cycle	6	5	4
Computation complexity	High	Moderate	Low (FPGA lookup)

7. Conclusions

This paper presented a novel triple-source reduced-component-count multilevel inverter (RCC-MLI) integrated with a carrier-less hybrid pulse-width modulation (PWM) strategy for enhanced power conversion performance. The proposed cross-connected configuration substantially minimizes the number of semiconductor switches and gate drivers required for a given output voltage level. Only four switches conduct at any instant, achieving approximately a 33% reduction in semiconductor devices compared with conventional MLIs of similar voltage ratings.

Comprehensive analytical modeling, MATLAB/Simulink simulations, and experimental validation on a nine-level prototype confirmed the feasibility and accuracy of the design. The proposed hybrid PWM algorithm based on the equal-area criterion eliminates the need for carrier and reference waveforms, simplifying real-time digital implementation while maintaining smooth and symmetric voltage generation. The inverter also achieves a higher effective switching frequency without increasing individual device commutations, thus improving waveform linearity and reducing harmonic distortion.

Quantitative analysis shows that the proposed topology achieves a total harmonic distortion (THD) reduction from 8.2% to 4.3% and an efficiency improvement from 91.5% to 95.2%, compared with conventional multicarrier PWM-based MLIs. The blocking voltage across each device is limited to approximately 45% of the total DC-link voltage, reducing device stress and enhancing long-term reliability. Experimental waveforms closely match analytical and simulated predictions, confirming excellent harmonic suppression, continuous current conduction under inductive loading, and an improved dynamic response.

The reduced component count, simplified gating structure, minimized switching losses, and FPGA-based real-time control make the proposed inverter highly suitable for renewable-energy interfaces, medium-power industrial drives, and electric vehicle powertrains.

Future research will focus on extending the proposed topology to three-phase configurations, higher voltage and power levels, and grid-connected applications. Additionally, advanced adaptive and bidirectional PWM control techniques will be explored to optimize harmonic performance and efficiency under varying source and load conditions. These developments are expected to further enhance the inverter’s potential for deployment in next-generation clean-energy systems and smart electric drive applications.