A New Asymmetric H-6 Structured Multilevel Inverter with Reduced Power Components

Abstract

Multilevel inverters play a key role in improving the power quality for industrial, domestic, and renewable energy sectors due to sinusoidal output voltage through small voltage steps, lesser THD (total harmonic distortion), and EMI (electromagnetic interference). There are several variants in MLI structures to generate a stepped voltage with their own operating characteristics, which flaws in switching devices with gate drivers, current conducting switches varied with varied voltage levels, and switches with different abilities in blocking voltagesto overcome increases in implementation costs and restrict its usage in high-power applications. Therefore, this article paves a solution for the above problem, which orients a new structure for asymmetric operation to propel large voltage levels with small values of switches in parallel with conventional topologies. The subtlety of the proposed topology is governed by a multicarrier pulse width modulation scheme, and ten different voltage magnitude algorithms are developed and compared foreffectiveness.Hitherto, many existing MLI topologies with reduced power switches have beendeveloped; among these, the H6 structure attempts to curtail the reduced conduction path. The operation of the suggested topology is confirmed in a Matlab/Simulink environment, and real-time performance is investigated using a laboratory prototype to accord the simulated results.

1. Introduction

The multilevel inverter (MLI) is an alternative solution for three-leg inverters in industrial and utility applications owing to several merits like high-quality output voltage, lower THD, lesser dv/dt, and lower EMI [1,2,3]. In multilevel inverters, the output quality is enriched by raising the number of steps in the load voltage waveform. This increases the number of DCpower sources, DC-link capacitors, and power switches, which increases the cost and accrues diligent control methods. Several remarkable topologies playa significant role in industrial adjustable speed drives and renewable energy applications [4,5,6]. The cascaded H-bridge inverters find extensive use in industrial drivers due to their modular structure, fault-tolerant recovery capability, and exemption from capacitor voltage balancing issues. However, they require a higher count of input DC power supplies and switching devices with voltage steps [7]. A new topology using a single DC source for a grid-connected PV system is introduced to achieve higher voltage levels using the level doubling concept. The developed system is composed of a single DC source-fed full bridge inverter and capacitor-fed half bridge leg to complete the entire system for grid interface applications [8]. A new 49-level inverter is developed using two packed U-cell structures sharing a common DC source through a high-frequency link. This topology needs a small number of switches, and a typical design is required for a high-frequency link transformer [9]. A pair of DC sources and capacitors with several switches form a 9-level inverter, and the topology looks simple in its state of operation. However, capacitor voltage balancing is not portrayed to obtain balanced voltage levels [10]. A topology using six unidirectional switches and one bidirectional switch to generate 7- and 11-level output voltages, respectively, is formulated for renewable energy applications. This topology is extended to produce more voltage levels in cascaded connections [11]. A new hybrid cascaded topology for medium and high voltage applications is introduced using six switches, three identical DClinks, and two blocking voltages. This topology produces six positive voltage states and negative voltage states are acquired through an H-bridge inverter [12]. A modified MLI topology for an asymmetrical structure using ten switches and four DC sources is used to achieve 21-level output on the inverter output side. This topology claims it is modular and impacts high power quality [13]. A new asymmetrical voltage source input topology is constructed using four DC sources and nine switches to obtain seventeen voltage levels. The topology with a cascaded structure produces voltage levels with less stress on the switches used in the proposed structure [14]. A topology with three different voltage sources and ten switches to generate a 15-level voltage for renewable and industrial applications is presented to offer a new structure in reduced count topologies [15]. A couple of DC sources and a capacitor areused to form a new MLI to generate a stepped output voltage. The topology uses fewerswitches and DC sources to offer higher voltage levels [16]. A module consists of a single DC source and a capacitor connected through seven switches to generate voltage levels. The structure can be extended with different voltage values in the voltage source to cascade with the basic symmetrical structure with the same number of switches doubled while cascading to achieve higher voltage levels. The topology requires suitable control for balancing the capacitor voltages [17]. A switched capacitor MLI is developed to overcome the drawbacks of the traditional cascaded H-bridge inverter with the use of a single DC source and DC capacitors. However, the topology suffers from a sudden rush in current in switched capacitors, and this problem is alleviated through charging inductors [18]. A switched DC source MLI is conceived using three DC sources and five switches. The topology generates all possible voltage levels with a series of a half-bridge cell and an H-bridge inverter. The topology requires high blocking voltage switches in the H-bridge inverter, and the value rises with an increase in voltage levels [19]. A switched inductor Z-source network is incorporated with the traditional MLI to exploit the properties of less THD and low electromagnetic interference [20]. A CHBMLI using a single DC source and a reduced number of transformers for active filter applications is developed to enjoy the merits of elimination of harmonics during nonlinear loads. However, the objective of diminishing the cost of switches and DC sources in developed topology increases the size of coupling transformers [21]. A CHBMLI is connected in a three-phase configuration that employs a single DC source and floating capacitors per phase. The floating capacitors serve the purpose of a level-doubling network without the use of a closed-loop control. The capacitor voltage of each H-bridge is equal to half; the voltage of the preceding H-bridge claiming binary asymmetric ratio is another advantage [22]. The arrangement of DC sources and capacitors in ‘E’ and ‘F’ shapesoffers reduced power components in the MLI structure, ‘E’ module helpsthe capacitor voltage divider to double the voltage levels. The capacitor voltages are balanced without complex control methods [23]. A dual DC source and a series of capacitors with several switches to fetch the stepped DC voltage and an H-bridge inverter areused to attain all voltage levels. The structure is nonmodular and a capacitor voltage balancing method is required [24]. A switched capacitor-based MLI structure usesa single DC source and fewer switches, diodes, and capacitors to claim a reduced power component in the MLI family. The DC capacitors are charged in a trinary ratio to result in a DC-boosted voltage [25]. A novel structure using three DC sources and eight switches to generate a stepped DC voltage and an H-bridge inverter is used to attain a stepped AC voltage level. The topology uses several modules to enrich the voltage levels [26]. A new MLI based on several subcellsis made from two DC sources and six switches, and it produces a 125-level asymmetrical configuration. The MLI uses less subcells to emulate CHBMLI with asymmetric voltage sources for enhancing the output voltage levels [27]. A new MLI using four DC sources is arranged in a hut-shaped structure to accumulate a 15-level stepped voltage. The topology uses only three DC sources in their modes of operation and one DC source falls under an unused state [28]. An H-bridge type module is made up of three DC sources and several switches to achieve stepped voltage. The topology is cascaded with several modules to improve voltage levels and reduce stress on the switches [29]. A transistor-clamped double DC source with an H-bridge is developed for solar energy applications and the topology appears similar to traditional transistor-clamped topologies [30].

In this context, a new topology is generalized to achieve possible voltage levels using reduced switches with less blocking voltage. The topology is developed to configure asymmetrical voltage sources to reach maximum voltage levels. There are nine different voltage methods that have been introduced to check the viability of the developed topology in asymmetrical configurations.

This paper is organized as follows: In Section 1, the focus is on exploring recent advancements in multilevel inverters. Section 2 demonstrates the planned proposed asymmetric H-6 topology and different operating modes. Section 3 involves delving into simulations and experimental investigations, engaging in a thorough comparative study that encompasses an analysis of other referenced topologies. Section 4 describes theconclusion and possible application.

2. Proposed Topology

In recent years, MLIs have had footprints in renewable energy sectors due to their inherent ability to produce good quality pole voltages in terms of small steps through low voltage sources and power structures formulated with fast-switching semiconductor switches tied to utility grids. This structure elevates the pole voltage in a shape closer to a sinusoid, which eliminates low-frequency harmonics naturally without the use of low-pass filters. However, the structures pertaining to outward pole voltage from small voltage steps require a larger number of switching devices with an increase in voltage steps. The conventional MLI structure is limited within the applications in medium voltage ranges, which are put forward to formulate new structures in MLI topology with fewer power components.

In order to produce more voltage levels, a newly developed MLI structure pictured in Figure 1, which comprises a string of isolated DC input sources (V_d1–V_dn) and (V_d1′–V_dn′) on either side of the H-6 inverter to produce all possible values of V_d1. The DC sources (V_d1–V_dn and V_d1′–V_dn′) utilize the switches (S_d1–S_dn & S_d1′–S_dn′) for generating voltage steps, and the switches _(SH1-SH6) change the polarity of generated voltage. The voltage source (V_d1) decides the minimum step in the load voltage while the remaining voltage sources (V_d2–V_dn and V_d1′–V_dn′) produce voltage steps in multiples of voltage source magnitude (V_d1) in the output voltage. The switching devices (S_se, S_se′ and S_ad) are used to add and subtract the voltage sources (V_d1′–V_dn′) from (V_d1–V_dn). Figure 2 portrays the operating modes to produce different steps of load voltage. The input voltage sources for the developed topology areacquired possibly from PV (photovoltaic) panels or FC (fuel cells) or any other storage elements like capacitors or batteries. In the suggested topology, a maximum of four switches in the level generation side functioning at PWM and three switches in the H-bridge operating at fundamental switching necessitate less switching loss. Hybrid PWM may also be employed to perform PWM operations in H-bridge inverters and fundamental switching in the proposed MLI structure in the proposed hybrid inverter to reduce power loss. The number of voltage sources, switches, and voltage levels are related by (n), [n + 9], and [(6 × n) + 3], where (n > 1) is the number of isolated DC input sources.

Since the proposed structure is an asymmetrical topology, there is a possibility of taking different voltage source values to elucidate the objective of attaining more voltage levels. Nine algorithms have been formulated to derive the values of source voltages to operate in the asymmetrical mode. The algorithms have been coined for the proposed structure with four DC sources (V_d1, V_d2, V_d1′, V_d2′) in a cascaded connection.

Table 1. Mathematical relations to determine various parameters using proposed voltage source algorithms.

Algorithm	Voltage Sources Values and Max. Output Voltage	No. of Voltage Levels	Blocking Voltage
Proposed Algorithm 1	${\mathrm{V}}_{\mathrm{d}(1,\mathrm{j})}={\mathrm{V}}_{\mathrm{d}(2,\mathrm{j})}={\mathrm{V}}_{\mathrm{d}(1,\mathrm{j})}{}^{\prime }={\mathrm{V}}_{\mathrm{d}(2,\mathrm{j})}{}^{\prime }={\mathrm{V}}_{\mathrm{dc}}$ ${\mathrm{V}}_{\mathrm{om}}={4\mathrm{nV}}_{\mathrm{dc}}$	(8 × n) + 1	27nVdc
Proposed Algorithm 2	${\mathrm{V}}_{\mathrm{d}(1,\mathrm{j})}={\mathrm{V}}_{\mathrm{d}(2,\mathrm{j})}={\mathrm{V}}_{\mathrm{dc}}{;\mathrm{V}}_{\mathrm{d}(1,\mathrm{j})}{}^{\prime }={\mathrm{V}}_{\mathrm{d}(2,\mathrm{j})}{}^{\prime }=2{\mathrm{V}}_{\mathrm{dc}}$ ${\mathrm{V}}_{\max }={6\mathrm{nV}}_{\mathrm{dc}}$	(12 × n) + 1	44nVdc
Proposed Algorithm 3	${\mathrm{V}}_{\mathrm{d}(1,1)}={\mathrm{V}}_{\mathrm{d}(2,1)}={\mathrm{V}}_{\mathrm{dc}}{;\mathrm{V}}_{\mathrm{d}(1,1)}{}^{\prime }={\mathrm{V}}_{\mathrm{d}(2,1)}{}^{\prime }=2{\mathrm{V}}_{\mathrm{dc}}$ ${\mathrm{V}}_{\mathrm{d}(1,\mathrm{j})}={\mathrm{V}}_{\mathrm{d}(2,\mathrm{j})}={\mathrm{V}}_{\mathrm{d}(1,\mathrm{j})}{}^{\prime }={\mathrm{V}}_{\mathrm{d}(2,\mathrm{j})}{}^{\prime }=2^{\mathrm{j}-1}{\mathrm{V}}_{\mathrm{dc}}$ ${\mathrm{V}}_{\max }=6{\displaystyle \sum _{\mathrm{j}=1}^{\mathrm{n}}{2}^{\mathrm{j}-1}}{\mathrm{V}}_{\mathrm{dc}}$	$12{\displaystyle \sum _{\mathrm{j}=1}^{\mathrm{n}}{2}^{\mathrm{j}-1}}+1$	44Vdc; n = 1 [44 + (5 × 2n) + (17 × 2n − 1)] × Vdc; n > 1
Proposed Algorithm 4	${\mathrm{V}}_{\mathrm{d}(1,1)}={\mathrm{V}}_{\mathrm{d}(2,1)}={\mathrm{V}}_{\mathrm{d}(1,1)}{}^{\prime }={\mathrm{V}}_{\mathrm{d}(2,1)}{}^{\prime }={\mathrm{V}}_{\mathrm{dc}}$ ${\mathrm{V}}_{\mathrm{d}(1,\mathrm{j})}={\mathrm{V}}_{\mathrm{d}(2,\mathrm{j})}={\mathrm{V}}_{\mathrm{d}(1,\mathrm{j})}{}^{\prime }={\mathrm{V}}_{\mathrm{d}(2,\mathrm{j})}{}^{\prime }=3^{\mathrm{j}-1}{\mathrm{V}}_{\mathrm{dc}}$ ${\mathrm{V}}_{\max }=4{\displaystyle \sum _{\mathrm{j}=1}^{\mathrm{n}}{3}^{\mathrm{j}-1}}{\mathrm{V}}_{\mathrm{dc}}$	$8{\displaystyle \sum _{\mathrm{j}=1}^{\mathrm{n}}{3}^{\mathrm{j}-1}}+1$	27Vdc; n = 1 27 × [1 + 3n − 1] × Vdc; n > 1
Proposed Algorithm 5	${\mathrm{V}}_{\mathrm{d}(1,1)}={\mathrm{V}}_{\mathrm{d}(2,1)}={\mathrm{V}}_{\mathrm{d}(1,1)}{}^{\prime }={\mathrm{V}}_{\mathrm{d}(2,1)}{}^{\prime }={\mathrm{V}}_{\mathrm{dc}}$ ${\mathrm{V}}_{\mathrm{d}(1,\mathrm{j})}={\mathrm{V}}_{\mathrm{d}(2,\mathrm{j})}=2^{\mathrm{j}-1}{\mathrm{V}}_{\mathrm{dc}}{;\mathrm{V}}_{\mathrm{d}(1,\mathrm{j})}{}^{\prime }={\mathrm{V}}_{\mathrm{d}(2,\mathrm{j})}{}^{\prime }=2{\mathrm{V}}_{\mathrm{d}(1,\mathrm{j})}$ $\begin{array}{l}{\mathrm{V}}_{\max }={4\mathrm{V}}_{\mathrm{dc}};\mathrm{n}=1\\ {\mathrm{V}}_{\max }=6{\displaystyle \sum _{\mathrm{j}=2}^{\mathrm{n}}{(2}^{\mathrm{j}-1}+4)}{\mathrm{V}}_{\mathrm{dc}};\mathrm{n}\ne 1\end{array}$	$12{\displaystyle \sum _{\mathrm{j}=2}^{\mathrm{n}}{2}^{\mathrm{j}-1}}+9;\mathrm{n}\ne 1$	27Vdc; n = 1 [27 + (22 × 2n] × Vdc; n > 1
Proposed Algorithm 6	${\mathrm{V}}_{\mathrm{d}(1,1)}={\mathrm{V}}_{\mathrm{d}(2,1)}={\mathrm{V}}_{\mathrm{d}(1,1)}{}^{\prime }={\mathrm{V}}_{\mathrm{d}(2,1)}{}^{\prime }={\mathrm{V}}_{\mathrm{dc}}$ ${\mathrm{V}}_{\mathrm{d}(1,\mathrm{j})}={\mathrm{V}}_{\mathrm{d}(2,\mathrm{j})}=3^{\mathrm{j}-1}{\mathrm{V}}_{\mathrm{dc}}{;\mathrm{V}}_{\mathrm{d}(1,\mathrm{j})}{}^{\prime }={\mathrm{V}}_{\mathrm{d}(2,\mathrm{j})}{}^{\prime }=2{\mathrm{V}}_{\mathrm{d}(1,\mathrm{j})}$ $\begin{array}{l}{\mathrm{V}}_{\max }={4\mathrm{V}}_{\mathrm{dc}};\mathrm{n}=1\\ {\mathrm{V}}_{\max }=6{\displaystyle \sum _{\mathrm{j}=2}^{\mathrm{n}}{(3}^{\mathrm{j}-1}+4)}{\mathrm{V}}_{\mathrm{dc}};\mathrm{n}\ne 1\end{array}$	$12{\displaystyle \sum _{\mathrm{j}=2}^{\mathrm{n}}{3}^{\mathrm{j}-1}}+9;\mathrm{n}\ne 1$	27Vdc; n = 1 [27 + (44 × 3n − 1] × Vdc; n > 1
Proposed Algorithm 7	${\mathrm{V}}_{\mathrm{d}(1,1)}={\mathrm{V}}_{\mathrm{d}(2,1)}={\mathrm{V}}_{\mathrm{d}(1,1)}{}^{\prime }={\mathrm{V}}_{\mathrm{d}(2,1)}{}^{\prime }={\mathrm{V}}_{\mathrm{dc}}$ ${\mathrm{V}}_{\mathrm{d}(1,\mathrm{j})}={\mathrm{V}}_{\mathrm{d}(2,\mathrm{j})}={\mathrm{V}}_{\mathrm{d}(1,\mathrm{j})}{}^{\prime }={\mathrm{V}}_{\mathrm{d}(2,\mathrm{j})}{}^{\prime }=4^{\mathrm{j}-1}{\mathrm{V}}_{\mathrm{dc}}$ ${\mathrm{V}}_{\max }=4{\displaystyle \sum _{\mathrm{j}=1}^{\mathrm{n}}{4}^{\mathrm{j}-1}}{\mathrm{V}}_{\mathrm{dc}}$	$8{\displaystyle \sum _{\mathrm{j}=1}^{\mathrm{n}}{4}^{\mathrm{j}-1}}+1$	34Vdc; n = 1 27 × [1 + 4n − 1] × Vdc; n > 1
Proposed Algorithm 8	${\mathrm{V}}_{\mathrm{d}(1,\mathrm{j})}={\mathrm{V}}_{\mathrm{d}(2,\mathrm{j})}=5^{\mathrm{j}-1}{\mathrm{V}}_{\mathrm{dc}}{;\mathrm{V}}_{\mathrm{d}(1,\mathrm{j})}{}^{\prime }={\mathrm{V}}_{\mathrm{d}(2,\mathrm{j})}{}^{\prime }=(2\times 5^{\mathrm{j}-1}{)\mathrm{V}}_{\mathrm{dc}}$ ${\mathrm{V}}_{\max }=6{\displaystyle \sum _{\mathrm{j}=2}^{\mathrm{n}}{(5}^{\mathrm{j}-1})}{\mathrm{V}}_{\mathrm{dc}}$	$12{\displaystyle \sum _{\mathrm{j}=1}^{\mathrm{n}}{5}^{\mathrm{j}-1}}+1$	[44 × 5n − 1] × Vdc
Proposed Algorithm 9	${\mathrm{V}}_{\mathrm{d}(1,\mathrm{j})}={\mathrm{V}}_{\mathrm{d}(2,\mathrm{j})}=7^{\mathrm{j}-1}{\mathrm{V}}_{\mathrm{dc}}{;\mathrm{V}}_{\mathrm{d}(1,\mathrm{j})}{}^{\prime }={\mathrm{V}}_{\mathrm{d}(2,\mathrm{j})}{}^{\prime }=(2\times 7^{\mathrm{j}-1}{)\mathrm{V}}_{\mathrm{dc}}$ ${\mathrm{V}}_{\max }=6{\displaystyle \sum _{\mathrm{j}=2}^{\mathrm{n}}{(7}^{\mathrm{j}-1})}{\mathrm{V}}_{\mathrm{dc}}$	$12{\displaystyle \sum _{\mathrm{j}=1}^{\mathrm{n}}{7}^{\mathrm{j}-1}}+1$	[44 × 7n − 1] × Vdc
Proposed Algorithm 10	${\mathrm{V}}_{\mathrm{d}(1,\mathrm{j})}={\mathrm{V}}_{\mathrm{d}(2,\mathrm{j})}=25^{\mathrm{j}-1}{\mathrm{V}}_{\mathrm{dc}}{;\mathrm{V}}_{\mathrm{d}(1,\mathrm{j})}{}^{\prime }={\mathrm{V}}_{\mathrm{d}(2,\mathrm{j})}{}^{\prime }=(5\times {25}^{\mathrm{j}-1}{)\mathrm{V}}_{\mathrm{dc}}$ ${\mathrm{V}}_{\max }=12{\displaystyle \sum _{\mathrm{j}=2}^{\mathrm{n}}{(25}^{\mathrm{j}-1})}{\mathrm{V}}_{\mathrm{dc}}$	${25}^{\mathrm{n}}$	[95 × 25n − 1] × Vdc

tabulates the mathematical relations pertaining to determiningvarious parameters using proposed voltage source algorithms. The proposed structure has an inherent feature of producing odd/even voltage levels. Using a few modules of the proposed MLI structure with an H-bridge inverter, more voltage steps are produced with fewer power elements compared with conventional MLIs.

The proposed asymmetrical topology has thefreedom to enjoy operations at different input voltage source values, which increases the number of output voltage levels. There are ten different mathematical relations presented to examine the performance of the proposed structure in asymmetrical modes with fewer switching devices, as shown in Table 1. It is observed that the blocking voltage of the switches used in the proposed structure is decided by the input voltage sources connected to produce the desired voltage levels. The suggested algorithms are comprehended with three modular structures with 39 switches and 12 DC sources in a cascaded connection, and the corresponding source voltage values are tabulated in

Table 2. Determination of values of voltage sources using derived algorithms.

Stages	PA3	PA4	PA5	PA6	PA7	PA8	PA9	PA10
I (S = 13)	Vd(1,1) = Vdc Vd(2,1) = Vdc Vd(1,1)’ = 2Vdc Vd(2,1)’ = 2Vdc	Vd(1,1) = Vdc Vd(2,1) = Vdc Vd(1,1)’ = Vdc Vd(2,1)’ = Vdc	Vd(1,1) = Vdc Vd(2,1) = Vdc Vd(1,1)’ = Vdc Vd(2,1)’ = Vdc	Vd(1,1) = Vdc Vd(2,1) = Vdc Vd(1,1)’ = Vdc Vd(2,1)’ = Vdc	Vd(1,1) = Vdc Vd(2,1) = Vdc Vd(1,1)’ = Vdc Vd(2,1)’ = Vdc	Vd(1,1) = Vdc Vd(2,1) = Vdc Vd(1,1)’ = 2Vdc Vd(2,1)’ = 2Vdc	Vd(1,1) = Vdc Vd(2,1) = Vdc Vd(1,1)’ = 2Vdc Vd(2,1)’ = 2Vdc	Vd(1,1) = Vdc Vd(2,1) = Vdc Vd(1,1)’ = 5Vdc Vd(2,1)’ = 5Vdc
III (S = 39)	Vd(1,1) = Vdc Vd(2,1) = Vdc Vd(1,1)’ = 2Vdc Vd(2,1)’ = 2Vdc Vd(1,2) = 2Vdc Vd(2,2) = 2Vdc Vd(1,2)’ = 4Vdc Vd(2,2)’ = 4Vdc Vd(1,3) = 4Vdc Vd(2,3) = 4Vdc Vd(1,3)’ = 8Vdc Vd(2,3)’ = 8Vdc	Vd(1,1) = Vdc Vd(2,1) = Vdc Vd(1,1)’ = Vdc Vd(2,1)’ = 3Vdc Vd(1,2) = 3Vdc Vd(2,2) = 3Vdc Vd(1,2)’ = 3Vdc Vd(2,2)’ = 3Vdc Vd(1,3) = 9Vdc Vd(2,3) = 9Vdc Vd(1,3)’ = 9Vdc Vd(2,3)’ = 9Vdc	Vd(1,1) = Vdc Vd(2,1) = Vdc Vd(1,1)’ = Vdc Vd(2,1)’ = Vdc Vd(1,2) = 2Vdc Vd(2,2) = 2Vdc Vd(1,2)’ = 4Vdc Vd(2,2)’ = 4Vdc Vd(1,3) = 4Vdc Vd(2,3) = 4Vdc Vd(1,3)’ = 8Vdc Vd(2,3)’ = 8Vdc	Vd(1,1) = Vdc Vd(2,1) = Vdc Vd(1,1)’ = Vdc Vd(2,1)’ = Vdc Vd(1,2) = 3Vdc Vd(2,2) = 3Vdc Vd(1,2)’ = 6Vdc Vd(2,2)’ = 6Vdc Vd(1,3) = 9Vdc Vd(2,3) = 9Vdc Vd(1,3)’ = 18Vdc Vd(2,3)’ = 18Vdc	Vd(1,1) = Vdc Vd(2,1) = Vdc Vd(1,1)’ = Vdc Vd(2,1)’ = Vdc Vd(1,2) = 4Vdc Vd(2,2) = 4Vdc Vd(1,2)’ = 4Vdc Vd(2,2)’ = 4Vdc Vd(1,3) = 16Vdc Vd(2,3) = 16Vdc Vd(1,3)’ = 16Vdc Vd(2,3)’ = 16Vdc	Vd(1,1) = Vdc Vd(2,1) = Vdc Vd(1,1)’ = 2Vdc Vd(2,1)’ = 2Vdc Vd(1,2) = 5Vdc Vd(2,2) = 5Vdc Vd(1,2)’ = 10Vdc Vd(2,2)’ = 10Vdc Vd(1,3) = 25Vdc Vd(2,3) = 25Vdc Vd(1,3)’ = 50Vdc Vd(2,3)’ = 50Vdc	Vd(1,1) = Vdc Vd(2,1) = Vdc Vd(1,1)’ = 2Vdc Vd(2,1)’ = 2Vdc Vd(1,2) = 7Vdc Vd(2,2) = 7Vdc Vd(1,2)’ = 14Vdc Vd(2,2)’ = 14Vdc Vd(1,3) = 49Vdc Vd(2,3) = 49Vdc Vd(1,3)’ = 98Vdc Vd(2,3)’ = 98Vdc	Vd(1,1) = Vdc Vd(2,1) = Vdc Vd(1,1)’ = 5Vdc Vd(2,1)’ = 5Vdc Vd(1,2) = 25Vdc Vd(2,2) = 25Vdc Vd(1,2)’ = 125Vdc Vd(2,2)’ = 125Vdc Vd(1,3) = 625Vdc Vd(2,3) = 625Vdc Vd(1,3)’ = 3125Vdc Vd(2,3)’ = 3125Vdc

. The first two methods are omitted for the discussion since the variety of voltage ratios is only two, and the other methods are very interesting in getting a variety of voltage ratios that are more than two. The least source voltage value decides the minimum step voltage in the load terminals, and the proposed relations result in a variety of voltage levels using the proposed structure. It is seen in Table 2 that methods 3 and 5 have voltage values in the order of even numbers, which produce voltage levels of 85 and 81, respectively. Similarly, methods 4 and 6 have voltage ratios in multiples of three and produce voltage levels of 105 and 153, respectively. Methods 7 and 8 produce voltage levels of 169 and 373, respectively, with fewer blocking voltage switches. Method 9 produces a maximum voltage level of 685 for the same number of switches and DC sources as used in methods 1 to 8. It is concluded that the proposed structure is capable of generating voltage levels higher in number with asymmetrical sources, which are acquired from PV or fuel cell sources.

The reliability of the proposed topology is justified by proper comparison with traditional and recent topologies in terms of isolated DC sources, switching devices, gate drivers, and total blocking voltage of the switches. Since the proposed topology involves isolated DC sources, a detailed comparison study is taken by considering similar asymmetrical cascaded MLI topologies with isolated DC sources [14,19,23,26,28]. These topologies are facilitated with a variety of isolated DC sources with asymmetrical voltage values. These methods help in identifying the maximum possible voltage levels that can be generated for given values of stacks (n).

Table 3. Mathematical relations to attain various design parameters.

Ref.	IGBTs	Gate Drivers	DC Sources	TBV	Levels
14	10n	9n	4n	33n	16n + 1
19	5n + 6	5n + 6	3n + 1	7(2(n + 2)) − 22	(2(n + 3)) − 5
23	6n + 8	6n + 7	4n + 1	144n + 12.5	12n + 13
26	8n	8n	3n	2(7n − 1)	7n
28	10n	9n	4n	17(15n − 1)/7	15n
Proposed MLI (PA10)	13n	13n	4n	95(25(n − 1))	25n

tabulates the relations to attain various parameters for proposed and recent asymmetrical topologies. The proposed topology with derived algorithm (PA10) shows a larger variation in level generation in a minimum number of stacks compared with recent topologies.

Figure 3 shows the variation of IGBTs for proposed and recent reduced count topologies. In the proposed topology, four isolated DC sources and 13 unidirectional IGBTs are used to formulate a stack (n). The maximum switches in the current conduction path will be half the total switch count. However, the conduction loss can be reduced by facilitating fundamental switching in the H-6 inverter and PWM operations in the switches connected in the DC sources. Figure 3 shows that the proposed MLI needs fewer IGBTs compared with recent topologies. In Figure 4, the proposed topology uses only unidirectional IGBTs, and the gate driver required is proportional to the switches used in the proposed topology. The recent reduced count topologies involve both unidirectional and bidirectional IGBTs and the number of gate drivers required by the recent topologies is high compared with the proposed MLI. The recent topologies are symmetrical and are decided by the variety of voltage sources used. The proposed MLI requires fewerDC sources as the level increases, as authenticated from Figure 5. In some conventional topologies, the DC sources are not completely utilized to produce the voltage levels [28]. The total blocking voltage (TBV) of the proposed topology and recent topologies are measured in terms of the TBV of the proposed topology. It is known from Figure 6 that the topologies [14,19,23,26,28] require switches with a blocking voltage of (5% to 32%) of the proposed topology. As the level increases, the proposed MLI standing voltage of the IGBTs isless compared with the proposed MLI.

The feasibility of the proposed MLI for utility applications suggeststhat it has good efficiency compared with traditional topologies. The proposed topology has better efficiency if it has lesser power loss. The power loss can be reduced by employing hybrid PWM in the proposed topology, the level generation part (IGBTs in DC sources side) switched at PWM and load current reversing in load (IGBTs in the H-6 inverter) performed by fundamental switching at line frequency. The power loss across the IGBT is to be computed during switching and conduction of load current over one switching cycle. The proposed MLI requires fewer IGBTs inthe current conduction path in line with traditional MLIs and four switches perform PWM switching in level generation and four switches with fundamental switching in an H-6 inverter compared with CHBMLI with eight switches for the same number of voltage levels. The switching loss incurred during the shift from off-state voltage/current to conduct current during on-state over one fundamental switching cycle. Similarly, the conduction loss is invariable with switching frequency (fs), and the switching loss increases proportional to (fs).

The switching loss during (Turn-ON and Turn-OFF) of the ‘ith’ switch is given in (1)

$$P_S={\displaystyle \sum _{j=1}^{13z}\frac{1}{6}\left[(t_{on}+t_{off})\times I\times V_{o,j}\times f\right]}$$

(1)

where, Ps is switching losses

Ton—on time in sec

Toff—off time in sec

I—Current in Amps

Vo,j—Output voltage in volts

f—Frequency in Hertz

The proposed MLI is portrayed to operate with the 25-level inverter with less switching loss in par with CHBMLI. For the 25-level inverter with equal step values of Vdc, the average switching loss is given in (2)

$$P_S={\displaystyle \sum _{i=1}^{13z}\frac{1}{6}\left[(t_{on}+t_{off})\times I_o\times V_o\times f\right]}$$

(2)

where, I_O—Output Current in amps

It is assumed that the ton and toff values are the same in each switch while carrying the load current (Io), therefore the switching loss is approximated in (3) as

$$P_S=\gamma \times V_o\times f$$

(3)

where γ is constant,

$$\gamma =\frac{1}{6}\left((t_{on}+t_{off})\times I_o\right)$$

(4)

The CHBMLI requires 16 switching devices which are switched at high switching frequency, while the proposed topology requires only three switches that operate at high switching frequency. The ratio of switching loss incurred by proposed topology over CHBMLI is given by

$$P_{S(CHBMLI)}=16\times \gamma \times V_{dc}\times f_s$$

(5)

$$P_{S(\mathrm{Pr}oposed)}=4\times \gamma \times V_{dc}\times f_s$$

(6)

$$\frac{P_{S(\mathrm{Pr}oposed)}}{P_{S(CHBMLI)}}=\frac{1}{4}$$

(7)

3. Simulation and Experimental Investigation

The operating characteristics of the developed MLI is understood in the Matlab/Simulink environment and the inverter is designed to produce the operating terminal voltage of 300 V (peak) for an RL load of 100 Ω and 100 mH, respectively. The input voltage sources are selected in a variety of values to configure the suggested MLI in an asymmetrical operation. The suggested MLI has the possibility of functioning at either fundamental switching or PWM. The PWM method is predominantly used in industrial applications and the proposed topology is studied with PWM operation. The well-known multicarrier PWM (MCPWM) method is considered for deliberating base PWM pulses, and the required pulses for each level are acquired suitably using logical functions to buffer the required switches to pump PWM modulated stepped voltage waveform in the load terminals. The simulation study is performed to operate the proposed MLI for producing the 25-level inverter with the input voltage parameters of Vd(1,1) = Vd(1,1) = 25 V; Vd(1,1)’ = Vd(1,1)’ = 125 V RL load of 100 Ω and 100 mH, respectively. The simulated response of the proposed asymmetrical MLI is presented in Figure 7, Figure 8 and Figure 9 with voltage stress of the PWM switched IGBTs, output voltage, and inductive load current. From Figure 7, it is understood that the voltage stress on IGBTs is decided by the voltage sources connected to the load in the conduction path. The IGBT (Sse) holds the magnitudes of voltage sources (Vd1′ and Vd2′), and the remaining IGBTs withstand the magnitudes of the voltage sources connected to it. Therefore, the proposed MLI has lower standing voltages at higher voltage levels. It is perceived in Figure 8 that the output voltage has a maximum value of 300 V (peak) and the switching frequency of 2 kHz. The output voltage follows the shape of a sinusoidal and has a THD of 4.57%, which is a relative value to the IEEE 519 standard. The simulated harmonic spectrum is shown in Figure 10. The load current is sinusoidal due to the low-pass filter behavior of the inductive load and has a value of 2 A and THD of 5.42%, respectively.

The proposed MLI is fabricated with similar parameters exercised in the simulation for laboratory prototype testing, depicted in Figure 11. The proposed MLI makes use of several isolated power modules using IGBTs (IRG4BC20SD) and associated driver circuits (IR2110). The MLI is making up for any voltage levels using few IGBT modules and gate driver units. The base PWM and required gating signals stream up the required voltage levels through Digilent Xilinx Spartan 3E-500 FG320 FPGA controller. The onboard clock frequency used for pulse generation is 50 MHz. The design flow postulates the base PWM generation for each level of the 25-level inverter. The data for reference sine is taken at different intervals and formed as Look-uptables (LUTs). A counter is set for acquiring the sine data from a stored memory address. Similarly, for carrier wave generation, a step value is calculated based on the carrier frequency and is added to the base value to generate a triangular carrier. The sine reference and triangular carrier waves are compared to produce the base PWM pulses. The Base PWM pulses are suitably employed to generate required pulses through logical operations for the 25-level inverter. The developed PWM patterns are obtained by writing VHDL coding and a bit file is generated using Xilinx-ISE software. The bit file is downloaded to the FPGA controller through Digilent Adept software. The corresponding output voltage, inductive load current, and harmonic spectrums are displayed in Figure 12, Figure 13 and Figure 14, respectively. The experimental results are displayed in accordance with simulation results.

4. Conclusions

The proposed asymmetrical MLI helps to attain a large number of voltage steps with a reduced number of DC sources, switches, and gate drivers compared with traditional MLIs. A stack of four voltage sources and 13 IGBTs is used to facilitate a new asymmetrical MLI. A few modules are arranged in a cascaded connection to achieve large variations in voltage steps with minimum IGBTs. The ten varieties of voltage source value computation methods are portrayed further to prove the viability of the proposed MLI for practical applications. The proposed MLI enjoys the freedom of replacing isolated DC sources by PV sources or capacitors to open a scope for investigations. The proposed MLI is simulated with traditional PWM and has a choice of switching tohybrid PWM also. The simulated results accumulate the inference from asymmetrical operation to extend the scope for deriving various voltage determination methods. The laboratory test performance is well followed with the simulation studies and concludes that the proposed MLI is well suited for medium voltage and renewable energy applications.