FPGA Implementation and Design of a Hybrid Chaos-AES Color Image Encryption Algorithm
Abstract
:1. Introduction
2. Algorithm Design
2.1. Chaotic System
2.2. Purpose of New Chaotic Encryption Algorithm
- i.
- AddRoundKey: Each byte in the matrix uses XOR to manipulate the round key; a subkey is derived from the main key using Rijndael’s key schedule.
- ii.
- SubBytes: Change each byte using an 8-bit substitution box. This step provides the nonlinear substitution of the replacement function.
- iii.
- ShiftRows: In the ShiftRows step, bytes in each row of the state are shifted cyclically to the left. The shifted number of places each byte is depended on the number of rows.
- iv.
- MixColumns: In order to properly mix linear operations in a matrix, this step uses a linear transformation to mix four bytes per line. The last encryption loop omits the MixColumns step and replaces it with another AddRoundKey.
- Step. i.
- In the Spin-Sort, we can express the plaintext as a 4 × 4 matrix in Figure 5a. Where x0, x1, x2, …, x15 are 8-bit values.
- Step. ii.
- Mark the matrix as an outer and inner blocks as Figure 5b.
- Step. iii.
- Take a vertex of the outer(inner) block as the root.
- Step. iv.
- Sorted by the root, clockwise (counterclockwise) from the outer (inner) block to the inner (outer) block.
2.3. Key Generator Design
- Step. i.
- Select the proper values to be the initial conditions for the 4D chaotic system.
- Step. ii.
- Execute pre-iteration nr rounds, where nr is 2000 rounds.
- Step. iii.
- Calculate summation of image pixel, according to Equation (6).
- Step. iv.
- Use Sumpixel as parameter to iterate np rounds as in Equation (7).
- Step. v.
- The initial 128-bit key generate after iterate np rounds in 4D chaotic system as Equation (8).
- Step. vi.
- Iterate once every 16-byte block encryption.
2.4. Flow Chart of Encryption
3. FPGA Implementation
3.1. Chaos System Discretization
3.2. Encryption System Hardware Implementation
3.2.1. SDRAM Access
3.2.2. Encryption System
- Step. i.
- Posedge clock, count a register dcnt to confirm if the number of rounds is 4.
- Step. ii.
- Posedge clock, module aes_key_expand_128 generate new round key.
- Step. iii.
- Posedge clock, check whether is initial round. If is initial round, registers sam,n are divided 128-bits input data XOR first round key, Else, assign by sam,n_next which is sam,n_mc XOR round key,
- Step. iv.
- Wire connected module aes_Csbox, spin_sort and mix_col. The module aes_Csbox produced sam,n_cs, the module spin_sort produced sam,n_ss, the module mix_col produced sam,n_mc.
- Step. v.
- Posedge clock, the output data is assigned sam,n_ss XOR round key.
4. Security Analyisis
4.1. Histogram Analysis
4.2. Correlation Analysis
4.3. Differential Attack Analysis
4.4. Information Entropy Analysis
5. Conclusions
Author Contributions
Funding
Conflicts of Interest
References
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IP-CORE | Time Latency (Clock, 50 MHz) |
---|---|
ALTFP_ADD | 8 |
ALTFP_SUB | 8 |
ALTFP_MULT | 6 |
Lena | Airplane | Pepper | Mandrill | |
---|---|---|---|---|
Diagonal | −0.000483 | 0.000348 | 0.000759 | −0.000042 |
Horizontal | −0.001001 | 0.000468 | 0.000466 | 0.000613 |
Vertical | −0.001015 | 0.001086 | −0.000803 | 0.002013 |
Proposed | Ref. [22] | Ref. [23] | Ref. [24] | |
---|---|---|---|---|
Diagonal | −0.000546 | 0.000573 | 0.006000 | 0.000700 |
Horizontal | −0.000383 | 0.000538 | −0.012700 | 0.004900 |
Vertical | −0.001287 | −0.007058 | 0.006700 | 0.003100 |
Proposed | Ref. [22] | Ref. [23] | Ref. [24] | |
---|---|---|---|---|
Diagonal | −0.003829 | −0.001693 | −0.007800 | 0.001700 |
Horizontal | 0.001205 | 0.001186 | −0.007500 | 0.005400 |
Vertical | −0.000961 | 0.000177 | −0.006800 | 0.000100 |
Proposed | Ref. [22] | Ref. [23] | Ref. [24] | |
---|---|---|---|---|
Diagonal | 0.002926 | −0.000927 | 0.002600 | 0.000700 |
Horizontal | −0.003825 | −0.002372 | −0.000700 | 0.005300 |
Vertical | −0.000798 | 0.007818 | 0.004200 | 0.002200 |
Proposed | Ref. [22] | Ref. [23] | Ref. [24] | |
---|---|---|---|---|
Lena | 99.6040% | 99.71% | 99.6150% | 99.6525% |
Airplane | 99.6051% | NaN | NaN | NaN |
Pepper | 99.6227% | 99.74% | 99.6156% | 99.6254% |
Mandrill | 99.6071% | 99.72% | 99.6031% | 99.6378% |
Proposed | Ref. [22] | Ref. [23] | Ref. [24] | |
---|---|---|---|---|
Lena | 33.4614% | 33.45% | 33.4893% | 33.4331% |
Airplane | 33.4503% | NaN | NaN | NaN |
Pepper | 33.5029% | 33.53% | 33.4336% | 33.4566% |
Mandrill | 33.4969% | 33.50% | 33.4392% | 33.4673% |
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Yang, C.-H.; Chien, Y.-S. FPGA Implementation and Design of a Hybrid Chaos-AES Color Image Encryption Algorithm. Symmetry 2020, 12, 189. https://doi.org/10.3390/sym12020189
Yang C-H, Chien Y-S. FPGA Implementation and Design of a Hybrid Chaos-AES Color Image Encryption Algorithm. Symmetry. 2020; 12(2):189. https://doi.org/10.3390/sym12020189
Chicago/Turabian StyleYang, Cheng-Hsiung, and Yu-Sheng Chien. 2020. "FPGA Implementation and Design of a Hybrid Chaos-AES Color Image Encryption Algorithm" Symmetry 12, no. 2: 189. https://doi.org/10.3390/sym12020189