# A 12-bit 30 MS/s Successive Approximation-Register Analog-to-Digital Converter with Foreground Digital Calibration Algorithm

^{*}

## Abstract

**:**

## 1. Introduction

_{cm}architecture, thereby achieving improved energy efficiency [4]. The bottom plates of the capacitor array are used to sample the input signals so as to achieve better linearity, from V

_{cm}switching to V

_{ref}or GND in each step, which can reduce switching energy usage. Moreover, the most significant bit (MSB) can be decided after sampling without any consumption of switching energy; thus, the total capacitor is halved, compared with conventional architecture, and the core area is also reduced. The topology of the whole SARADC is shown in Figure 1.

## 2. The Digital Foreground Calibration Algorithm

#### 2.1. Comparator Offset

_{ref}/2

^{N*bit}. For example, for a 12-bit SARADC with a 1.2 V power supply, 1 LSB is equal to 293 µV. However, the offset error voltage of the comparator is usually larger than 5 mV. Therefore, this design proposes a self-calibration technique for digital-to-analog (DAC) mismatch, based on the comparator that requires the offset voltage to be minimized through self-calibration in advance. In this design, the comparator has a two-stage preamplifier to enhance precision. Post-simulation of the comparator layout shows that the difference of input minimum voltage is about 65 µV and can be compared, preceding the demand of the comparator self-calibration precision by about 1/4 LSB. Thus, meeting the requirement completely.

_{p}<0> ~ C

_{p}<7>; C

_{n}<0> ~ C

_{n}<7>). The calibration capacitor arrays are binary-weighted, like the capacitor array of the main DAC in SARADC, while the unit capacitance size is as small as possible.

_{cm}. PMOS capacitance is added until the comparator output turns; the offset error is less than 1/4 LSB, and there is minimal impact on the performance of the whole ADC.

#### 2.2. Capacitor Mismatch

_{cm}by connecting with the common voltage, before the node becomes disconnected and remains disconnected until the conversion process is over. During the conversion process, the top plate voltage moves, but eventually returns to a constant value that is close to V

_{cm}at the end of the process. Finally, the total charge of the parasitic capacitances is the same from the beginning to the end of the process. From the perspective of charge, parasitic capacitances do not cause voltage error. Accordingly, the parasitic capacitances on the top plate of the capacitor array do not affect the overall accuracy of the conversion process.

#### 2.3. The Calibration Theory

_{cm}; when the sampling phase is finished, the top plate of the capacitor array is disconnected with common voltage, V

_{cm}. Both the bottom plates of the positive and negative capacitor arrays are constantly connected with common voltage, V

_{cm}, as shown in Figure 4a. The calibration MOS capacitor is then added to the positive or negative side, according to the feedback of the output of the comparator, and the code is restored until the comparator’s output changes; this step constitutes the calibration comparator offset for the MSB decision. The voltage for both positive and negative comparator inputs is as given in Equation (1):

_{u}represents the ideal unit capacitor, and C

_{0}= C

_{Rd}= C

_{u}; C

_{i}= 2

^{i}·C

_{u}; δ

_{0}is the mismatch of the unit capacitor; and δ

_{i}is the mismatch of the capacitor array, C

_{i}. Based on Equation (1), mismatch is the main reason leading to voltage error.

_{cm}; both the bottom plate of C

_{10}in the positive capacitor array and the bottom plates (except C

_{10}) in the negative array change from common voltage, V

_{cm}, to reference voltage, V

_{ref}, at the same time; moreover, the rest of the capacitor array’s bottom plates connected with common voltage, V

_{cm}, remain unchanged. The process is as shown in Figure 4b, and as given in Equations (2) and (3):

_{cm}; both the bottom plate of C

_{9}in the positive capacitor array and the bottom plates (except C

_{9}) in the negative array change from common voltage, V

_{cm}, to reference voltage, V

_{ref}, at the same time; moreover, the rest of the capacitor array’s bottom plates connected with common voltage, V

_{cm}, remain unchanged. The process is as shown in Figure 4c, and as given in Equations (4) and (5):

_{6}, is calibrated. The maximum voltage error probably caused by capacitor array, C

_{6}, is less than half of LSB; it can thus completely satisfy the demands of a 12-bit SARADC.

#### 2.4. Linearity Analysis

^{N}

^{−2}is the maximum standard deviation, then

## 3. Circuit Implementation

^{N}

^{−1}binary-weighted unit capacitor arrays that are multiples of the unit capacitor C

_{u}(C

_{u}, 2·C

_{u}, 4·C

_{u}... 2

^{N}

^{−2}·C

_{u}). A redundant unit capacitor C

_{Rd}(C

_{Rd}= C

_{u}) is added to the array to make the number of capacitors a multiple of two, so that the total capacitance becomes 2

^{N}

^{−1}·C

_{u}; the redundant unit capacitor is sampled together with the other capacitor arrays, but does not take part in the process of quantization. The V

_{cm}-based capacitive structure SARADC only uses half as many unit capacitors, compared with conventional architecture; moreover, for a 12-bit SARADC, the V

_{cm}-based tri-level switch structure saves about 87.51% in terms of switching energy consumption.

#### Two-Stage Preamplifier Full-Scale Differential Dynamic Comparator

_{offset}, of the comparator can be calculated as:

_{TH}

_{1}

_{,}

_{2}represents the threshold voltage, $\Delta {\left(W/L\right)}_{1,2}$ represents the physical dimension mismatch between M

_{1}and M

_{2}, and $\Delta {R}_{load}$ represents the load resistance mismatch.

_{ox}variation may cause input-referred offset for the latch. The threshold voltage mismatch of the input transistors is the primary cause of comparator offset, which is inversely proportional to the gate area. Thus, the latch must be driven by a preamplifier to reduce the input-referred offset. To overcome the input-referred offset of the latch, the preamplifier circuit must supply enough gain to resolve the minimum difference of the input signal and amplify it to a large enough voltage. Accordingly, the comparator circuit offset is stored and canceled without adding any extra timing, by using this preamplifier. The input noise of the comparator is as shown in Figure 6.

## 4. Simulation Results

_{s}= 2 MS/s.

_{s}= 2MS/s is shown in Figure 11. The comparator, capacitor digital-to-analog converter (CDAC), and SAR control logic power consumption, form the majority of the ADC power consumption. Preamplifier power consumption accounts for most of the power of the comparator. Switches always change from V

_{cm}, to V

_{ref}or GND, and a great deal of energy will be used in this process. Bootstrap, Clock generator, and the digital calibration block only use a small amount of energy, which shows that the foreground digital calibration algorithm does not significantly increase power consumption.

## 5. Conclusions

_{ref}, of the DAC was set to supply voltage VDD to achieve rail-to-rail sampling.

^{2}. All capacitors were implemented using MOM structures. The digital calibration logic was based on a comparator MOS capacitor array and synthesized using Design Compiler, with an estimated area of 0.084 mm

^{2}. The power supply is 1.2 V. At a 30 MS/s conversion rate, this SARADC achieved a state-of-the-art ENOB of 11.08 at a 14.56 MHz full-scale sine wave input frequency, resulting in a 39.45 fJ/conversion-step.

## Author Contributions

## Funding

## Acknowledgments

## Conflicts of Interest

## References

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**Figure 4.**Calibration process of capacitor array mismatch. (

**a**) Calibrate Comparator offset; (

**b**) Calibrate mismatch of capacitor array C

_{10}; (

**c**) Calibrate mismatch of capacitor array C

_{9}.

**Figure 10.**Signal-to-noise-and-distortion ratio (SNDR) and spurious free dynamic range (SFDR) with input frequency.

Ref. [6] | Ref. [7] | Ref. [1] | Ref. [3] | This work | |
---|---|---|---|---|---|

Process (μm) | 0.13 | 0.13 | 0.055 | 0.04 | 0.13 |

Supply (V) | 1.2 | 1.2 | 3.3/1.2 | 1.1 | 1.2 |

Resolution (bits) | 10 | 8 | 16 | 6 | 12 |

Sampling rate (MS/s) | 40 | 360 | 16 | 700 | 30 |

SFDR (dB) | 57.7 | 63.1 | 97.5 | / | 84.45 |

SNDR (dB) | 50.6 | 45.6 | 78 | 35.3 | 68.56 |

ENOB (bit) | 8.11 | 7.28 | 12.66 | 5.57 | 11.08 |

Power (mW) | 0.55 | 3.55 | 16.3 | 0.81 | 2.39 |

FoM (fJ/conv.-step) | 50 | 56 | 165 | 24.4 | 39.45 |

Technology (μm) | 0.13 |

Resolution (bits) | 12 |

Sampling rate (MS/s) | 30 |

ENOB (bits) | 11.08 |

SNDR (dB, fin = 14.56 MHz) | 68.56 |

SFDR (dB, fin = 14.56 MHz) | 84.45 |

DNL (LSB) | −0.64/+0.65 |

INL (LSB) | −1.1/+1.3 |

Power (mW) | 2.39 |

FoM (fJ/conv.-step) | 39.45 |

Active (mm^{2}) | 0.273 |

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**MDPI and ACS Style**

Li, S.; Guo, Y.; Chen, J.; Liang, B.
A 12-bit 30 MS/s Successive Approximation-Register Analog-to-Digital Converter with Foreground Digital Calibration Algorithm. *Symmetry* **2020**, *12*, 165.
https://doi.org/10.3390/sym12010165

**AMA Style**

Li S, Guo Y, Chen J, Liang B.
A 12-bit 30 MS/s Successive Approximation-Register Analog-to-Digital Converter with Foreground Digital Calibration Algorithm. *Symmetry*. 2020; 12(1):165.
https://doi.org/10.3390/sym12010165

**Chicago/Turabian Style**

Li, Shouping, Yang Guo, Jianjun Chen, and Bin Liang.
2020. "A 12-bit 30 MS/s Successive Approximation-Register Analog-to-Digital Converter with Foreground Digital Calibration Algorithm" *Symmetry* 12, no. 1: 165.
https://doi.org/10.3390/sym12010165