Novel Hybrid-Size Digit-Serial Systolic Multiplier over GF(2m)
Abstract
:1. Introduction
2. Mathematical Formulation of the Proposed Multiplication Algorithm
Algorithm 1. Proposed multiplication algorithm for hybrid field-size-based implementation |
Inputs: and (also and ) are the pair of elements (polynomial basis representation) in for |
field-size of and , respectively |
Output: for and is the field polynomial |
1. Initialization step |
1.1 Define , , …, for according to (8) 1.2 Define , , …, for according to (9) 1.3 Define |
2. Multiplication step |
2.1 According to the field-size selection signal, determine the value of j 2.2 For 2.3 2.4 End for |
3. Final step |
3.1 Get |
3. Proposed Hybrid-Size Digit-Serial Systolic Multiplier
3.1. Novel Input Data Broadcasting Scheme
3.2. Proper Arrangement on the Input Data Delivery
3.3. Hybrid Accumulation
3.4. Final Structure
4. Complexity and Comparison
5. Conclusions
Author Contributions
Funding
Conflicts of Interest
Abbreviations
IP | Intellectual property |
ECC | Elliptic curve cryptography |
PE | Processing elements |
IC | Integrated chip |
NCSU | North Carolina State University |
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Design | AND | XOR | Register | Latency | Critical-Path |
---|---|---|---|---|---|
Digit-serial systolic structures (trinomial of size ) | |||||
[7] | |||||
[8] | |||||
Digit-serial systolic structures (pentanomial of size ) | |||||
[4] | |||||
DS-I [9] | |||||
Hybrid-size digit-serial systolic structures (pentanomial of size and trinomial of size ) | |||||
Proposed | |||||
Design | Area (m) | Delay (ns) | Power (W/GHz) | ADP (m ns) | PDP (W/GHz× ns) |
---|---|---|---|---|---|
Digit-serial trinomial-based () | |||||
[7] | 46,958 | 4.48 | 56,068 | 251,185 | |
[8] | 46,174 | 4.48 | 55,726 | 249,652 | |
Digit-serial pentanomial-based () | |||||
[4] | 22,675 | 45.63 | 35,412 | 1,034,660 | 1,615,850 |
[9] | 26,998 | 4.16 | 33,139 | 112,312 | 137,858 |
Hybrid-size ( and ) | |||||
Traditional | 73,172 | 4.48 | 88,865 | 327,811 | 398,115 |
Proposed | 29,961 | 6.4 | 40,672 | 191,750 | 260,301 |
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Hu, Z.; Xie, J. Novel Hybrid-Size Digit-Serial Systolic Multiplier over GF(2m). Symmetry 2018, 10, 540. https://doi.org/10.3390/sym10110540
Hu Z, Xie J. Novel Hybrid-Size Digit-Serial Systolic Multiplier over GF(2m). Symmetry. 2018; 10(11):540. https://doi.org/10.3390/sym10110540
Chicago/Turabian StyleHu, Zhenji, and Jiafeng Xie. 2018. "Novel Hybrid-Size Digit-Serial Systolic Multiplier over GF(2m)" Symmetry 10, no. 11: 540. https://doi.org/10.3390/sym10110540
APA StyleHu, Z., & Xie, J. (2018). Novel Hybrid-Size Digit-Serial Systolic Multiplier over GF(2m). Symmetry, 10(11), 540. https://doi.org/10.3390/sym10110540