Hysteresis Reduction for Organic Thin Film Transistors with Multiple Stacked Functional Zirconia Polymeric Films

Abstract

We show that transfer hysteresis for a pentacene thin film transistor (TFT) with a low-temperature solution-processed zirconia (ZrO_x) gate insulator can be remarkably reduced by modifying the ZrO_x surface with a thin layer of crosslinked poly(4-vinylphenol) (c-PVP). Pentacene TFTs with bare ZrO_x and c-PVP stacked ZrO_x gate insulators were fabricated, and their hysteresis behaviors compared. The different gate insulators exhibited no significant surface morphology or capacitance differences. The threshold voltage shift magnitude decreased by approximately 71% for the TFT with the c-PVP stacked ZrO_x gate insulator compared with the bare ZrO_x gate insulator, with 0.75 ± 0.05 and 0.22 ± 0.03 V threshold voltage shifts for the bare ZrO_x and c-PVP stacked ZrO_x gate insulators, respectively. The hysteresis reduction was attributed to effectively covering hysteresis-inducing charge trapping sites on ZrO_x surfaces.

1. Introduction

Combined metal oxide and organic layers have been extensively studied for research and practical applications [1,2,3], providing key functional materials for next-generation electronics. Applications for metal oxides and organic compounds encompass a wide range of electronic components including thin film transistors (TFTs), light emitting diodes, photovoltaic cells, and biochemical sensors [4,5,6]. One of their most critical features is solution processability, which offers facile low-cost large area production for electronics compared with conventional vacuum processes. Solution processes commonly incorporate sol-gel methods [7]. Diverse metal oxides and organic compounds for electronic applications have been previously demonstrated to provide high optical transparency in the visible region and mechanical flexibility [8,9]. Thus, combined metal oxide and organic layers may provide new concepts for electronics incorporating flexibility, transparency, and other significant technological advantages.

One example application for combined metal oxide and organic layers is gate insulators and active layers for organic TFTs [10]. TFTs are critical components of electronic circuits in displays and sensors, and zirconia (ZrO_x), hafnia, yttria, and titania films are attractive candidates for low-voltage organic TFT gate insulators [11,12]. ZrO_x offers a good option for organic TFTs due to its solution processability, large band gap, high permittivity, low leakage current, and thermal and mechanical stability [12,13]. One facile sol-gel method for obtaining high-quality defect-minimized ZrO_x films is high-temperature annealing, since sol-gel methods are generally based on a series of chemical reactions requiring specific activation energies. However, high-temperature annealing is not suitable for flexible electronics, which are built on plastic substrates with relatively low thermal resistance, since most plastic substrates are severely damaged by process temperatures above 200 °C [14]. Thus, eliminating defects and related effects in low-temperature solution-processed ZrO_x films is essential for flexible electronics applications.

Previous studies have shown that TFTs with solution-processed ZrO_x gate insulators often exhibit low electrical stability, e.g., large transfer hysteresis [15,16,17]. Interfacial properties between gate insulators and active layers are crucial for TFT electrical characteristics; hence, gate insulator surface properties can greatly affect hysteresis. Therefore, low-temperature solution-processed ZrO_x gate insulators need improved TFT hysteresis characteristics. For example, covering ZrO_x gate insulators with thin polymeric layers may provide improved interfaces by preventing hysteresis-inducing factors present on the surfaces from forming direct contacts with TFT channels. Although bilayer gate insulators are commonly employed for TFT hysteresis reduction, surface modification of low-temperature solution-processed ZrO_x films with polymeric layers has not yet been explored in the context of TFT hysteresis.

This study fabricated pentacene TFTs with bare zirconia (ZrO_x) and crosslinked poly(4-vinylphenol) (c-PVP) stacked ZrO_x gate insulators and analyzed their hysteresis behaviors. Cross-sectional and surface morphologies for bare and c-PVP stacked ZrO_x thin films were examined by scanning electron microscopy (SEM) and atomic force microscopy (AFM), and water contact angles were measured. Morphological properties for pentacene thin films thermally deposited on bare and c-PVP stacked ZrO_x thin films were examined by AFM, and their crystalline properties by X-ray diffraction (XRD). Metal–insulator–metal (MIM) capacitor capacitances were also measured.

2. Materials and Methods

We produced ZrO_x solution by dissolving 40 mg/mL zirconium (IV) acetylacetonate (487.66 g/mol, Sigma Aldrich) in methanol (32.04 g/mol, Sigma Aldrich) [18], and added monoethanolamine (61.08 g/mol, Sigma Aldrich) as a stabilizer, i.e., molar ratio 1:1 between zirconium (IV) acetylacetonate and monoethanolamine. The ZrO_x solution was stirred at 50 °C for 12 hours. To produce c-PVP solution, we dissolved PVP (25,000 g/mol, Sigma Aldrich) in propylene glycol methyl ether acetate (132.16 g/mol, Sigma Aldrich) at 0.1 wt%, and then added methylated poly(melamine-co-formaldehyde) (432.84 g/mol, Sigma Aldrich) at a 1:1.125 weight ratio as a crosslinking agent [19]. The PVP solution was stirred at room temperature for 12 hours.

Top-contact bottom-gate pentacene TFTs with bare and c-PVP stacked ZrO_x thin gate insulators were fabricated, and 50 nm aluminum films were thermally evaporated on cleaned glass substrates through a shadow mask at a 0.1 nm/s deposition rate, and bare and c-PVP stacked ZrO_x thin films were formed on the substrates. ZrO_x solution was spin coated onto the substrate at 3000 rpm with subsequent soft and hard bake two-step thermal treatment. Soft bake samples were annealed on a hotplate at 65 °C for 10 minutes, whereas hard bake samples were annealed on a hotplate at 200 °C for 1 hour in a moisture-rich environment, created by vaporizing water from a reservoir at 7 mg/min. To form c-PVP stacked ZrO_x gate insulators, PVP solution was spin-coated on pre-formed ZrO_x film at 3000 rpm with subsequent thermal treatment on a hot plate at 200 °C to crosslink PVP chains. Then, 50 nm pentacene (278.35 g/mol, Sigma Aldrich) films were thermally evaporated on the gate insulators at a 0.1 nm/s deposition rate to form active layers. Finally, source/drain electrodes were fabricated by thermally evaporating 50 nm gold films onto the pentacene films through a shadow mask at a 0.1 nm/s deposition rate, creating channels with length L = 50 μm and width W = 400 μm. In addition, two MIM construction capacitors were fabricated using bare and c-PVP stacked ZrO_x thin films. Aluminum films (50 nm) were deposited by thermal evaporation to form bottom and top electrodes for the MIM capacitors. All deposition processes were conducted at 1.6 × 10⁻⁶ Torr base pressure.

Electrical characterization for the pentacene TFTs was performed using the EL420C semiconductor parameter analyzer (ELECS, Seoul, South Korea), and MIM capacitor capacitances were measured using the HP4192A impedance analyzer (Hewlett Packard, San Jose, CA, USA). SEM, AFM, and XRD measurements for thin films were performed using S-4800 (Hitachi High-Technologies, Tokyo, Japan), NX20 (Park Systems, Suwon, South Korea), and D/Max-2500 (Rigaku, Tokyo, Japan), respectively.

3. Results and Discussion

Figure 1a,b show typical cross-sectional SEM surface images for bare and c-PVP stacked ZrO_x thin films. The thin films exhibited thicknesses of approximately 51.4 and 54 nm, respectively, indicating that the stacked c-PVP layer was approximately 2.6 nm. Figure 1c,d show water contact angles on bare and c-PVP stacked ZrO_x thin films. The measured contact angles ≈ 66.1° and 62.4°, respectively. We calculated surface energies (γ_Ps) for the bare and c-PVP stacked ZrO_x thin films as

$${\gamma }_P=\frac{{\gamma }_W}{4}{\left(1+\text{cos}{\theta }_0\right)}^2$$

(1)

where γ_W = 73.0 mJ/m² is the surface free energy for water, and θ₀ is the contact angle at equilibrium [20]. Thus, γ_Ps ≈ 36.0 and 39.1 mJ/m² for bare and c-PVP stacked ZrO_x thin films, respectively, i.e., the c-PVP stacked ZrO_x thin film exhibited a higher γ_P than the bare ZrO_x thin film. The different γ_P between the bare ZrO_x and c-PVP stacked ZrO_x thin films is related to their different chemical states. Figure 1c,d insets show typical surface AFM images (3 × 3 μm) for bare and c-PVP stacked ZrO_x thin films, respectively. The thin films exhibit comparable surface morphologies and root-mean-square surface roughness; approximately 0.162 and 0.171 nm, respectively. Structural defects, such as pinholes, were not observed in the AFM analyses, which indicates that the gate stack quality was sufficiently high for both bare ZrO_x and c-PVP stacked ZrO_x thin films.

Figure 2a,b show typical surface AFM images (1.5 × 1.5 μm) for pentacene thin films thermally deposited on bare and c-PVP stacked ZrO_x thin films, respectively. The thin films exhibit an approximate surface roughness equal to 6.55 and 7.72 nm, respectively. The pentacene on the c-PVP stacked ZrO_x thin film exhibited more dendritic and larger grains than that on the bare ZrO_x thin film. The relatively high γ_P for c-PVP stacked ZrO_x thin films can affect pentacene layer-by-layer growth, yielding relatively larger grains [21].

Figure 3a shows typical XRD patterns for bare and c-PVP stacked ZrO_x thin films with thermally deposited pentacene thin films. There were no discernible sharp XRD peaks in either case, indicating that they were formed in amorphous states. All pentacene thin films exhibited (001), (002), (003), and (004) peaks, which agrees well with the typical (00l) pattern for pentacene thin film phase crystallites [22]. Figure 3b shows the (001) diffraction peaks for the pentacene thin films. Examination of (001) diffraction peaks provides critical information on the molecular state of pentacene thin films [23]. The pentacene thin films exhibited similar full width at half maximum (FWHM) values for the (001) peaks, approximately 0.191 ± 0.001°. Since the XRD peak FWHM for organic films is associated with their crystallinity [24], the similar FWHM values suggest comparable crystallinity between the pentacene thin films. The pentacene thin films exhibited similar (001) interlayer spacing values, approximately 1.499 ± 0.001 nm, which were calculated by Bragg’s Law (λ = 2d_hkl sin(θ)) [25]. In addition, as shown in Figure 3b, the pentacene thin film deposited on the c-PVP stacked ZrO_x thin film exhibited a relatively lower bulk-to-thin film phase XRD intensity ratio than the one deposited on bare ZrO_x film. This indicates that the pentacene thin film on the c-PVP stacked ZrO_x thin film has a lower density of bulk phase crystallites than that on the bare ZrO_x thin film [23]. The variation in the pentacene phase state is related to the different chemical states and γ_P between bare ZrO_x and c-PVP stacked ZrO_x thin films.

The MIM capacitor capacitances were measured by applying a small alternating current (AC) signal (10 mV at 100 kHz). MIM capacitors with a c-PVP stacked ZrO_x thin film exhibited a comparable but slightly lower capacitance than those with a bare ZrO_x thin film (approximately 74.7 and 79.4 nF/cm², respectively). The calculated capacitance for MIM capacitors with a c-PVP stacked ZrO_x film was 74.8 nF/cm², from the usual series capacitance relationship, which agrees well with the measured value (74.7 nF/cm²). In addition, the dielectric constant of the bare ZrO_x thin film was 4.61, and the average dielectric constant of the c-PVP stacked ZrO_x thin film was 4.55. It worth noting that the dielectric constant of ZrO_x thin film (=4.61) is higher than that for c-PVP (=3.9) and conventional SiO₂ (=3.9), since different dipole–channel interactions may lead to different TFT characteristics.

Figure 4a,b show transfer characteristics for pentacene TFTs with bare and c-PVP stacked ZrO_x gate insulators, respectively, measured by varying the gate voltage (V_G) from 0.5 to −4 V and back in 0.5 V increments and 0.1 V decrements at constant V_D = −4 V. Since drain current is

$$I_D=\frac{W{\mu }_{eff}{C}_{ox}}{2L}{(V_G-V_T)}^2$$

(2)

where C_ox is the gate insulator capacitance and V_T is the threshold voltage [26], we extracted field-effect mobilities (μ_FEs) from the slope of |I_D|^1/2 with respect to V_G. The pentacene TFTs exhibited comparable μ_FE values (1.02 ± 0.06 cm²/Vs). The Figure 4a,b insets show output characteristics for pentacene TFTs with bare and c-PVP stacked ZrO_x gate insulators, respectively, measured by changing drain voltage (V_D) from 0 V to −4 V in 0.1 V increments at different V_Gs (V_G = 0, −1, −2, −3, and −4 V). All devices exhibited a linear I_D increase for small V_D and I_D saturation for high V_D. All devices were operated in p-channel accumulation mode.

There were remarkable hysteresis differences between pentacene TFTs with the two gate insulator types. Transfer hysteresis is an important parameter for TFT electrical stability [27]. We extracted V_T by linear extrapolation from |I_D|^1/2 versus V_G plots to I_D = 0; V_T,forward = −1.60, V_T,backward = −0.85 V for the bare ZrO_x case; and V_T,forward = −0.98, V_T,backward = −0.76 V for the c-PVP stacked ZrO_x case. The TFT with the c-PVP stacked ZrO_x gate insulator exhibited a smaller V_T magnitude than that with the bare ZrO_x gate insulator. In particular, V_T,hysteresis = V_T,backward − V_T,forward = 0.75 ± 0.05 and 0.22 ± 0.03 V for the bare and c-PVP stacked ZrO_x cases, respectively. V_T,hysteresis decreased by approximately 71% for the TFT with the c-PVP stacked ZrO_x gate insulator compared with the bare ZrO_x gate insulator. Note that a TFT channel was formed at the gate insulator/semiconductor interface. The relatively smaller V_T,hysteresis for the c-PVP stacked ZrO_x case indicates that c-PVP stacked ZrO_x gate insulator and pentacene film interfaces had a lower number of charge-trapping sites than bare ZrO_x gate insulator and pentacene films did, since V_T,hysteresis magnitude is directly dependent on the quantity of charge trapped during hysteresis. Sol-gel solution-processed metal oxide thin films often suffer from various defects, including Schottky and Frenkel defects, residual hydroxyl groups and ligands, and various byproducts [28]. Due to the high possibility for the presence of such diverse defects, we consider that solution-processed bare ZrO_x gate insulators created more defect-induced charge-trapping sites at pentacene film interfaces, whereas c-PVP layer defects were limited to mainly residual hydroxyl groups, inducing less interfacial charge-trapping sites [19]. Moreover, high-k ZrO_x dipoles, strongly interacting with TFT channel charge carriers, possibly contributed to the TFT hysteresis. Covering the ZrO_x gate insulator with a c-PVP layer provided an improved interface by preventing surface charge-trapping sites from forming a direct contact with the TFT channel. Consequently, the c-PVP stacked ZrO_x gate insulator led to significantly reduced hysteresis in pentacene TFTs.

Further study is needed to identify the fundamental hysteresis mechanisms through optical and thermal analyses, and theoretical calculations for individual defect species. Moreover, devising methods of modifying the ZrO_x dielectric constant and bandgap will be important for further advancement of ZrO_x. The current study regarding low-temperature solution-processed ZrO_x films in organic TFTs provides a significant step towards developing flexible and transparent electronics.

4. Conclusions

We showed that transfer hysteresis for a pentacene TFT with a low-temperature solution-processed ZrO_x gate insulator was remarkably reduced by modifying the ZrO_x surface with a thin c-PVP layer. This study compared hysteresis behaviors for pentacene TFTs with bare and c-PVP stacked ZrO_x gate insulators. We found V_T,hysteresis = 0.75 ± 0.05 and 0.22 ± 0.03 V for bare and c-PVP stacked ZrO_x thin films, respectively. MIM capacitors exhibited a comparable capacitance for bare and c-PVP stacked ZrO_x thin films (79.4 and 74.7 nF/cm², respectively). Pentacene TFTs exhibited a comparable μ_FE (1.02 ± 0.06 cm²/V/s) for both thin film types. These results provide useful background to improve electrical stability for next-generation electronics incorporating combined metal oxide and organic layers.