A Comparison Study on Multilayered Barrier Oxide Structure in Charge Trap Flash for Synaptic Operation

Abstract

A synaptic device that contains weight information between two neurons is one of the essential components in a neuromorphic system, which needs highly linear and symmetric characteristics of weight update. In this study, a charge trap flash (CTF) memory device with a multilayered high-κ barrier oxide structure on the MoS₂ channel is proposed. The fabricated device was oxide-engineered on the barrier oxide layers to achieve improved synaptic functions. A comparison study between two fabricated devices with different barrier oxide materials (Al₂O₃ and SiO₂) suggests that a high-κ barrier oxide structure improves the synaptic operations by demonstrating the increased on/off ratio and symmetry of synaptic weight updates due to a better coupling ratio. Lastly, the fabricated device has demonstrated reliable potentiation and depression behaviors and spike-timing-dependent plasticity (STDP) for use in a spiking neural network (SNN) neuromorphic system.

1. Introduction

The artificial intelligence (AI) processor has been one of the most important technologies in the 4th industrial revolution [1,2]. AI hardware consisting of conventional, complementary metal-oxide semiconductor (CMOS) circuits based on the von Neumann architecture have been widely implemented, while the system consumes a quite amount of power due to the von Neumann bottleneck [3,4]. To overcome the von Neumann bottleneck, a neuromorphic computing system has been one of the promising candidates to emulate a human brain that consumes approximately 20 Watts of power.

This paper provides a study on an artificial synaptic device, which is one of the essential components of a neural network for building a hardware-based spiking neural network (SNN) system. A biological neural network consists of numerous neurons and synapses. A neuron acts as a spike generator to transfer a spike signal to the next neuron, and a synapse connects two neurons to control the connection strength, which is modified by the biological process called synaptic plasticity in the biological nervous system [5,6]. Since the number of synapses in a neural system is a few orders of magnitude bigger than the number of neurons in general, designing a proper synaptic device is critical in terms of size and power consumption [7,8]. In addition, previous studies have shown that achieving a high accuracy system is determined by synaptic devices with proper symmetricity, nonlinearity(ν), and high conductance on/off ratio in large-scale artificial neural networks (ANN) [9,10].

In the current industry, a charge trap flash (CTF) memory has been fabricated with a silicon nitride dielectric film as a charge trapping layer to trap electrons and SiO₂ as a tunneling barrier oxide layer [11]. For the use in neuromorphic hardware, we fabricated a CTF device and engineered the barrier oxide layer by proposing a multilayered high-κ structure on the MoS₂ channel to mimic some of the key synaptic-like behaviors. Conductance of the device represents a synaptic weight, controlled by program/erase operation. The device demonstrates the improved symmetric curves and conductance on/off ratios in potentiation and depression behaviors. We also present a spike-timing-dependent plasticity (STDP) to demonstrate a popular learning rule used in SNN-based neuromorphic computing systems.

2. Fabrication Methods

A MoS₂-based CTF memory device was fabricated on a SiO₂ (300 nm)/P⁺-Si substrate, as shown in the schematic in Figure 1a. MoS₂ flakes were mechanically exfoliated onto a substrate by using the “scotch tape” method to make a FET channel [12]. For the tape exfoliation method, a piece of cellulose tape was applied on the top surface of the bulk MoS_2, and several layers of flakes from the crystals were peeled off. This leads to the clean surface that had not been previously exposed to the ambient condition [13]. As shown in Figure 1b,c, the AFM image shows the thickness of the exfoliated MoS₂ flake. The flakes were dipped in acetone for 2 h to completely remove the tape residue on the substrate. Then, the sample was rinsed with isopropyl alcohol (IPA) and deionized water (DI water) for 10 min, respectively [14]. The two peaks of MoS₂ ($E_{2g}^1$ and A_1g) in Raman spectroscopy were clearly observed using 532 nm wavelength in the device region in Figure 1d. Drain and source electrodes (Ti 5 nm/Au 70 nm) were patterned using photolithography, followed by an e-beam evaporator deposition process. Since two dimensional layered materials have dangling bond-free surface [15], 0.5 nm of Al were deposited first as a seed layer, creating a native thin Al₂O₃ layer for the atomic layer deposition (ALD) process [16]. For the tunneling oxide layer, 4 nm of SiO₂ were deposited by plasma-enhanced chemical vapor deposition (PECVD) at 250 °C. A multilayer oxide/nitride stack was formed to increase the trap sites rather than a single layer by alternately depositing a 2 nm Si₃N₄ film as a charge trapping layer and a 2 nm Al₂O₃ film as an intermediate barrier oxide layer by PECVD at 250 °C and ALD at 150 °C, respectively. For the top-gate dielectric blocking oxide, 6 nm of Al₂O₃ was deposited using ALD. Finally, the top-gate electrode was deposited with Ti 5 nm/Au 70 nm by e-beam evaporator. The samples were annealed at 300 °C for 2 h by flowing H₂ 5%/N₂ 95% mixed gas. The cross-sectional transmission electron microscopy (TEM) image of the device in Figure 1e identified the MoS₂ channel layer and the multilayered charge trapping structure.

3. Results and Discussion

Electrical properties were measured by a vacuum chamber probe station (MS Tech (Hwaseong, Korea), M5VC) and a semiconductor characterization system (Keithley, 4200A-SCS) at room temperature and ambient condition. For the measurement, two source measure units (SMUs) at drain/top-gate terminals were used to sweep and measure voltages with the source terminal grounded. The output and transfer curves of the CTF memory device are shown in Figure 2. The linear and symmetric drain-source current ($I_{ds}$) of the output curve ($I_{ds}-V_{ds})$ implies an ohmic contact between MoS₂ and Ti/Au as shown in Figure 2a. Figure 2b shows the transfer curve ($I_{ds}-V_{gs}$) measured by sweeping the top-gate at the range of –10 V to 10 V at the various drain-source voltages ($V_{ds}$) of 0.1 V, 1 V, and 2 V. This device exhibits n-type operation due to the unique characteristics of MoS₂ [17] and has the field-effect mobility of 2.1 ${\mathrm{cm}}^2{\mathrm{V}}^{-1}{\mathrm{s}}^{-1}$. The mobility was extracted from the transfer curve in Figure 2b using Equation (1);

$$\mathsf{\mu }=\left(d{I}_{ds}/d{V}_{gs}\right)\times \left(L/W{V}_{ds}{C}_i\right)$$

(1)

where L is length (5 µm), W is channel width (5 µm) for the device, and C_i is the capacitance for gate insulator per unit area.

Voltage pulses ($V_{gs}$) representing a neuronal spike train were consecutively applied to the top-gate to mimic the potentiation and depression behaviors of a biological synapse. The operating mechanism of the CTF device is related to the tunneling hot electrons and the charge trapping states. When a negative voltage pulse is applied to the top-gate electrode, a portion of the trapped electrons in the three nitride layers are released to the channel. As a result, the device is moved to a low threshold voltage state (erase state), and the channel current (conductance) increases. On the contrary, when a positive voltage pulse is applied to the top-gate electrode, the three nitride layers are gradually charged by the electrons tunneled from the channel, resulting in a high threshold voltage state (program state). This state effectively decreases the channel current (conductance). In this study, two different devices were fabricated with different intermediate barrier oxide stacks to compare the synaptic device properties. Schematics of the two different multilayered charge trapping thin film stacks are illustrated in Figure 3a.

Both structures have the same 4 nm of SiO₂ for the tunneling oxide, 6 nm of Al₂O₃ for the blocking oxide, and 2 nm of Si₃N₄ for each charge trapping layer, while they have different intermediate barrier oxide layers (2 nm of Al₂O₃ and 2 nm of SiO₂ for Device 1 and Device 2, respectively) for this comparison. Each intermediate barrier oxide layer and charge trapping nitride layer was deposited alternately three times for both devices. Figure 3b shows the potentiation and depression curves of the synaptic devices with thirty-two synaptic weight states. For the measurement, thirty-two consecutive voltage pulses of −13 V with the pulse width of 10 µs for potentiation and +13 V with the pulse width of 10 µs for depression were applied sequentially to the top-gate to update the weight, and the device channel current (or conductance) was read after each pulse was applied. Device 1 with Al₂O₃ as the intermediate barrier oxide layers shows a higher conductance on/off ratio than that of Device 2 with SiO₂ as the intermediate barrier oxide layers, attributed to the coupling ratio differences between the two devices. A device coupling ratio determines a portion of the applied voltage across the tunneling oxide at the given top-gate voltage. Therefore, the higher coupling ratio allows for the higher tunneling voltage applied between the channel and the charge trapping layer. A coupling ratio equation is given by [18,19];

$${\alpha }_{cg}=C_{Block}/\left(C_{Block}+C_{Tunnel}\right)$$

(2)

where ${\alpha }_{cg}$ is coupling ratio, $C_{Block}$ and $C_{Tunnel}$ are capacitances of the blocking oxide and the tunneling oxide, respectively.

The estimated values of the coupling ratio of Device 1 and Device 2 are 0.34 and 0.28, respectively. From the measurements, Device 1 with a high coupling ratio shows a higher conductance on/off ratio and more linear potentiation and depression curves than Device 2 as shown in Figure 3b,c. A high coupling ratio enhances the tunneling efficiency and the memory window for threshold voltage shift, and hence, the device’s synaptic behavior is improved. Figure 3d,e show the nonlinearity values for fourteen cycles of potentiation and depression operations, defined by Equations (3) and (4) [20].

Potentiation:

$$\mathrm{G}=G_1\left(1-e^{-\nu P}\right)+G_{min}$$

(3)

Depression:

$$\mathrm{G}=G_{max}-G_1(1-e^{-\nu \left(1-P\right)})$$

(4)

where

$$G_1=\left(G_{max}-G_{min}\right)/\left(1-e^{-\nu }\right),$$

G_max and G_min are the maximum and minimum conductance of the device, respectively, ν is a parameter of nonlinearity, and P is the normalized pulse number.

The average nonlinearity values at thirty-two conductance steps of Device 1 and Device 2 in the potentiation operations were estimated as 3.49 and 4.48, respectively; and the average nonlinearity values of the devices in the depression operations were estimated as 8.27 and 12.76, respectively. Figure 4 shows the robustness of the synaptic device through an iterative process of 896 voltage pulses in potentiation and depression operations.

Synaptic weight updates based on the STDP learning rule are demonstrated in Figure 5 to mimic a biological process in a SNN-based neuromorphic system [21]. The STDP behavior modulates the synaptic weight information between the pre- and post-synaptic neurons according to a relative spike timing difference. To show the STDP behavior, a set of differently shaped pulses (V_applied), containing the timing difference information (∆t = t_post − t_pre) between a pre-synaptic pulse (V_pre) and a post-synaptic pulse (V_post), were applied to the top-gate (Figure 5a,b).

The pre- and post-synaptic neuron spike shapes (V_pre and V_post) were adapted from a previous study [22]. When V_pre spikes before V_post (positive ∆t case), the synaptic weight is enhanced, whereas, when V_post spikes before V_pre (negative ∆t case), the synaptic weight is weakened. Figure 5c shows the amount of synaptic weight (conductance) change at each ∆t. The exponential fitting lines at both polarities indicate a well-behaved STDP learning rule; the shorter the ∆t, the greater the amount of weight change.

4. Conclusions

In summary, we fabricated a flash memory device with a multilayered charge trapping structure to mimic synaptic operations. A high on/off ratio and symmetric conductance updates have been demonstrated using high-κ intermediate barrier oxide film stacks. The device with Al₂O₃ as intermediate barrier oxide layers exhibited a higher on/off ratio and better linear conductance change than the device with SiO₂ as intermediate barrier oxide layers. This result is attributed to the enhanced coupling ratio from the high-κ material used in the intermediate barrier oxide layers, which increases the memory threshold voltage shift window of the device. The iterative experiment and STDP data from the fabricated synaptic device suggest that a CTF device with the multilayered high-κ barrier oxide structure can be one of the viable synaptic device candidates for an SNN-based neuromorphic system.