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Computers 2018, 7(3), 46; https://doi.org/10.3390/computers7030046

New Residue Number System Scaler for the Three-Moduli Set {2n+1 − 1, 2n, 2n − 1}

Department of Computer Engineering, School of Engineering, Princess Sumaya University for Technology, P.O. Box 1438, Al-Jubeiha, Amman 11941, Jordan
Received: 13 August 2018 / Revised: 29 August 2018 / Accepted: 30 August 2018 / Published: 3 September 2018
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Abstract

This work proposes the first scaler designed specifically for the three-moduli set M 1 = { 2 n + 1 1 , 2 n , 2 n 1 } . Hence, there is no other functionally similar scaler to compare the proposed scaler with. However, when compared with the latest published scalers for a different moduli set, M 2 = { 2 n + 1 , 2 n , 2 n 1 } , the proposed scaler has a better area and power performance, while it requires a longer time delay. As demonstrated in earlier publications, replacing the ( 2 n + 1 ) channel in the M 2 moduli set by the ( 2 n + 1 1 ) channel, to form the M 1 moduli set, considerably improves the overall time performance of residue-based multiply–accumulate arithmetic units. View Full-Text
Keywords: residue number system; scaling; computer arithmetic; VLSI design residue number system; scaling; computer arithmetic; VLSI design
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This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).
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Hiasat, A. New Residue Number System Scaler for the Three-Moduli Set {2n+1 − 1, 2n, 2n − 1}. Computers 2018, 7, 46.

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