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Micromachines 2018, 9(12), 637; https://doi.org/10.3390/mi9120637

Monolithic Low Noise and Low Zero-g Offset CMOS/MEMS Accelerometer Readout Scheme

Institute of Electronic Engineering, National Chiao Tung University, Hsinchu 300, Taiwan
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Received: 17 November 2018 / Revised: 26 November 2018 / Accepted: 28 November 2018 / Published: 30 November 2018
(This article belongs to the Special Issue MEMS/NEMS Sensors: Fabrication and Application)
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Abstract

A monolithic low noise and low zero-g offset CMOS/MEMS accelerometer and readout scheme in standard 0.18 μm CMOS mixed signal UMC process is presented. The low noise chopper architecture and telescopic topology is developed to achieve low noise. The experiments show noise floor is 421.70 μg/√Hz. The whole system has 470 mV/g sensitivity. The power consumption is about 1.67 mW. The zero-g trimming circuit reduces the offset from 1242.63 mg to 2.30 mg. View Full-Text
Keywords: Accelerometer readout; low noise; low zero-g offset Accelerometer readout; low noise; low zero-g offset
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This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).
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Liu, Y.-S.; Wen, K.-A. Monolithic Low Noise and Low Zero-g Offset CMOS/MEMS Accelerometer Readout Scheme. Micromachines 2018, 9, 637.

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