Electro-Thermal Improvement in a β-Ga₂O₃ Cage-Integrated Slanted-Fin MOSFET

Abstract

Electro-thermal improvement is critical for β-Ga₂O₃ power devices to mitigate self-heating while maintaining high-voltage capability. Here, we propose a β-Ga₂O₃ cage-integrated slanted-fin MOSFET (C-SFMOSFET). By optimizing the cage-to-fin and cage-to-drain distances, the cage sequence simultaneously strengthens channel depletion and enhances heat dissipation in the gate-to-drain region. Compared with the baseline slanted-fin MOSFET (SFMOSFET), the proposed 4-cage C-SFMOSFET achieves a 1.75× higher Baliga’s figure of merit and reduces the peak junction temperature by 8 °C at 0.55 W/mm. These results indicate that the proposed device layout can effectively improve device-level electro-thermal performance and further exploit the inherent advantages of ultra-wide-bandgap β-Ga₂O₃.

1. Introduction

The ultra-wide-bandgap (UWBG) semiconductor β-Ga₂O₃ has attracted considerable research interest for next-generation power devices because of its high theoretical Baliga’s figure of merit (BFOM), its large breakdown electric field, and the availability of large-size substrates [1,2,3,4,5]. These advantages make β-Ga₂O₃ a promising candidate for high-power and high-efficiency switching applications.

These material properties also broaden the device-level design space for electric-field engineering [6,7]. For example, Wang et al. demonstrated a lateral superjunction-equivalent MOSFET [8], which achieved full depletion and punch-through operation as the electric field approached the critical value of β-Ga₂O₃. However, selective p-NiO filling in the drift region degraded the on-state performance. Meng et al. introduced a self-aligned vertical gate structure together with a gate field plate into a lateral MOSFET, reducing the electric field in the gate-to-drain access region and suppressing nonlinear current rise in saturation [9]. However, the stringent process requirements of the self-aligned vertical gate indicate that electrostatic optimization may come with manufacturability penalties. These studies show that electrical-performance enhancement in β-Ga₂O₃ MOSFETs is feasible but often involves practical or structural trade-offs.

More critically, the relatively low thermal conductivity of β-Ga₂O₃ (10.9–27 W/m·K at 300 K) makes self-heating a persistent bottleneck, so that even effective electric-field engineering remains thermally constrained [10]. To address this issue, several thermal-management approaches have been explored. Substrate-level strategies, such as substrate thinning and heterogeneous integration with high-thermal-conductivity materials, can reduce the thermal resistance of β-Ga₂O₃ MOSFETs [11,12,13]. However, the mechanical fragility of β-Ga₂O₃ complicates aggressive thinning and may introduce extra cost and reliability concerns. Layout-oriented studies have also shown that topside geometry strongly influences heat extraction. For example, Kim et al. reported that reducing the gate-to-drain distance in lateral β-Ga₂O₃ transistors lowered the peak temperature through enhanced heat extraction by the drain electrode, but at the expense of breakdown voltage [14]. They further showed that channel orientation and drain-interconnection geometry also play important roles in thermal management [15]. In addition, thermal characterization studies, such as Raman thermography of β-Ga₂O₃ fin-based devices, have highlighted the importance of thermal management and the associated electro–thermal trade-offs [16]. Collectively, these studies indicate that prior efforts mainly focused on electric-field optimization, thermal management, or identifying electro-thermal trade-offs, but did not establish a practical device-layout-level strategy to mitigate this trade-off in a unified manner.

These limitations motivate device-level electro-thermal co-optimization in β-Ga₂O₃ power devices. In our previous work, a β-Ga₂O₃ slanted-fin MOSFET (SFMOSFET) was proposed to reshape the electrostatic potential profile beneath the gate and promote a more favorable drain-side extension of the depletion region, thereby improving electric-field management and BFOM compared with a straight-fin device [17]. However, although slanted-fin geometry enhances depletion modulation under the gate, electric-field crowding and thermal accumulation in the gate-to-drain region remain significant challenges. More importantly, once additional field-modulation elements are introduced, their interaction with the slanted-fin-induced depletion profile becomes a nontrivial co-design issue rather than a simple structural add-on. In other words, the placement of a floating cage sequence in a slanted-fin MOSFET should be coordinated with the slanted-fin-induced depletion boundary, so that the favorable gate-controlled depletion can be preserved while the remaining gate-to-drain region is further regulated. Meanwhile, the cage sequence can provide an additional topside heat-spreading path.

Unlike a simple extension of our previous work, the present study focuses on the co-design between the slanted-fin-induced depletion profile and the floating cage sequence for simultaneous electric-field and thermal improvement. Based on this concept, this study proposes a β-Ga₂O₃ cage-integrated slanted-fin MOSFET (C-SFMOSFET). By jointly optimizing the cage-to-fin distance and cage-to-drain distance, the proposed device is designed to alleviate electric-field crowding and self-heating in the gate-to-drain region in a unified manner. Comprehensive electro-thermal simulations and experimental characterization verify the advantages of the C-SFMOSFET and provide a device-layout-level electro-thermal design strategy for thermally constrained β-Ga₂O₃ power devices. The novelty does not lie in the use of metal stripes alone, but in their coordinated layout with the slanted-fin-induced depletion boundary to achieve device-level electro-thermal co-optimization.

2. Cage Sequence Design by Electro-Thermal Analysis

2.1. Device Structure and Modeling Framework

This section summarizes the co-simulation workflow, device dimensions, and thermal material parameters used in the following electro-thermal analysis. The proposed C-SFMOSFET is derived from the baseline SFMOSFET and evaluated using a two-step framework combining Sentaurus (O-2018.06-SP2) and ANSYS Icepak (2019 R3).

Sentaurus was first used to construct the device models and simulate device operation under specified bias conditions. From these simulations, the electrostatic potential, electric-field distribution, depletion profile, and internal temperature distribution were obtained to identify the active heat-generation region. ANSYS Icepak was then employed to evaluate topside heat dissipation to the surrounding air for different device layouts. In Icepak, an equivalent heat-source distribution was assigned to the active β-Ga₂O₃ region, according to the heat-generation region identified from the Sentaurus simulation, and the same total dissipated power was applied to all layouts to ensure a fair comparison. Steady-state thermal fluid analysis was performed with coupled flow and temperature fields. Natural convection was taken into account by enabling gravity, and all six faces of the surrounding air domain were defined as opening boundaries. The resulting air-velocity distributions above the device were then compared to assess the relative topside heat-dissipation capability of different layouts.

The SFMOSFET employed the following geometrical parameters (Figure 1a): gate-to-drain length L_GD = 20 μm, gate length L_G = 2 μm, gate-to-source length L_GS = 3 μm, and drain-to-source length L_DS = 25 μm. The slanted fin structure had the following parameters: drain-side width W_D = 2.4 μm, source-side width W_S = 0.4 μm, fin angle α = 63°, fin length L_fin = 2 μm, and fin height H_fin = 800 nm. The gate width is W_G = 2 μm [18] and the gate dielectric is 30-nm-thick Al₂O₃.

The thermal parameters used in the model are summarized in Figure 1c. The thermal conductivities were taken from the literature: β-Ga₂O₃ = 27 W/m·K [19], Al₂O₃ = 3.5 W/m·K [20], Ti = 180 W/m·K [21], Ni = 90 W/m·K [21], and Au = 318 W/m·K [21]. The remaining interface-related parameters were obtained via time-domain thermoreflectance (TDTR) [22]. For the Ni/Al₂O₃/β-Ga₂O₃ (45 nm/30 nm/500 μm) sample, the overall thermal boundary conductance (TBC) of the MOS stack was measured to be 30.13 MW/m²·K. Au was selected as the cage material for electro-thermal evaluation, although other materials may offer similar electro-thermal behavior [23]. For the Au/Al₂O₃/β-Ga₂O₃ (300 nm/30 nm/500 μm) sample, the TBC at the Au/Al₂O₃ interface was 30.96 MW/m²·K.

2.2. Electric-Field Optimization of the Cage Sequence

Because the gate-to-drain spacing of the SFMOSFET exceeds its maximum depletion width, an electrically floating metal cage sequence was introduced to further regulate the electrostatic potential in the gate-to-drain region. The cage sequence interacts strongly with the slanted-fin-induced depletion extension. Hence, its boundary position should be coordinated with the slanted-fin-induced depletion region; otherwise, the favorable depletion regulation established by the slanted-fin may be compromised. The optimization, therefore, proceeded in two steps: boundary-position optimization first, followed by cage-geometry optimization.

A 2-cage sequence was first used to determine the proper boundary position. In this design, each cage width was 2 μm and the inter-cage spacing was 9 μm within L_GD = 20 μm. The 2-cage sequence was shifted to different locations as a whole unit along the gate-to-drain direction of the SFMOSFET, while keeping the cage width and inter-cage spacing fixed. Here, d_D denotes the distance from the cage edge to the drain and d_F denotes the distance from the cage edge to the fin (Figure 2a). After boundary optimization, a 4-cage C-SFMOSFET with the same overall device dimensions was constructed for cage-number evaluation, as shown in Figure 1b.

The modulated mechanism involves electrostatic potential redistribution among adjacent floating cages. In the current work, the off-state condition refers to the bias state in which the device is turned off while a high drain voltage is applied (e.g., V_GS = −15 V and V_DS = 1000 V, unless otherwise specified). The electrostatic potential difference between neighboring cages is described by Formula (1) [24], where ϕ_i is the electrostatic potential of the cage i, Q_i is the induced charge of cage i, and C_i is the capacitance between adjacent cage i and cage i + 1. The cage closest to the drain electrode is defined as cage 1. Accordingly, ϕ₀ denotes the electrostatic potential of the drain electrode, and W_depletion denotes the depletion-region width. As indicated by Formula (2), extending depletion reduces the lateral gate-edge off-state electric-field peak (E_peak). Distributing the electrostatic potential across multiple cages, therefore, smooths the off-state electric-field profile in the slanted-fin and cage region and improves breakdown voltage (V_BR).

$${\varphi }_i-{\varphi }_{i+1}={\displaystyle \frac{Q_{\mathrm{i}}}{C_{\mathrm{i}}}}$$

(1)

$$E_{\mathrm{peak}}={\displaystyle \frac{V_{\mathrm{Drain}}-{\displaystyle \sum _{\mathrm{i}=0}^{\mathrm{n}-1}({\varphi }_{\mathrm{i}}}-{\varphi }_{\mathrm{i}+1})}{W_{\mathrm{depletion}}}}$$

(2)

The boundary optimization process follows a clear design rule: too small a d_F should be avoided, because the attractive effect of the cage on channel electrons perturbs the favorable depletion extension induced by the slanted-fin structure and thereby weakens the original gate-controlled depletion, resulting in a higher E_peak (Figure 3b,e,h). In the 2-cage C-SFMOSFET, the minimum E_peak of 5.7 MV/cm at the off-state bias V_GS = −15 V and V_DS = 1000 V is obtained at d_D = 3 μm and d_F = 3.5 μm (Figure 2b). These optimized boundary parameters were then used for the subsequent cage-number optimization. Based on this optimized boundary, the 4-cage C-SFMOSFET further reduces off-state E_peak by 7%, from 5.96 MV/cm in the SFMOSFET to 5.54 MV/cm under the same bias condition (Figure 2c).

The optimum cage geometry parameters should be selected to achieve the best overall electric-field balance in the gate-to-drain region. To this end, 2-cage (wider), 4-cage (proposed), and 8-cage (narrower) sequences were compared, using the same proper cage-boundary positions (d_D = 3 μm and d_F = 3.5 μm) and the same total cage area. As shown in Figure 4a, the individual cage widths were 4, 2, and 1 μm for the 2-cage, 4-cage, and 8-cage sequences, respectively. At the off-state bias of V_GS = −15 V and V_DS = 1000 V, the simulated gate-edge electric-field peaks (E_gate or E_peak) were 5.08, 5.54, and 5.84 MV/cm, respectively (Figure 4b). The 2-cage sequence exhibited the lowest E_gate at this bias because its wider cages provided stronger capacitive coupling to the channel and, thus, stronger electrostatic potential modulation, even with a smaller cage number (Figure 4d). However, this stronger modulation also produced a larger electrostatic potential drop across the cage-controlled region, which shifted the electric-field concentration toward the drain edge.

This trade-off became more evident at a higher drain bias under off-state blocking conditions. At V_GS = −15 V and V_DS = 2000 V, E_gate increased to 5.57, 6.00, and 6.34 MV/cm for the 2-cage, 4-cage, and 8-cage sequences, respectively, while the corresponding drain-side electric-field peaks (E_drain) were 5.01, 4.16, and 3.83 MV/cm (Figure 4c). The higher E_drain in the 2-cage sequence indicates that excessively wide cages, despite their strong capacitive coupling to the channel, tend to transfer the high-electric-field region toward the drain edge and, thus, increase the risk of premature breakdown [3]. In contrast, excessively narrow cages in the 8-cage sequence weaken the local capacitive coupling to the channel. As a result, although the cage number is larger, the local electrostatic potential modulation remains weak, the electrostatic potential drop near the gate side becomes steeper, and E_gate correspondingly increases (Figure 4e). Therefore, cage geometry should be optimized by balancing the stronger drain-edge electric field induced by overly wide cages against the higher gate-edge electric field caused by overly narrow cages. On this basis, the 4-cage sequence provides the best overall electric-field balance and was therefore adopted in this work.

2.3. Electric-Field Modulation After Device Scaling

The design principle remained valid after device scaling, but an effective cage sequence still required proper co-design with the slanted-fin-induced depletion extension, together with re-optimization of the cage width to maintain strong electrostatic potential modulation. To verify this, the gate-to-drain spacing was reduced from 20 to 10 μm, and three scaled layouts were compared with the reference SFMOSFET, as shown in Figure 5a. The first scaled 4-cage layout was obtained by the nearly proportional scaling of the original proposed 4-cage design, with the cage width reduced from 2 μm to 1 μm and the boundary distances reduced from d_D = 3 μm and d_F = 3.5 μm to d_D = 1.5 μm and d_F = 1.5 μm. The second scaled 4-cage layout retained the 1 μm cage width but used d_D = 1 μm and d_F = 3 μm to preserve a wider d_F for the favorable depletion extension induced by the slanted-fin structure. Based on this cage-boundary-preserved layout, the third scaled 2-cage layout further increased the cage width to 2 μm, while keeping d_D = 1 μm and d_F = 3 μm in order to strengthen capacitive coupling to the channel.

At the off-state bias of V_GS = −15 V and V_DS = 1000 V, the E_gate of the reference SFMOSFET and the three scaled layouts are 6.06, 6.07, 5.98, and 5.79 MV/cm, as shown in Figure 5b, respectively. Nearly proportional scaling provided almost no improvement, because the reduced d_F places the cage sequence too close to the slanted-fin gate and weakens the favorable depletion extension. In contrast, preserving sufficient cage-boundary spacing restored the intended depletion-assisted modulation, while further increasing the cage width enhances capacitive coupling and improves electrostatic potential redistribution, as shown in Figure 5c. These results indicate that, after scaling, effective cage optimization depends on both proper cage-boundary matching and an adequate cage width within the reduced gate-to-drain design.

2.4. Enhanced Heat Dissipation Considering Self-Heating

In addition to the electric-field benefits discussed above, the cage sequence also influences the thermal behavior of the device. The superior thermal performance of the proposed 4-cage C-SFMOSFET compared with the baseline SFMOSFET can be understood as the combined effect of enhanced upward heat spreading within the device and improved topside heat dissipation to the ambient air.

In lateral β-Ga₂O₃ devices, the primary heat source is located in the channel region near the gate (Figure 6a–d). Owing to the TBC at the Au/Al₂O₃ interface of 30.96 MW/m²·K, part of the heat generated in the channel can be transferred upward to the Au cage layer, which provides an additional heat-spreading path [25]. This upward heat-extraction effect becomes more evident with increasing cage number (Figure 6e). Under identical power dissipation (P = 0.12 W/mm), the 4-cage C-SFMOSFET reduces the peak junction temperature (T_peak) by 2.5 °C compared with the SFMOSFET.

In addition to improved internal heat-spreading, the 4-cage sequence also contributes to better topside heat dissipation by increasing the exposed surface area. Under natural-convection conditions, Formula (3) indicates that the convective heat transfer rate Q_conv is related to the convective heat transfer coefficient h and the surface area exposed to the fluid A [26].

$$Q_{\mathrm{conv}}\propto hA$$

(3)

Since the convective heat transfer coefficients at both Al₂O₃/air (for SFMOSFET) and Au/air interfaces (for 4-cage C-SFMOSFET) are primarily governed by the fluid (air) properties, a typical natural convection heat transfer coefficient of approximately 5 W/m²·K was adopted [27]. Consequently, the larger exposed surface area of the 4-cage C-SFMOSFET was expected to enhance topside convective heat dissipation under comparable natural-convection conditions. The disparity in natural convection heat dissipation performance between the SFMOSFET and 4-cage C-SFMOSFET was validated using the ANSYS Icepak simulation. The topside thermal pathway in the SFMOSFET was β-Ga₂O₃/Al₂O₃/air, whereas that in the 4-cage C-SFMOSFET was β-Ga₂O₃/Al₂O₃/cage/air. Benefiting from the 4-cage sequence with 300 nm-thick Au sidewalls, the 4-cage C-SFMOSFET provided a 12% larger topside heat dissipation area (Figure 7a,b). This led to enhanced heat transfer from the device to the surrounding air and alleviated local thermal accumulation in the near-surface ambient region, as reflected by the reduced temperature gradient near the surface and the larger low-air-velocity region above the device (Figure 7c,d) [28]. Therefore, the 4-cage C-SFMOSFET provides improved topside heat dissipation. This heat dissipation advantage offered by the 4-cage C-SFMOSFET becomes increasingly pronounced at higher power dissipation levels [11].

3. Experimental Verification and Discussion

3.1. Fabrication and Measurement

Both the 4-cage C-SFMOSFET and the SFMOSFET were fabricated for experimental validation (Figure 8a–c). A β-Ga₂O₃ epitaxial film with a channel layer (600 nm thick and with a 2.5 × 10¹⁷ cm⁻³ doping concentration) and an unintentionally doped layer (200 nm thick) was grown on an (010) Fe-doped semi-insulating substrate. Mesa isolation and a slanted-fin channel were etched to a depth of 800 nm via inductively coupled plasma (ICP) etching in a BCl₃/Cl₂ ambience. The slanted fin was defined by e-beam lithography, and surface damage was removed with piranha solution [29]. The gate oxide (30-nm-thick Al₂O₃), gate electrodes (45-nm/400-nm-thick Ni/Au), and source-drain electrodes (10 nm/200 nm-thick Ti/Au) were identical for both devices. The 4-cage sequence was formed by depositing 300-nm-thick, 2-μm-long Au layers along the device width on the SFMOSFET surface (Figure 8c).

Systematic electrical and thermal measurements were performed to investigate the electro-thermal performance of the 4-cage C-SFMOSFET and the SFMOSFET. Electrical characteristics, including output, transfer, and breakdown characteristics, were measured using a Keysight B1500A analyzer. In addition, I–V characteristics were measured under both DC and pulsed conditions [30]. The DC measurements included self-heating effects, while the pulsed measurements were performed with a duty cycle of 0.035% to suppress self-heating. This comparison was used to examine the current variation induced by self-heating in two devices qualitatively. The thermal performance was further characterized using a QFI InfraScope under identical power dissipation for quantitative analysis, with the ambient temperature set to 70 °C to obtain clear thermal images [31].

3.2. Experimental Results and Discussion

The 4-cage C-SFMOSFET prototype exhibited superior electro-thermal performance compared with the control SFMOSFET (Figure 9a–f and

Table 1. Measured performance comparison between SFMOSFET and 4-cage C-SFMOSFET.

Device	IDS-DC at VGS = 10 V VDS = 20 V	IDS-Pulse at VGS = 10 V VDS = 20 V	Ron at VGS = 10 V	VTH at VDS = 10 V IDS = 1 mA/mm	VBR at VGS = −15 V	BFOM	Tpeak at P = 0.55 W/mm
Normalized by	WG	WG	WG	/	/	W × LDS	W
SFMOSFET (Control)	75.8 mA/mm	184.6 mA/mm	215.3 Ω·mm	−10.5 V	1586 V	2.34 MW/cm2	85 °C
4-cage C-SFMOSFET (Prototype)	81.1 mA/mm	186.1 mA/mm	206 Ω·mm	−9.8 V	2055 V	4.10 MW/cm2	77 °C
Relative variation	+7%	+0.8%	−4.3%	+0.7 V	+29%	×1.75	−8 °C

). The breakdown voltage (V_BR) increased by 29% from 1586 V to 2055 V, and BFOM, defined as V_BR²/R_on,sp, improved by a factor of 1.75, where R_on,sp is the specific on-resistance value normalized to the active region area W × L_DS. The threshold voltage (V_TH), extracted at I_DS = 1 mA/mm for consistent comparison, shifted positively by 0.7 V. At V_GS = 10 V and V_DS = 20 V, the DC output current (considering the self-heating effect) increased by 7%, from 75.8 mA/mm to 81.1 mA/mm and the on-state resistance decreased by 4.3%, while the pulsed current showed no obvious change. The T_peak of the 4-cage C-SFMOSFET (77 °C) was 8 °C lower than that of SFMOSFET (85 °C) at P = 0.55 W/mm. The increased V_BR and the positive shift in V_TH are consistent with the electrostatic potential modulation and enhanced channel depletion introduced by the optimized cage sequence. The improved DC output current and reduced on-state resistance are associated with improved carrier transport resulting from alleviated self-heating.

This work experimentally validates the electro-thermal co-optimization of the cage sequence and slanted-fin-induced depletion. To better position the present work with respect to the existing literature, representative prior β-Ga₂O₃ MOSFET studies on electric-field control and thermal management are summarized in

Table 2. Comparison with representative prior β-Ga₂O₃ MOSFET studies on electric-field control and thermal management.

Reference	Device/Strategy	Main Focus	Representative Result	Main Limitation Relative to This Work
Wang et al., TED 2022 [8]	Superjunction-equivalent between the gate-to-drain region	Electric-field management	VBR = 1362 V; 4.86× BFOM	Electrical optimization only; no thermal improvement
Kim et al., ITherm 2021 [14]	Drain-metal heat extraction by gate-to-drain spacing variation	Electro-thermal trade-off	~35% higher ΔTpeak when LGD decreased from 11 μm to 1 μm at 0.8 W/mm	Trade-off identified, but no mitigation strategy
Kim et al., TED 2022 [15]	Thermally aware lateral layout by channel direction and drain-interconnection width	Layout-level thermal management	~10% lower ΔTpeak by orientation optimization; ~8% higher ΔTpeak with narrower interconnects at 1 W/mm	Thermal optimization only; no simultaneous VBR/BFOM improvement
Kim et al., TED 2023 [11]	Double-sided diamond cooling	External thermal management	~75% lower steady-state ΔTpeak at 4 W/mm	External cooling only; no device-layout optimization
Zhao et al., APL 2026 [16]	Raman thermography of multi-fin β-Ga2O3 FinFETs	Thermal crosstalk	Near-gate hotspot: 70.77 °C in multi-fin vs. 28.8 °C in single-fin devices at 4.7 mW per fin	Trade-off identified, but no mitigation strategy
Xu et al., IEDM 2019 [12]	Ga2O3-on-SiC MOSFETs by ion-cutting	Substrate-level thermal management	Up to 500 K; ~14% Ron degradation; ~600 V sustained	Substrate integration only; no device-layout optimization
This work	Cage-integrated slanted-fin MOSFET	Layout-level electro-thermal co-optimization	VBR = 2055 V; 1.75× BFOM; ~53% lower ΔTpeak relative to ambient (−8 °C in Tpeak) at 0.55 W/mm	Experimentally validated electro–thermal co-improvement at the device-layout level

. As shown, these prior studies mainly focused on either electric-field engineering or thermal management, revealing important electrical–thermal trade-offs or improving only one aspect at a time, but not providing an experimentally validated device-layout-level strategy for simultaneous electro-thermal improvement. The present results support the proposed co-design strategy, in which the floating cage sequence is coordinated with the slanted-fin-induced depletion profile to further regulate the gate-to-drain region while also enhancing topside heat spreading.

4. Conclusions

In summary, an electro-thermally improved β-Ga₂O₃ C-SFMOSFET is presented in this study. The cage-integrated slanted-fin structure improves channel depletion and raises the breakdown voltage. In addition, the cage sequence promotes thermal transport and topside heat dissipation, which helps improve its high-temperature power handling. Despite the low thermal conductivity of β-Ga₂O₃, the proposed device-level electro-thermal improvement layout offers a practical balance between thermal constraints and electrical performance, providing useful design guidance for thermally sensitive β-Ga₂O₃ devices. Future work will extend this framework to the design of large-sized β-Ga₂O₃ power devices.