Research on Robust and Efficient Optimization Design Methods for Analog Integrated Circuits

Round 1

Reviewer 1 Report

Comments and Suggestions for Authors

This paper offers a review of several design methodologies aimed at automatizing the development of analog integrated circuits, exploiting design from libraries and parameter optimization strategies.

 

In general, the review gathers a large variety of software-aided techniques for analog circuit designs, offering also a critical comparison in the last part of the paper.

 

To improve the quality of the manuscript, the following points are highlighted:

1) The quality of Figures shown in the paper is not always sufficient as some texts and labels are not readable. Please, do your best to improve the quality of the figures in the text (as they also show algorithm steps used to perform analog design and optimization).

2) Make more reference to the figures in the text. In general, cited algorithms/methodologies are mentioned with few lines and a short reference to a graph. To improve the comprehension of the work, more details should be shown in the text with strong references to the figures.

3) Related to this, the paper only shows a huge list of design techniques proposed in literature for analog integrated design. In my opinion, some practical examples might be shown to help the comprehension of these techniques. For example, how is an operational amplifier (or any other circuit) designed in practice using these techniques? This would be helpful to understand main points of your analysis, offering also the opportunity to show a critical elaboration of the addressed topic.

4) Please,  show more details when referring to the tables. The content of each column should be clearly introduced in the text and also more discussion about their content is required.

5) It is suggested adding the following papers in the introduction, which give practical examples where  the adoption of otimized strategies for analog design might be possible:

1. Zhong, X. Yang, R. P. Martins, Y. Zhu and C. -H. Chan, "A 0.016mm2 Active Area 4GHz Fully Ring-Oscillator-Based Cascaded Fractional-N PLL With Burst-Mode Sampling," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no. 10, pp. 3792-3796, Oct. 2023, doi: 10.1109/TCSII.2023.3288120.
2. Tegazzini, G. Di Meo, D. De Caro and A. G. M. Strollo, "High-Precision MUX-Based Digital Delay Interpolators Based on a Novel Transistor Sizing Algorithm," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 72, no. 7, pp. 938-942, July 2025, doi: 10.1109/TCSII.2025.3571482.

Author Response

Comments 1: The quality of Figures shown in the paper is not always sufficient as some texts and labels are not readable. Please, do your best to improve the quality of the figures in the text (as they also show algorithm steps used to perform analog design and optimization).

Response 1: Thanks for the reviewer’s suggestive comments. The quality of Figures shown in the paper has been adjusted, which is shown in the appendix.

Comments 2: Make more reference to the figures in the text. In general, cited algorithms/methodologies are mentioned with few lines and a short reference to a graph. To improve the comprehension of the work, more details should be shown in the text with strong references to the figures.

Response 2: Thanks for the reviewer’s suggestive comments. The corresponding descriptions for Figure 2 (a-c) in Section 2.1.1 are shown as follows,

1. With the development of large language model (LLM), the AnalogCoder topology optimi-zation architecture based on LLM agent was proposed by Yao Lai et al. [35]. Figure 2 (a) systematically presents the core design framework of AnalogCoder, which deconstructs the full-design process of both "basic circuit design" and "composite circuit design". This method converts circuit design tasks into design prompts to input into the well-trained LLM model, and the automated topology design and error correction can be achieved. 20 circuits among 24 benchmark tasks without the need for complex model training pro-cesses are successfully designed with low deployment costs, which indicates the ad-vantage of the proposed method. However, the adaptability to ultra-large-scale circuits is limited.
2. A DRL based circuit topology synthesis framework (CTSF) was proposed by Zhao et al. [36], which takes functional sub-circuits as basic units. This framework consists of six core components: 1) Design specifications (gray squares); 2) Pre defined BB library (PBBL); 3) Comprehensive rule set; 4) Policy Gradient Neural Network (PGNN); 5) RL loop (orange square); 6) Topology generation and evaluation module. The sub-circuit combination logic is optimized through a signal segmentation mechanism, and existing design knowledge is reused to improve synthesis efficiency. The example of new circuit topology synthesis is shown in Figure 2 (b).
3. Lu et al. [37] proposed a novel topology synthesis method by decomposing the circuits into several present modules. Figure 2 (c) clearly presents that the transistor sizing is guided by behavioral-level topology, and the layout rules are directly derived by topology constraints, which significantly improves design efficiency. The operational amplifier is decomposed into the input stage, amplification stage, and compensation stage, and the automated optimization design from design specifications to layout can be realized through rule-driven module combination and parameter matching. This method can complete the design without human intervention, which greatly shortens the design cycle. However, the limitations of preset modules make it difficult to generate innovative topologies that break the traditional structures, and the compatibility matching between modules may become a performance bottleneck.

The corresponding descriptions for Figure 2 (d-e) in Section 2.1.2 are shown as follows,

1. An operational amplifier topology optimization method based on variational graph autoencoder (VGAE) was proposed by Lu et al. [40]. The overall flowchart is shown in Figure 2 (d). From the figure, the topology structure is converted into a directed acyclic graph (DAG) and embeds it into a continuous space. Then, the optimal solution in the continuous space is efficiently searched through Bayesian optimization (BO), and the circuit topology is decoded through a graph decoder. The convergency speed is significantly faster than the traditional genetic algorithm, but the topology embedding and restoration process may lead to the loss of some structural information.
2. Lyu et al. [42] reviewed two core topology optimization methods for high-dimensional design space: dimension reduction and region planning, as shown in Figure 2 (e). Where, the dimension reduction method utilizes inherent dimensional relationships to guide the optimization process in low dimensional subspaces. Region planning limits the optimization scope to feasible areas. Based on the above analyzation, the ACOB open-source benchmark library is established to provide a systematic algorithm evaluation platform for parameter optimization of known topologies.

The corresponding descriptions for Figure 3 (a-d) in Section 2.1.3 are shown as follows,

1. The graph grammar framework was further developed by Zhao et al. [45]. The automated topology synthesis framework is shown in Figure 3 (a). From the figure, the method encodes topology generation as a tree structure. The feasible solutions are quickly screened by symbolic analysis and gm/ID method, and the topology uniqueness is ensured through two-layer isomorphism checking. Three-stage operational amplifiers are successfully synthesized by the framework, and its generation efficiency and reliability are better than those of the existing tool FEATS. However, the tree structure encoding method still limits the complexity of the topology to a certain extent, and its adaptability to large-scale circuits with multi-module interactions is insufficient.
2. Gao et al. [48] proposed the AnalogGenie generation engine, and the overall flowchart is shown in Figure 3 (b). From the figure, AnalogGenie represents each topology as a sequence and generates various analog circuit topologies from scratch by predicting the pin connections of devices. In this engine, a large-scale dataset containing 3350 topologies is built, and scalable topology description is realized using pin-level graph representation and Euler tour sequence. This engine can generate 11 types of analog circuits with a maximum of 64 devices, and the proportion of novel topologies is nearly 100% with better performance metrics than existing methods.
3. Shen et al. [49] proposed the ATOM framework. The overall framework is shown in Figure 3 (c) consisting of three core modules: behavior-level topology design space, continuous topological representation learning, and freeze-thaw BO. The design space decomposes operational amplifier into interpretable functional modules, while the continuous representations of topologies are learned by variational autoencoder (DVAE). Then, the design parameters are optimized by BO. The success rate and optimization efficiency of this framework are significantly better than existing methods. The number of simulations can be reduced by up to 8.15 times, and the generated topologies include both classic structures and innovative schemes. However, the decomposition logic of function-al modules still needs to be designed based on domain knowledge.
4. Zhao et al. [51] proposed the automatic topology synthesis method integrated with frequency compensation mechanism. The topology construction process from scratch is shown in Figure 3 (d). At the same time, the compensation structure without preset compensation templates can be synchronously optimized. This method has been successfully synthesized multi-stage analog circuits that meet stability metrics. The design efficiency is better than the traditional "topology first, then compensation" method.

The corresponding descriptions for Figure 4 (a) in Section 2.2.1 are shown as follows,

1. Zhao et al. [59] proposed a VTSMOC method to optimize multiple competitive black-box objectives. The overall framework is shown in Figure 4 (a) consisting of four key stages: domain decomposition via dynamic Voronoi tree construction, global exploration via Voronoi tree search, batch selection of promising cells, and local exploitation via constrained multi-objective BO (MOBO). This method achieves high sampling efficiency in high-dimensional constrained multi-objective optimization (CMOO) problems while maintaining low computational costs. Verifications on charge pump and amplifier show that the sample efficiency and computational efficiency are significantly better than existing methods.

The corresponding descriptions for Figure 4 (b-g) in Section 2.2.2 are shown as follows,

1. The DNN-Opt framework proposed by Ahmet et al. [60] adopts RL-inspired based on actor-critic (deep neural network (DNN)) architecture to realize the size optimization of analog circuits. The overall framework is shown in Figure 4 (b). First, initial samples are generated from the design space, and pseudo-samples are created to train the critic network for predicting circuit performance. Then, new candidates are produced by the actor network, and the candidates are judged by the critic network. The optimal results can be obtained after the iterations. Verifications on folded cascode operational amplifiers, low dropout (LDO), and other circuits demonstrate that the optimization efficiency can be improved by 5–30 times.
2. Choi et al. [62] proposed the MA-Opt framework, as shown in Figure 4 (c). From the figure, the core architecture is same as DNN-opt. Based on this architecture, parallel training of multiple actors is adopted to share high-quality design schemes in this method. In addition, shared elite solution set and cooperative near-sampling methods are proposed to improve optimization effects. The proposed method is verified on two-stage operational amplifier, three-stage transimpedance amplifier (TIA) and other circuits, and the target metric is improved by 34% compared with DNN-Opt.
3. Yang et al. [66] built a neuron network model to predict the performance metrics of the two-stage Miller-compensated operational amplifier, and the flowchart is shown in Figure 4(d) Compared with traditional optimization design methods, the design time can be shortened by more than ten times.
4. Chen et al. [67] proposed a high-accuracy modeling method for analog ICs based on convolutional neural networks (CNN). The model structure is shown in Figure 4(e). The design parameters are converted into two-dimensional sparse matrix according to the circuit topology, and the mapping relationship can be learned through the CNN. The fitting accuracy (R²) can reach over 99%.
5. Kourosh et al. [68] described each circuit as a graph structure, and GNN can be adopted to learn node relationships to predict output node voltages. The model structure is shown in Figure 4 (f). Studies have shown that predicting output node voltages through a pre-trained GNN model can obtain performance of new topologies, and the sample efficiency is up to 10 times higher than that of randomly initialized models.
6. Wang et al. [70] proposed a topology-general DC model. The model structure is shown in Figure 4 (g). The graph structure can be converted into the circuit netlist, and multiple key performances of amplifier can be predicted through DC parameters based on GNN and attention operations. Verifications on 7 amplifiers with different topologies show that the average MAPE is as low as 0.84%, which is 3.88 times faster than SPICE simulation

The corresponding descriptions for Figure 5 (a), (b), and (d) in Section 2.3.1 are shown as follows,

1. For technology migration of full-flow design, a modeling method combining BO-aided sampling (BOAS) sampling and TL was proposed by Liu et al. [72]. The overall diagram is shown in Figure 5 (a). Firstly, the sample region is initialized, and the region is adjusted via BOAS to filter valid samples. Then, a neural network of source domain is trained. Finally, knowledge of source domain is transferred to the target domain through two augmenting linear layers, which can drastically reduce the number of training samples for the target NN. The schematic-level model can be transferred to the post-layout stage and different technology nodes (45nm/32nm). Verifications on inverters, amplifiers, and digital to analog converter (DAC) show that the dataset for DAC post-layout modeling is reduced by 150 times, and the dataset for amplifier technology migration is reduced by 17 times. The problem of surging data demand caused by technology differences through intelligent sampling has been alleviated. However, the area adjustment strategy of BO sampling relies on prior knowledge of technology differences, and its flexibility is insufficient when adapting to unknown new technologies.
2. Poddar et al. [74] proposed the INSIGHT framework, as shown in Figure 5 (b), which formulates analog circuit performance prediction as an autoregressive sequence generation task. Then, the decoder-based Transformer architecture is adopted to predict the performance cross 45nm/90nm/130nm multi-technology nodes. When transferring the pre-trained model to a new technology node, the high accuracy performance prediction can be achieved with only a small amount of data fine-tuning. The test R² score is ≥0.95, and the training data is reduced by 60%.
3. The KATO framework proposed by Wei et al. [75], as shown in Figure 5 (d), first realizes the knowledge transfer in transistor size optimization across 180nm/40nm technology nodes. The figure depicts the core architecture consisting of an encoder, a decoder, and a neural kernel (Neuk)-enhanced GP. The encoder maps target domain inputs to the source domain space, and the design knowledge is captured by pre-trained source GP. The decoder transforms GP outputs to match target domain metrics. The results show that the number of simulations is reduced by 2 times, and the design performance is improved by 1.2 times. This framework also supports cross-topology transfer, but the knowledge alignment mechanism is highly sensitive to technology differences, which needs careful adjustment of the encoding strategy.

The corresponding descriptions for Figure 5 (c) and (e) in Section 2.3.2 are shown as follows,

1. A graph-guided TL framework for sigma-delta (ΔΣ) ADC was proposed by Wang et al. [77], as shown in Figure 5 (c). Combining graph attention network with RL, the electrical similarity between circuits is identified through graph similarity detection, which realizes model transfer among ΔΣ ADCs with different topologies such as 3rd-order/4th-order cascade of integrators feed forward (CIFF) and cascade resonator feedback (CRFB). The number of system-level simulations of ΔΣ ADC can be reduced by 1.7-11 times, and the power consumption is improved by 12.4%. TL across multiple functional topologies has become an important breakthrough direction.
2. Lee et al. [78] proposed the Trans-Net optimizer. The flowchart is shown in Figure 5 (e) comprising a netlist-mapped circuit matrix, MLP-Mixer modules, a circuit evaluator, and a circuit optimizer. The circuit matrix is generated by one-to-one mapping from SPICE netlists. The MLP-Mixer fuses device and node information. The circuit evaluator predicts circuit performance, while the circuit optimizer generates transistor sizing. Knowledge transfer across five different topologies such as operational amplifiers and comparators is realized. This method can uniformly optimize multiple analog circuits without retraining the model.

The corresponding descriptions for Figure 6 (a-c) in Section 3.1.1 are shown as follows,

1. Mohsen et al. [80] proposed the AnaCraft framework, as shown in Figure 6 (a). The figure illustrates the optimization flow, including interactions between actor/critic networks of PVT and transistor sizing, probabilistic models, and the circuit simulator. An adversarial multi-agent RL architecture is adopted, and the relationship between circuit sizing optimization and PVT conditions is defined as a "collaborative-adversarial" problem. Then, the design parameters are optimized through an actor-critic architecture, and extreme PVT conditions are simulated with circuit simulator to enhance the robustness of design parameters. A 45nm CMOS operational amplifier and a 7nm FinFET data receiver has been optimized. The results show that the number of simulations can be reduced by approximately 3 times, and runtime can be reduced by about 2 times, while satisfying all PVT constraints.
2. Karthik et al. [82] proposed a prioritized RL framework, as shown in Figure 6 (b), which depicts the two-stage critic network. The first stage embeds the design knowledge (analytical design equations, device characteristics, data-driven modeling) to extract key parameters DK(s). The second stage is an augmented critic network Q_DK that integrates the state DK(s) and action for evaluation. High-value training trajectories are prioritized through a non-uniform replay buffer sampling strategy to guide local exploration. A 90nm CMOS two-stage amplifier is optimized, and the optimized results outperforms Monte Carlo, BO, and standard RL methods. Although knowledge integration reduces blind exploration, the quantification and encoding of design knowledge rely on expert experience, which results in insufficient flexibility when adapting to different circuit.
3. Kim et al. [84] proposed the GLOVA framework, as shown in Figure 6 (c). A risk-sensitive RL algorithm is adopted in this framework, and the performance fluctuations caused by PVT conditions are treated as "risk costs" which is integrated into the optimization objective function. An actor-critic framework is introduced to optimize design parameters, and a μ-σ evaluation mechanism is used to quantify the performance mean and fluctuation range of different parameter configurations. Combined with a simulation reordering strategy, high-risk parameter combinations are prioritized for verification to reduce invalid computational costs. Validation on 28nm CMOS strongarm latches shows that this method improves sample efficiency by up to 80.5 times and reduces runtime by 76.0 times, while supporting industrial-grade process corner and Monte Carlo simulation validation.

The corresponding descriptions for Figure 6 (d-e) in Section 3.1.2 are shown as follows,

1. Wei et al. [86] proposed the RobustAnalog framework, as shown in Figure 6 (d). The optimization tasks under different PVT conditions are modeled as an MTL problem, and the multi-task deep deterministic policy gradient (DDPG) algorithm is used to train the model parameters. To alleviate gradient conflicts in multi-task training, a k-means task pruning strategy is introduced to eliminate redundant PVT condition tasks, and gradients are normalized through the PCGrad algorithm. Validations on three types of analog circuits show that the simulation costs can be reduced by 14-30 times compared with BO, Evolution Strategy (ES), standard DDPG, and other methods, while achieving a 100% success rate in passing all PVT condition tests.
2. Li et al. [87] proposed the PVT-Transfer framework, as shown in Figure 6 (e). This framework integrates multi-task optimization and knowledge transfer mechanisms to achieve cross-PVT parameter reuse. High-quality parameter combinations are screened through an assortative mating strategy, and data-driven models are used to capture parameter correlation laws under different PVT conditions. Validations on 180nm CMOS bandgap and three-output voltage reference circuits show that this method reduces the number of simulations by 60% compared with GCN-RL and improves the figure of merit (FoM) by 10 times compared with manual design.

The corresponding descriptions for Figure 7 (a-b) in Section 3.2.1 are shown as follows,

1. Saraju et al. [91] extended this idea by integrating process variations and parasitic effects, and used PSO to optimize transistor size and oxide layer thickness. Figure 7 (a) illustrates the core logic of incorporating manufacturing process variations into design to enhance chip yield. The probability density function (PDF) models are established to provide a foundation for subsequent statistical estimation and circuit optimization. Under worst-case process variations, this method achieves a 25% power reduction and controls the center frequency deviation within 1%.
2. Nuno et al. [94] proposed a layout-aware sizing optimization method. Figure 7 (b) demonstrates a comparison diagram of different optimization-based analog IC sizing methods. The figure distinguishes different performance evaluation paths, which can output the optimal parameters that meets geometric constraints and parasitic requirements, and intuitively demonstrates the integration logic of layout information in sizing. Parasitic effects are estimated through floorplan and global routing, and design parameters are optimized by the NSGA-II algorithm. Validations on two-stage operational amplifiers and folded cascode operational amplifiers with UMC 130nm process show that the parasitic estimation accuracy is close to that of commercial tools, and the optimization time is significantly shortened. However, the parasitic estimation relies on the accuracy of the floorplan.

The corresponding descriptions for Figure 7 (c-d) in Section 3.2.2 are shown as follows,

1. The Berkeley analog generator (BAG) framework proposed by Crossley et al. [98] is a foundational work in this direction, and the optimization process is shown in Figure 7(c). The BAG can implement the entire design flow from specifications to layout consists of two parts: (a) a UML class diagram of the BAG framework; (b) A demonstration of the design flow, covering parametric schematic creation, layout exploration, and generator coding. The full-flow design of VCOs and switched-capacitor regulators with 65nm process are successfully designed by the framework, which demonstrates great potential for electronic design automation.
2. Rafael et al. [100] proposed a method integrating parasitic-aware sizing optimization and geometric constraint sizing optimization, as shown in Figure 7(d). The flowchart takes performance goals, netlists, and geometric requirements as inputs and forms an iterative closed-loop through design space exploration, geometric module optimization, parasitic estimation, and performance evaluation. Through templated layout generation technology, the method extracts parasitic parameters by analytical methods and layout sampling. Geometric objectives such as area and aspect ratio are considered in the optimization. The optimized operational amplifier design meets all electrical and geometric constraints, which can significantly reduce iterations between electrical and physical design.

Comments 3: Related to this, the paper only shows a huge list of design techniques proposed in literature for analog integrated design. In my opinion, some practical examples might be shown to help the comprehension of these techniques. For example, how is an operational amplifier (or any other circuit) designed in practice using these techniques? This would be helpful to understand main points of your analysis, offering also the opportunity to show a critical elaboration of the addressed topic.

Response 3: Thanks for the reviewer’s suggestive comments. To illustrate the practical applicability of the review method, two-stage amplifier, as the typical analog circuits, is selected as the practical examples.

For Section 2.1.1 ‘Topology Synthesis Method Based on Preset Modules’, the practical applications are shown as follows.

  Firstly, the two-stage amplifier is decomposed into serval sub circuit units (such as input stage, amplification stage, compensation stage) according to the topology constraints. Then, MOJITO system, DRL strategy, or AnalogCoder can be adopted to complete the reassembly of sub modules and generate new topologies. The quality of each new topology needs to be evaluated by the circuit simulator, and a new two-stage amplifier topology that meets the design specifications can be generated.

For Section 2.1.2 ‘Topology Fine-Tuning Method Based on Known Structures’, the practical applications are shown as follows.

  Firstly, the mature topology of two-stage amplifier is encoded into a directed acyclic graph DAG. Then, evolutionary algorithms such as NSGA-II, and BO are adopted for structural optimization and parameter adjustment. Finally, the optimized topology is restored through a graphic decoder. To balance the exploration complexity and optimization efficiency, a layered optimization strategy, which optimizes topology structure in the upper layer, optimizes parameter size in the lower layer, and allocates weights through expected functions, can be used. ACOB open-source benchmark library can provide the algorithm evaluation support.

For Section 2.1.3 ‘Topology Optimization Method Generated from Scratch’, the practical applications are shown as follows.

  This method generates a new topology architecture from scratch, without relying on preset templates, and can balance innovative structure exploration and efficient optimization. Firstly, based on design experience, the two-stage amplifier is decomposed into interpretable functional modules such as input stage and amplification stage, or encoded into a deduction tree structure through graph syntax rules. By utilizing the deterministic generation algorithm of FEATS and the two-layer isomorphism checking mechanism, topological uniqueness can be ensured to avoid redundancy. Then, topology optimization technologies such as RL and AnalogGenie are utilized to learn the performance of different topologies, and the optimal new topology can be generated. Finally, the evolutional algorithms can be used to fine tune design parameters and improve core performance such as Av, GBW, and PC.

For Section 2.2.1 ‘Parameter Optimization Methods Based on Intelligent Optimization Algorithms’, the practical applications are shown as follows.

  The core objective of parameters optimization for two-stage amplifier is to automatically find the optimal parameters in the design space. Firstly, the design parameters of two-stage amplifier such as transistor sizes, bias circuit, compensation capacitor and the core performance metrics such as Av, GBW, SR, area, and PC are extracted. Then, a multi-objective optimization function is constructed according to design requirements and constraints. Finally, the design parameters are optimized by intelligent optimization methods such as GA, PSO, and BO. To address the issue of low search efficiency in high-dimensional design space, some mechanisms such as survivability testing, subspace search, and Voronoi tree decomposition are adopted to improve search efficiency. In addition, mixed multi group strategies or adaptive optimization mechanisms can be integrated into the search process to balance global and local exploitation capabilities.

For Section 2.2.2 ‘Parameter Optimization Methods Based on Deep Learning Algorithms’, the practical applications are shown as follows.

  The optimization of two-stage amplifiers base on deep learning methods can be divided into two directions: 1) Firstly, extract the key design parameters and performance metrics of two-stage amplifiers. Construct the actor network to provide the optimization path, and construct the critic network to evaluate the quality of the optimization path. Meanwhile, corresponding reward function should be set. Then, optimization strategies such as DDPG, PPO, and TD3 are adopted. By continuously interacting with the circuit environment, the design space can be efficiently explored. To improve the search efficiency in the high dimensional design space of two-stage amplifiers, multi agent solutions (such as MA Opt and MA-RL) can be adopted. By decomposing two-stage amplifiers into sub blocks, the agent can be parallelly trained, and the elite solutions are shared. 2) During the optimization, it is necessary to constantly run circuit simulators, which can waste a lot of simulation time. Firstly, circuit data of two-stage amplifiers are previously simulated, and the machine learning models such as DNN, GNN, CNN (such as ESSAB, Circuit GNN) are established to learn the complex mapping relationship between design parameters and key performance metrics. Thus, the time-consuming circuit simulations can be replaced to quickly evaluate optimization effects and improve optimization efficiency.

For Section 2.3.1 ‘Transfer Between Different Technology Nodes’, the practical applications are shown as follows.

  The TL of two-stage amplifier across technology nodes requires reusing the design knowledge and model parameters of mature technology nodes. Firstly, a performance prediction model based on DNN, Transformer is trained through the training data. The mapping relationship between the design parameters and performance (such as gain, bandwidth, power consumption) of the two-stage amplifier is learned. Then, the migration strategies of freezing the pre layer, fine-tuning the post layer, and adding the linear layers are adopted to efficiently transfer the source domain knowledge to the target domain, which can significantly reduce the training data (up to 60% reduction) cross different technology nodes.

For Section 3.1.1 ‘Robust Optimization Based on Reinforcement Learning’, the practical applications are shown as follows.

  The fluctuations in the performance of two-stage amplifier can be caused by the variation of PVT condition, and it is necessary to integrate PVT conditions into the optimization process. Firstly, extract multiple performance metrics such as Av, GBW, PC, and analyze the influence of different PVT conditions. Then, the robust optimization function of two-stage amplifier is established. Finally, different robust RL strategies such as AnaCraft, PPAAS, and GLOVA are adopted to introduce PVT conditions into the agent learning process, which can achieve the efficient and robust optimization meeting all PVT constraints.

For Section 3.1.2 ‘Robust Optimization Based on Multi-Task Learning’, the practical applications are shown as follows.

  The parameters optimization for two-stage amplifier in different PVT conditions can be considered as multiple tasks, and the robustness and optimization efficiency are improved through knowledge sharing. Firstly, extract the core performance metrics such as Av, GBW, and PC, and analyze the performance impact under different PVT conditions. Then, an MTL model is constructed to treat each PVT condition as a subtask. By sharing model parameters, KL divergence regularization distillation strategy is used to achieve the reuse of design knowledge across different PVT conditions. In addition, the multi task DDPG algorithm can be trained to capture parameter correlations under different PVT conditions. Finally, key parameters such as transistor size and bias current are iteratively optimized to verify the performance consistency under all PVT conditions.

For Section 3.2.1 ‘Parasitic-Aware Optimization Methods Based on Approximate Parasitic Modeling’, the practical applications are shown as follows.

  Firstly, a parasitic approximation model based on domain knowledge can be constructed through polynomial meta models or parameterized layouts described in GBLD language. Then, based on input noise robustness requirements, intelligent optimization algorithms such as BO, PSO, NSGA-II can be used to iteratively optimize key design parameters such as transistor size and oxide thickness, and reduce the deviation between optimized performance and actual performance. The parasitic estimation accuracy is close to that of commercial tools, which can significantly shorten the design cycle, and achieve efficient and robust optimization of the secondary operational amplifier.

For Section 3.2.2 ‘Parasitic-Aware Optimization Methods Based on Automatic Layout’, the practical applications are shown as follows.

  The optimization loop of "parameter optimization layout generation parasitic feedback" for two-stage amplifier can achieve the combination of preliminary design and physical implementation. Firstly, based on the design specifications of two-stage amplifier, preliminary optimization of transistor parameters is completed through gm/Id method or evolutionary algorithm. Then, the layout of two-stage amplifier can be automatically generated by BAG optimizer, and geometric target constraints such as area and aspect ratio are extracted. Through analytical methods, layout sampling, or magical tools, parasitic parameters can be accurately extracted and fed back to the parameter optimization stage in real time. Key parameters such as transistor size and bias current can be iteratively adjusted to solve the problem of disconnection between early design and physical implementation. Finally, the optimal solution can be found by a small number of simulations, which satisfy all electrical specifications and geometric constraints.

Comments 4: Please, show more details when referring to the tables. The content of each column should be clearly introduced in the text and also more discussion about their content is required.

Response 4: Thanks for the reviewer’s suggestive comments.

The corresponding revisions for Table 1 in Section 2.1.3 are shown as follows,

  Table 1 summarizes the optimization circuits, topology synthesis methods, evaluated methods, and optimization results from three aspects of preset modules-based, known structure-based, and generate from scratch methods. From the table, many circuits topology such as amplifier, voltage references, and VCO are optimized by current research. The key optimized performance metrics such as Av, GBW, PM, PC are listed to verify the effectiveness of the topology synthesis methods, and the generations and running time are summarized to verify the efficiency. From the results, the method based on preset modules has limited on performance improvement due to poor topological flexibility. The method of generating from scratch can discover new circuit structures, but usually require higher computational costs. Hybrid methods such as PGNN combined with NSGA-II or ATOM exhibit a good balance between performance, novelty, and optimization efficiency.

The corresponding revisions for Table 2 in Section 2.2.2 are shown as follows,

  Table 2 summarizes the optimization circuits, optimization methods, technology nodes, and optimization results of efficient parameter optimization methods. Many circuits such as amplifiers, charge pump, VCO, comparator, and LDO circuit under different technology nodes are optimized. Key performance metrics of optimized circuits are listed to verify the optimization effect. Generations and running time are verified the optimization efficiency. The comparison results show that traditional evolutionary algorithms are more robust in performance improvement, but require longer running times; The method based on RL or surrogate models can converge in fewer generations, significantly reducing the overall optimization time, but the quality of the results depends on the model accuracy and training strategy.

The corresponding revisions for Table 3 in Section 2.3.2 are shown as follows,

  To comprehensively compare the transfer effect of all methods, Table 3 summarizes the transferred circuits, transfer methods, transfer range and transfer effect of the present TL methods. Amplifiers, ∆Σ DAC, bandgap reference, TIA, LDO, and CT ∆Σ ADC are transferred. Different transfer strategies (freezing network layers) and hybrid strategies are listed by reusing existing design or model knowledge. In addition, the specific scenarios of TL including different technology nodes (such as 180 nm → 65 nm, 45 nm → 32 nm), and different topology structures (such as Two TIA ↔ Three TIA、CIFF ↔ CRFB) are summarized. From the results, the TL effect is mainly reflected in three aspects: 1) the improvement of circuit performance, such as the improvement of PC, Av, GBW, and FoM; 2) The improvement of optimization efficiency, including a significant reduction in the number of simulation samples, iteration times, and design time; 3) The feasibility of implementing structural evolution or order expansion in complex systems.

The corresponding revisions for Table 4 in Section 3.1.2 are shown as follows,

  Table 4 summarizes the optimized circuits, optimization methods, technology nodes, and robust optimization results for the comparison of robust optimization effects when considering PVT conditions. Many circuits such as amplifiers, LDO, FIA, OSCA, and BGR, are optimized. The optimization effects of each method in robust design are listed, mainly including: 1) the reduction of required number of simulation samples and simulations, 2) the improvement of simulation and optimization efficiency, 3) the improvement of the overall FoM while meeting all PVT corner validations. The comparison results show that most methods achieve an order of magnitude efficiency improvement while ensuring that all PVT conditions are met, reflecting the significant advantages of intelligent robust optimization in complex circuit design problem.

Comments 5: It is suggested adding the following papers in the introduction, which give practical examples where the adoption of optimized strategies for analog design might be possible:

1. Zhong, X. Yang, R. P. Martins, Y. Zhu and C. -H. Chan, "A 0.016mm2 Active Area 4GHz Fully Ring-Oscillator-Based Cascaded Fractional-N PLL With Burst-Mode Sampling," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no. 10, pp. 3792-3796, Oct. 2023, doi: 10.1109/TCSII.2023.3288120.
2. Tegazzini, G. Di Meo, D. De Caro and A. G. M. Strollo, "High-Precision MUX-Based Digital Delay Interpolators Based on a Novel Transistor Sizing Algorithm," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 72, no. 7, pp. 938-942, July 2025, doi: 10.1109/TCSII.2025.3571482.

Response 5: Thanks for the reviewer’s suggestive comments. The following papers are cited as ‘With the continuous evolution of CMOS technology toward deep submicron and advanced nodes, non-ideal effects have been significantly enhanced, and the impacts of PVT variations, mismatches, and parasitic effect on circuit performance have become increasingly prominent, which has posed severe challenges to the traditional experience-based design methods [9-12].’ in the introduction to give practical examples.

Author Response File: Author Response.docx

Reviewer 2 Report

Comments and Suggestions for Authors

In this manuscript, the optimization design methods for analog ICs are reviewed. It is an interesting topic on the development of analog IC design methodology. The review is systematic organized by the authors. However, following issues should be addressed:

1. There are many typos and grammar mistakes in the manuscript. Please polish the English to meet the publication standard.
2. Some repetitive expression in the manuscript, which should be refined. 
3. The influence of PVT, especially the process variations, on the performance of analog circuit, plays more and  more important roles in some advanced analog ICs. The most advanced analog IC with the highest performance, should consider the process influences. Authors should supplement the consideration on this part.

Author Response

Comments 1: There are many typos and grammar mistakes in the manuscript. Please polish the English to meet the publication standard.

Response 1: Thanks for the reviewer’s suggestive comments. The manuscript has been carefully checked, and the English has been polished. The corresponding modifications have been highlighted in the manuscript. Thanks!

Comments 2: Some repetitive expression in the manuscript, which should be refined.

Response 2: Thanks for the reviewer’s suggestive comments. The corresponding repetitive expression has been refined. The corresponding modifications have been highlighted in the manuscript. Thanks!

Comments 3: The influence of PVT, especially the process variations, on the performance of analog circuit, plays more and more important roles in some advanced analog ICs. The most advanced analog IC with the highest performance, should consider the process influences. Authors should supplement the consideration on this part.

Response 3:

Thanks for the reviewer’s suggestive comments. In addition to PVT, the impact of process changes on high-performance analog circuits is also significant. When the process changes, the topology structure of the circuit is not altered, and the electrical characteristics and parasitic effects of the circuit can be changed. Therefore, by learning circuit topology information, optimization algorithms can optimize design parameters under different technology nodes. Many researches have been conducted on robust optimization under process changes. Liu et al. [72] proposed a TL optimization method combined with BO assisted sampling (BOAS) to reduce the training dataset size required for NN models under different technology nodes. A 17 times reduction can be achieved in amplifier dataset in the technology nodes migration stage. Xinget al. [75] first proposed a knowledge alignment and transfer optimization (KATO) system to achieve the optimization under process changes. Two-stage and three-stage OpAmps in the 40 nm and 180 nm technology nodes are optimized. Compared with the benchmark scheme, it can achieve up to 2 times the simulation reduction and 1.2 times the design improvement. Wang et al. [76] proposed GCN-RL method. GCN model is introduced in actor networks which can learn circuit topology representations. The circuit performance among 5 technology nodes can be optimized. The method outperforms other schemes in terms of knowledge transfer ability, achieving better FoM. Lee et al. [78] defined circuit topology by mapping the Spice netlist one-to-one, learned shared information between circuit topologies, and achieved knowledge transfer across technology nodes. The experiment results show that the FoM of 5 circuits under 45, 65, 180 nm technology nodes are better than GCN-RL, CAN-RL methods. The corresponding modifications have been made in SECTION ‘III. Robust Optimization Design Methodology for High-Performance Analog ICs’ (3.1.1 Robust Optimization Based on Reinforcement Learning). Thanks!

Author Response File: Author Response.docx

Round 2

Reviewer 1 Report

Comments and Suggestions for Authors

The authors extensively reponded to my comments improving the quality of the text. From my side, there are no further comments.

Reviewer 2 Report

Comments and Suggestions for Authors

The revised version has addressed the comments. It can be accepted now.