Correction: Hsieh et al. Single-Grain Gate-All-Around Si Nanowire FET Using Low-Thermal-Budget Processes for Monolithic Three-Dimensional Integrated Circuits. Micromachines 2020, 11, 741

1. Error in Figure 2

In the original publication [1], there was a mistake in Figure 2 as published. In the paper, we demonstrated monolithic 3D GAA-FETs using low thermal budget processes that have been proved and partially disclosed for monolithic 3D stacking in past conference papers [2,3]. In Figure 2a, the original FIB image was selected from IEDM2016 to represent the sequential 3DIC. It should be the same as the image we published in IEDM2016. However, it seems that it was a mirror image in this paper. After discussion, this might be due to an editing error when we labeled the text in the image and rearranged the figure. Unfortunately, the original FIB file was lost. To correct this error, we prepared another FIB image (supporting FIB image) instead and modified the figure caption accordingly (Figure 2 and caption). The corrected Figure 2 appears below.

2. Error in Figure 6

In the original publication, there was a mistake in Figure 6 as published. The TEM images were cut, and the scale bar was redrawn to present clearer information in this paper. However, the numbers of the scale bar in this paper seem incorrect compared to the image we published in Figure 2b in 2015 IEDM [3]. This might be due to an unconscious editing error when we rearranged the image and edited Figure 6b. To correct this issue, we prepared another TEM image of the Si FET (supporting TEM image) using the same silicide process conditions and device structure. The corrected Figure 6 appears below. The authors state that the scientific conclusions are unaffected. This correction was approved by the Academic Editor. The original publication has also been updated.

3. Text Correction

There was an error in the original publication. The last sentence on page 3 of 12 in our Micromachines paper (doi:10.3390/mi11080741) “A two tier monolithic 3D-IC can be simply realized by repeating the whole low-thermal budget processes (T_sub < 400 °C) (Figure 2a,b).” needs a more detailed description.

A correction has been made to the last sentence on page 3 of 12 in our Micromachines paper (doi:10.3390/mi11080741):

A two-tier monolithic 3D-IC can be simply realized by repeating the whole low-thermal budget processes (T_sub < 400 °C) as we have shown in IEDM 2016 [2]. Figure 2a shows a two-tier monolithic 3D-IC having a metal interconnect to connect the top and bottom Si FETs. By using the proposed single-grain GAA Si NW FETs, the monolithic 3DIC will have better system performance, as illustrated in Figure 2b.

4. Missing Citation

In the original publication, reference 40 was not cited [3]. The citation has now been inserted on page 8 of 12, line 6, and should read:

The mixing of Ni₂Si and Si occurs via liquid phase diffusion [38], which leads to a uniform NiSi film without heterogeneous aggregation and spike at the interface between the NiSi and the Si, which is confirmed in Figure 6b,c [40].

The authors state that the scientific conclusions are unaffected. This correction was approved by the Academic Editor. The original publication has also been updated.