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Micromachines
Volume 16
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10.3390/mi16101096
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Article

Reduction Method for a Network-on-Chip Low-Level Modeling

by
Evgeny V. Lezhnev
1,
Aleksandr Y. Romanov
1,*,
Dmitry V. Telpukhov
2,
Roman A. Solovyev
2 and
Mikhail Y. Romashikhin
1
1
HSE University, 101000 Moscow, Russia
2
AlphaChip LLC., 124498 Moscow, Russia
*
Author to whom correspondence should be addressed.
Micromachines 2025, 16(10), 1096; https://doi.org/10.3390/mi16101096
Submission received: 24 July 2025 / Revised: 10 September 2025 / Accepted: 22 September 2025 / Published: 26 September 2025
(This article belongs to the Section E：Engineering and Technology)
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Abstract

This article explores the concept of low-level modeling of networks-on-chip (NoCs). A method for reducing the low-level NoC model by replacing the real IP blocks with a data packet generator module is proposed. This method is implemented in the low-level NoC modeling ECAD tool HDLNoCGen. This makes it possible to significantly increase the maximum number of nodes in the simulated NoC, as well as speed up the modeling and investigate the resource costs for network synthesis. A universal interface that can be used to connect new components to the network is also described. This interface has two main benefits: it reduces connection resource costs by eliminating the need to modify the connected component and shortens the time required to configure the connection interface itself. The proposed methodology of low-level NoC modeling is shown to be effective in analyzing the operation of routing algorithms of the NoC communication subsystem based on various topologies.
Keywords: computer-aided design (CAD); network-on-chip (NoC); RTL; HDL; modeling computer-aided design (CAD); network-on-chip (NoC); RTL; HDL; modeling

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MDPI and ACS Style

Lezhnev, E.V.; Romanov, A.Y.; Telpukhov, D.V.; Solovyev, R.A.; Romashikhin, M.Y. Reduction Method for a Network-on-Chip Low-Level Modeling. Micromachines 2025, 16, 1096. https://doi.org/10.3390/mi16101096

AMA Style

Lezhnev EV, Romanov AY, Telpukhov DV, Solovyev RA, Romashikhin MY. Reduction Method for a Network-on-Chip Low-Level Modeling. Micromachines. 2025; 16(10):1096. https://doi.org/10.3390/mi16101096

Chicago/Turabian Style

Lezhnev, Evgeny V., Aleksandr Y. Romanov, Dmitry V. Telpukhov, Roman A. Solovyev, and Mikhail Y. Romashikhin. 2025. "Reduction Method for a Network-on-Chip Low-Level Modeling" Micromachines 16, no. 10: 1096. https://doi.org/10.3390/mi16101096

APA Style

Lezhnev, E. V., Romanov, A. Y., Telpukhov, D. V., Solovyev, R. A., & Romashikhin, M. Y. (2025). Reduction Method for a Network-on-Chip Low-Level Modeling. Micromachines, 16(10), 1096. https://doi.org/10.3390/mi16101096

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