# Modeling and Analysis of Wide Frequency Band Coaxial TSV Transmission Interconnect

^{*}

## Abstract

**:**

_{11}and S

_{21}parameters are 0.4% and 0.18%, respectively, which proves the validity of the equivalent circuit modeling in this paper. Finally, parametric analysis is performed to investigate the effect of different model parameters on the signal-transmission characteristics of the CTSV interconnect.

## 1. Introduction

- (1)
- Accurate equivalent circuit model containing CTSV, RDL, and bump is built.
- (2)
- Due to the accuracy of distributed parameter circuits at high frequencies [21], the equivalent circuit model can perfectly match the actual situation more than 100 GHz.
- (3)
- The influence of different parameters on transmission characteristics of the CTSV interconnect is studied, providing a basis for the CTSV interconnect design.

## 2. 3D Structural Modeling and Equivalent Circuit Extraction of the CTSV Interconnect

#### 2.1. Equivalent Circuit Extraction of the CTSV

_{Si}characterizes the influence of intermediate silicon substrate capacitance, G

_{Si}characterizes the influence of intermediate silicon substrate conductance, C

_{ox1}characterizes the influence of internal oxide layer capacitance, C

_{ox2}characterizes the influence of external oxide layer capacitance, C

_{d1}characterizes the influence of internal depletion layer capacitance, C

_{d2}characterizes the influence of external depletion layer capacitance, C

_{1}characterizes the series connection of internal oxide capacitance and internal depletion layer capacitance, C

_{2}characterizes the series connection of external oxide capacitance and external depletion layer capacitance, $\mathsf{\delta}$ characterizes skin depth, L

_{1}and R

_{1}characterize the influence of internal metal conductor, and L

_{2}and R

_{2}characterize the influence of external shielding layer metal.

_{Si}, G

_{Si}, C

_{ox1}, C

_{ox2}, C

_{d1}, C

_{d2}, C

_{1}, and C

_{2}are shown from Equations (5) to (12).

_{1}and L

_{2}are shown from Equations (13) and (14).

#### 2.2. Equivalent Circuit Extraction of the RDL

_{cylinder}and L

_{cylinder}represent the influence of the cylindrical metal in the vertical direction of the RDL, R

_{flat}and L

_{flat}represent the influence of the square metal in the horizontal direction of the RDL, and C

_{V}characterizes the capacitance effect due to the presence of the BCB insulation layer between the square metal plane of the RDL and the conductive part of the CTSV.

_{cylinder}, L

_{cylinder}, R

_{flat}, L

_{flat}, and C

_{V}are shown from Equations (22) to (30).

#### 2.3. Equivalent Circuit Extraction of the Bump

_{b}and L

_{b}characterize the effect of the metal cylinder part, and C

_{b}characterizes the capacitive effect between the metal cylinder and adjacent conductor of the RDL.

_{b}, L

_{b}and C

_{b}are shown from Equations (31) to (35).

## 3. Simulation and Verification

_{11}curves of the 3D model and the equivalent circuit model are in perfect agreement in the frequency range from 0.1 to 120 GHz, and the simulation error is basically no more than 1%. The S

_{21}curves agree better, especially around the desired 100 GHz frequency, in which the maximum error is no more than 0.48%. These errors mainly come from parasitic resistance, capacitance, and inductance, among which the errors caused by parasitic capacitance are obvious at low frequencies, the errors caused by parasitic inductance are obvious at high frequencies, and the contributions of parasitic resistance to the errors are almost the same at different frequencies [13]. In order to reduce these errors, we adopt the distributed parameter method when establishing the equivalent circuit model and consider parasitic effects into the circuit model. We compare the simulation results of the obtained circuit model with those in HFSS, analyze the reasons for the differences between the two at different frequencies, continuously optimize the obtained circuit model, and finally obtain an equivalent circuit model with the minimum error.

## 4. Parametric Analysis

#### 4.1. Scanning Analysis of CTSV Height

_{11}increases and S

_{21}decreases with the increasing CTSV height. The reason is that as the CTSV height increases, the signal-transmission distance becomes larger and the associated parasitic parameters become larger, especially the effect of parasitic capacitance. The larger parasitic parameters make the attenuation of the signal increase and the transmission quality decrease, so small CTSV height is more favorable for the signal transmission. At the same time, however, from the process point of view, a small CTSV height will reduce the depth-to-width ratio of the CTSV, increase the difficulty of production, and decrease the distance between different chips, which is likely to occur in coupling.

#### 4.2. Scanning Analysis of RDL Width and Thickness

#### 4.3. Scanning Analysis of Bump Height

_{11}decreases slightly with the increase of bump height, and within a certain range, S

_{21}increases with the increase of bump height, which indicates that the signal-transmission performance becomes better as the bump height increases. But this effect is no longer significant when the bump height is greater than 3.5 μm. The reason of which is related to the impedance matching of the bump signal port.

## 5. Conclusions

## Author Contributions

## Funding

## Informed Consent Statement

## Data Availability Statement

## Conflicts of Interest

## References

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**Figure 10.**Comparison of simulation results of S

_{11}and S

_{21}of the CTSV interconnect at different widths (

**A**) and thicknesses (

**B**).

Parameter | Symbol/Unit | Value |
---|---|---|

CTSV height | h_{CTSV}/μm | 90 |

Inner Cu cylinder radius of the CTSV | r_{1}/μm | 5 |

Outside diameter of internal insulation of the CTSV | r_{2}/μm | 5.5 |

Outside diameter of internal depletion region of the CTSV | r_{3}/μm | 6.4 |

Outside diameter of Si substrate of the CTSV | r_{4}/μm | 7.6 |

Outside diameter of external depletion region of the CTSV | r_{5}/μm | 8.5 |

Outside diameter of middle insulation of the CTSV | r_{6}/μm | 9 |

Outside diameter of external Cu cylinder of the CTSV | r_{7}/μm | 10 |

Outside diameter of external insulation of the CTSV | r_{8}/μm | 10.5 |

Metal cylindrical radius of the RDL | r_{RDL}/μm | 5 |

Metal cylindrical height of the RDL | h_{RDL}/μm | 3 |

Metal flat length of the RDL | l_{RDL}/μm | 100 |

Metal flat width of the RDL | w_{RDL}/μm | 10 |

Metal flat thickness of the RDL | t_{RDL}/μm | 1 |

Distance between RDL and CTSV | d_{RDL}/μm | 3 |

Area between the RDL metal flat and the CTSV conductor section | S_{RDL}/μm^{2} | 28.36 |

Metal cylindrical radius of the bump | r_{bump}/μm | 5 |

Metal cylindrical height of the bump | h_{bump}/μm | 3 |

Equivalent distance between the bump metal cylinder and adjacent conductor | d_{bump}/μm | 1.8 |

Equivalent area between the bump metal cylinder and adjacent conductor | S_{bump}/μm^{2} | 15.7 |

Relative permittivity of oxide | ε_{ox}/1 | 4 |

Relative permittivity of Si | ε_{Si}/1 | 11.9 |

Relative permittivity of depletion region | ε_{ox}/1 | 11.9 |

Conductivity of Si | σ_{Si}/(S/m) | 7.1 |

Conductivity of Cu | σ_{Cu}/(S/m) | 5.8 × 10^{7} |

Resistivity of Cu | ρ/(Ω·m) | 1.8 × 10^{−8} |

Relative permeability of Cu | μ/1 | 9.999 × 10^{−1} |

Relative permittivity of BCD | ε_{BCD}/1 | 2.6 |

Operating angle frequency | ω/(rad/s) | 200π |

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**MDPI and ACS Style**

Zhang, Y.; Zhi, C.; Dong, G.
Modeling and Analysis of Wide Frequency Band Coaxial TSV Transmission Interconnect. *Micromachines* **2024**, *15*, 1127.
https://doi.org/10.3390/mi15091127

**AMA Style**

Zhang Y, Zhi C, Dong G.
Modeling and Analysis of Wide Frequency Band Coaxial TSV Transmission Interconnect. *Micromachines*. 2024; 15(9):1127.
https://doi.org/10.3390/mi15091127

**Chicago/Turabian Style**

Zhang, Yujie, Changle Zhi, and Gang Dong.
2024. "Modeling and Analysis of Wide Frequency Band Coaxial TSV Transmission Interconnect" *Micromachines* 15, no. 9: 1127.
https://doi.org/10.3390/mi15091127