Degradation Measurement and Modelling under Ageing in a 16 nm FinFET FPGA

Round 1

Reviewer 1 Report

Comments and Suggestions for Authors

There were several attempts to model degradation on FPGA devices. the current presentation provide nice overview on previous attemts ans propose a model to emulate the degredation.

I have several comments to the authors:

In the introduction the authors claim: "The common failure mode for all three mechanisms is the progressive degradation of the transistor threshold voltage. This mechanism is not true for TDDB

the authors describe in detail a simulation before ageing, they compare the propagation times measured with those estimated by the design software (Vivado) and reflect to measurements. the methodology is not clear and especially the motivation for this process. what is the purpose of this simulations?

Fig 5 the leters a and b are cut, the linear fit should be horizontal

Fig 6 the temperatures should be mentioned over the figures

author proposes a semi-empirical model for agins. you need to pecify precisely how this model is derived – this model is relatively accepted for NBTI – you need to add references!

 The authors made very eloquent presentation of the process performance using the alfa dispersion factor however it is not clear how this presentation can help in correlating the actual effect of the degradation when we take silicon with different process corners

I assume that The parameters extraction in table 2 was done using the regression tools, however since there are so many degrees of freedom it is necessary to add the errors expected from this regression

Author Response

Dear Reviewer,

We would like to thank you for your careful review of the document and for your constructive comments and suggestions. Please find attached responses and modifications to your comments. 

Best regards

Author Response File: Author Response.pdf

Reviewer 2 Report

Comments and Suggestions for Authors

The authors conducted a comprehensive reliability study of an FPGA ring oscillator circuit using 16 nm FinFET technology and compared it with 28 nm MOSFET technology. They also built an empirical model to predict the variation of propagation time in ROs with aging time, temperature, voltage, stress duty cycle, and FPGA resources. Overall, the manuscript is carefully documented, but the text is too lengthy for the subject.

This work characterized the reliability of FGPA boards fabricated using 16 nm and 28 nm technologies. However, the reliability of the FPGA board is affected by many aspects. The 16 nm and 28 nm FET device technology may not be the critical factor, Packaging and FPGA design rules can be more dominant in reliability. Therefore, the measurements and models made in this work may not be applicable to other digital circuits and FPGAs produced by other brands, making this study less meaningful. 

The authors have published some very similar work (refs [25], [27] and ref [34]) which appear to cover most of Sections 2 and 3 of this manuscript. What is the novelty and contribution of this work after removing the published parts in [25][27] and [34]?

There are many mistakes in figure numbering and section numbering.

Comments on the Quality of English Language

Many typos, please proofread the entire manuscript.

Author Response

Dear Reviewer,

We would like to thank you for your careful review of the document and for your constructive comments and suggestions. Please find in attachment responses and modifications to your comments. 

Best regards

Author Response File: Author Response.pdf

Reviewer 3 Report

Comments and Suggestions for Authors

In this work, the authors presented a comprehensive reliability analysis of the 16nm FinFET and FPGA ring RO with different temperature and voltage stresses aged for 8000 hours and compared with conventional MOSFET FPGA. This paper provides valuable insights into the FinFET transistors reliability characterization under moderate stress conditions and long aging times, and thus is suitable for the Micromachines journal publication. Yet there are still a few points left in the current manuscript that require further discussion, and thus I would recommend minor visions before publishing:

 

·        The stress conditions used in this paper (Vnom ≤ Vstress ≤ 1.3Vnom and 25C ≤ Tstress ≤ 115C) are less aggressive than the conditions used in the HKMG FPGA in ref [25] (Vnom ≤ Vstress ≤ 1.5Vnom and 55C ≤ Tstress ≤ 115C), but the activation energy Ea is still higher – could the authors comment more on that? Is this related to the intrinsic difference between FinFET vs planar MOSFET difference or extrinsic setup conditions other than voltage and temperature?

·        Could the authors compare the results from this study with state-of-the-art FinFET aging reports in Section 1.2? Is it possible to segment out PBTI vs NBTI contributions in the current setup?

 

·        Small spelling error correction: it should be “aging” instead of “ageing”.

Author Response

Dear Reviewer,

We would like to thank you for your careful review of the document and for your constructive comments and suggestions. You will find in attachment answers and modifications to your comments. 

Sincerely

Author Response File: Author Response.pdf

Round 2

Reviewer 2 Report

Comments and Suggestions for Authors

The authors have responded to the questions in the response letter. However, they made no (or they did not mark any) modifications in the revised manuscript. Again, there are many failure mechanisms in FPGAs, and it would be unreasonable to make assumptions about the reliability of the FETs without discussing them. Inexperienced readers may also be misled.

Comments on the Quality of English Language

English looks good

Author Response

Please see the attachment

Author Response File: Author Response.pdf