Yang, J.; Huang, Z.; Wang, D.; Liu, T.; Sun, X.; Qian, L.; Pan, Z.; Xu, S.; Wang, C.; Wu, C.;
et al. A Novel Scheme for Full Bottom Dielectric Isolation in Stacked Si Nanosheet Gate-All-Around Transistors. Micromachines 2023, 14, 1107.
https://doi.org/10.3390/mi14061107
AMA Style
Yang J, Huang Z, Wang D, Liu T, Sun X, Qian L, Pan Z, Xu S, Wang C, Wu C,
et al. A Novel Scheme for Full Bottom Dielectric Isolation in Stacked Si Nanosheet Gate-All-Around Transistors. Micromachines. 2023; 14(6):1107.
https://doi.org/10.3390/mi14061107
Chicago/Turabian Style
Yang, Jingwen, Ziqiang Huang, Dawei Wang, Tao Liu, Xin Sun, Lewen Qian, Zhecheng Pan, Saisheng Xu, Chen Wang, Chunlei Wu,
and et al. 2023. "A Novel Scheme for Full Bottom Dielectric Isolation in Stacked Si Nanosheet Gate-All-Around Transistors" Micromachines 14, no. 6: 1107.
https://doi.org/10.3390/mi14061107
APA Style
Yang, J., Huang, Z., Wang, D., Liu, T., Sun, X., Qian, L., Pan, Z., Xu, S., Wang, C., Wu, C., Xu, M., & Zhang, D. W.
(2023). A Novel Scheme for Full Bottom Dielectric Isolation in Stacked Si Nanosheet Gate-All-Around Transistors. Micromachines, 14(6), 1107.
https://doi.org/10.3390/mi14061107
