SiC Heterojunction Trench MOSFET with a Buried P-Type Pillar for the Low Gate-Drain Charge and Switching Loss

Abstract

A novel Silicon-Carbide heterojunction U-MOSFET embedded a P-type pillar buried in the drift layer (BP-TMOS) is proposed and simulated in this study. When functioning in the on state, the merged heterojunction structure will control the parasitic body diode, and the switching loss will decrease. Moreover, to lighten the electric field on the gate oxide corner, a high-doped L-shaped P⁺ layer near the heterojunction beneath the gate oxide was introduced; thus, the gate oxide reliability improved. A p-type pillar is introduced in the drift layer. The p-type pillar can assistant the drift layer to deplete. Thus, the specific on-resistance for BP-TMOS can be reduced with an increase in the N-drift region’s doping concentration. Compared to the traditional SiC MOSFET (C-TMOS), the specific on-resistance decreased by 20.4%, and the breakdown voltage increased by 53.7% for BP-TMOS, respectively. Meanwhile the device exhibits a 55% decrease and a 69.7% decrease for the switching loss and gate to drain charge.

1. Introduction

Over the years, the wide band-gap material has become a new research topic in the power devices. Silicon–carbide devices is a major type used in the power systems. The low on-state resistance, higher power density, increased high work frequency, and the widely forbidden band all stand out [1,2,3]. The small size and high reliability of the SiC MOSFET are both necessary to minish power dissipation and increase the efficiency. To avoid the aged deterioration effect, when the SiC MOSFET is used in the power system, usually paralleled with a Schottky barrier diode (SBD) [4,5,6,7], it may cause more energy dissipation and undesirable stray inductances. In order to obtain the optimised the reverse recovery performance and reduce switching loss, several papers have proposed several structures, for example, using a SBD paralleled with the SiC trench MOSFET [8,9,10,11,12]. In addition, in the trench SiC MOSFET, the gate oxide corner reliability is also an issue of interest. Under the trench gate, surrounding a highly doped P+ layer is an effective method.

Compared to the SiC SBD, two types of poly-silicon/SiC formed the heterojunction diode, which have better performance on the third quadrant. In this paper, the novel structure that buried a P-type pillar in drift layer has been researched. In addition to the optimised reverse recovery performance and the reduced the switching loss from the Heterojunction diode (HJD) in the drift region, the assist depletion effect from the P-pillar can bring a better balance among the specific on-resistance (R_on,sp) and the breakdown voltage (BV). The dynamic and static performances of the proposed structure have been carefully investigated.

2. Device Structure and Mechanism

Figure 1a,b show the structures of the BP-TMOS that buried a P-type pillar and the traditional SiC MOSFET(C-TMOS). The energy band along the poly-silicon/SiC in the BP-TMOS is also shown in Figure 1c. In comaprison to the traditional one, BP-TMOS also has a heterojuction structure, which is composed of the poly-silicon/SiC. The heterojuction structure has a conduction band of 0.45 eV and valence band of 1.73 eV, respectively. An electron barrier height Φ_BN (about 1.48 eV) is caused by conduction band E_C and the Fermi-band E_f. When the device is in a forward state, the height of this barrier will result in a smaller forward voltage (V_F). Conversely, in a reverse position, the breakdown voltage BV is enhanced. Beneath the gate oxide and near the heterojunction, using a highly doped L-shaped P+ region reduced the gate oxide maximum electric field and improved the gate oxide layer’s reliability [13,14,15]. In addition, in the drift region near the gate oxide corner, the electric field concentration can lower by the L-shaped P+ layer and narrow the overlap area between the drift layer and the gate oxide layer and, thus, can achieve a fast-switching time and a high BV. From the work mechanism, the P-type pillar will afford an assistant depletion effect. Thus, the lateral P-pillar/N-drift junction and the vertical P-base/N-drift junction consist of the total depletion in drift layer. The drift layer doping concentration can be increased. Therefore, R_on,sp can be reduced and BV can be increased at the same time.

For practice, the device was placed in a tape-out process at the interface of SiO₂, and SiC introduced the traps with a uniform concentration 5 × 10¹² eV⁻¹ cm⁻².

Table 1. The main parameters of the devices.

Parameter	C-TMOS	BP-TMOS	Unit
N drift doping, ND	7.5 × 1015	optimised	cm−3
N drift thickness, LD	8	7.6	μm
P+ layer doping, NP+	1 × 1019	1 × 1019	cm−3
P well doping, Npwell	3 × 1017	3 × 1017	cm−3
CSL layer thickness, TCSL	0.4	0.8	μm
CSL layer doping, NCSL	2 × 1016	2 × 1016	cm−3
P well thickness, Tpwell	0.8	0.8	μm
Gate width, Wtrench	0.7	0.7	0.7
LP-poly	/	1	μm
LP	/	0.4	μm
P-pillar doping, NP	/	optimised	cm−3
P-pillar width, WP	/	optimised	μm
P-pillar length, TP	/	optimised	μm

lists the basic parameters of the two devices. In this paper, the devices were analysed by the Sentaurus TCAD tool. In a recombination process, Auger recombination, Shockley–Read–Hall (SRH), and doping-dependent methods are used, and Okuto–Crowell models are used in the electron/hole continuity equations [16]. The mobility model used Enormal, high-field velocity saturation, and incomplete ionization.

3. Results and Discussions

Figure 2 shows the FoM (Figure of Merit, BV²/R_on) with different W_P and T_P for the BP-TMOS. Fixing a certain T_P of 3.8 μm, 5.7 μm, or 7.6 μm, FoM increases at first and then declines with an increase in W_P. There is a maximum point for the FoM. The T_P is chosen when it is equal to the drift thickness (L_D), and W_P is chosen when the largest FoM is obtained. Just as shown in Figure 2, the optimised values of W_P and T_P are 0.5 μm and 7.6 μm for BP-TMOS, respectively.

Figure 3 provides the off-state characteristics about the proposed one and the traditional one. Figure 3a includes the off-state I-V curves. It clearly shows that the BVs of BP-TMOS and C-TMOS are 1180 V and 773 V, respectively. The total drain-source current I_ds achieves 10 μA/cm² when considering its breakdown. Figure 3b shows the electric field distributions of BP-TMOS and C-TMOS on the vertical direction when the breakdown takes place. The electric field distribution in drift layer of BP-TMOS is uniform due to the assistant depletion effect of the P-pillar and wider P+ layer; thus, it has a higher BV.

Figure 4 provides the 2D electric field graphics of BP-TMOS and C-TMOS in the same drain voltage of 650 V. For BP-TMOS, the gate oxide corner maximum electric field (E_ox) is 1.2 MV/cm, which is lower than 1.45 MV/cm for the C-TMOS. That is to say that the gate oxide reliability of BP-TMOS is better. In addition, the SiC region maximum electric field (E_SiC) in BP-TMOS is also much lower, which means the premature breakdown near the P+ shielding layer is restrained for BP-TMOS, and a higher BV is, therefore, obtained as shown in Figure 3.

Figure 5 provides the devices’ electric performances with different structure parameters. Figure 5a shows the dependences on BV with different N_P and N_D for the BP-TMOS. It can be observed that there is a maximum point of BV for certain N_D. Due to mutual depletion, a higher N_D needs a higher N_P to obtain the maximum BV. Figure 5b provides the optimizations of BV and R_on,sp for BP-TMOS and C-TMOS. The criteria conditions include FoM. The optimised value of N_D for BP-TMOS is chosen as 1.5 × 10¹⁶ cm⁻³, while in C-TMOS, it is 7.5 × 10¹⁵ cm⁻³, and an N_P of 8.1 × 10¹⁶ cm⁻³ was chosen. Compared to C-TMOS, BP-TMOS has a larger FoM.

Figure 6 shows the third quadrant I-V curves for C-TMOS and BP-TMOS. It is obvious that the reverse voltage (V_F) of BP-TMOS is far below C-TMOS because of HJD; as a result, BP-TMOS has a small dead-time loss. Moreover, just as Figure 6b shows, when the drain hole current I_dsH = 10 A/cm², the reverse voltage (V_PN) of the BP-TMOS increases to 3.4 V, while the V_PN of the C-TMOS is 2.7 V. This indicated that BP-TMOS has a large turn-on voltage relative to the body diode; thus, unwanted consumption can be controlled.

Figure 7 shows the dependences between the gate voltage (V_g) and gate charge (Q_g) of the devices. The active device area is set to be 1 cm². The Q_g and the gate-drain charge (Q_gd) are 525 nC/cm² and 50 nC/cm² for BP-TMOS, respectively, which are both smaller than 775 nC/cm² and 165 nC/cm² of C-TMOS. This is because there is a L-shaped P+ layer in the BP-MOSFET, which reduces the overlap area between the drift region and the gate oxide.

The switching performances analysis of the two devices used mixed-mode simulation in a double-pulse test. Figure 8 shows the switching performances for the two devices. Although SiC SBD has been used when simulating C-TMOS, BP-TMOS still has a small current spike in the turn-on state compared to C-TMOS.

Figure 9 shows test circuit and switching losses. Figure 9b shows the switching loss results for the two devices. In comparison to C-TMOS, BP-TMOS has 55% decrease. The smaller Q_gd charge and the introduced heterojunction structure are the pivotal elements for the low switching loss.

Table 2. Basic device characteristics.

Parameter	C-TMOS	BP-TMOS
Ron,sp (mΩ·cm2)	1.86	1.48
BV (V)	773	1180
Qg (nC/cm2)	775	525
Qgd (nC/cm2)	165	50
FoM (MW/cm2)	321	940
VF (V)	2.7	3.4

summarises device performances, and BP-TMOS has a better comprehensive performances.

A feasible fabrication procedure of the proposed device is provided in Figure 10. The double epitaxial layers including N drift and CSL are grown on the N substrate layer by chemical vapour deposition (CVD). The P-type layer in N drift used dose aluminium implantation. The P + shielding layer and the floating guard rings in termination region are formed simultaneously by heavy-dose aluminium implantation at 500 °C ambient temperature. After forming the P channel and N + source regions, all implants are activated at 1600 °C. The gate trench is formed by inductively coupled plasma (ICP) etching with a depth of 1.2 μm. After that, gate oxide and gate electrode are formed by thermal oxidation and low-pressure CVD processes, as well as P-poly in the dummy gate. Finally, the metal layers are deposited and sintered on the surface as well as the backside to form electrodes.

4. Conclusions

In this paper, a device was introduced which merged an HJD structure and a P-pillar in a SiC trench MOSFET. The merged HJD optimised the third quadrant performance. Near the gate trench, the electric field concentration can be reduced by the L-shaped high-doped P+ region. In addition, in the drift region, the buried region provides an assistant depletion effect. The breakdown voltage, the switching property, the reverse recovery characteristic, and the on-resistance are all promoted for the proposed structure.