Wang, Q.; Zhang, D.; Zhao, Y.; Liu, C.; Hu, Q.; Liu, X.; Yang, J.; Lv, H.
A 1T2C FeCAP-Based In-Situ Bitwise X(N)OR Logic Operation with Two-Step Write-Back Circuit for Accelerating Compute-In-Memory. Micromachines 2021, 12, 385.
https://doi.org/10.3390/mi12040385
AMA Style
Wang Q, Zhang D, Zhao Y, Liu C, Hu Q, Liu X, Yang J, Lv H.
A 1T2C FeCAP-Based In-Situ Bitwise X(N)OR Logic Operation with Two-Step Write-Back Circuit for Accelerating Compute-In-Memory. Micromachines. 2021; 12(4):385.
https://doi.org/10.3390/mi12040385
Chicago/Turabian Style
Wang, Qiao, Donglin Zhang, Yulin Zhao, Chao Liu, Qiao Hu, Xuanzhi Liu, Jianguo Yang, and Hangbing Lv.
2021. "A 1T2C FeCAP-Based In-Situ Bitwise X(N)OR Logic Operation with Two-Step Write-Back Circuit for Accelerating Compute-In-Memory" Micromachines 12, no. 4: 385.
https://doi.org/10.3390/mi12040385
APA Style
Wang, Q., Zhang, D., Zhao, Y., Liu, C., Hu, Q., Liu, X., Yang, J., & Lv, H.
(2021). A 1T2C FeCAP-Based In-Situ Bitwise X(N)OR Logic Operation with Two-Step Write-Back Circuit for Accelerating Compute-In-Memory. Micromachines, 12(4), 385.
https://doi.org/10.3390/mi12040385