New Logic-In-Memory Paradigms: An Architectural and Technological Perspective
Abstract
:1. Introduction
2. State of the Art
- (A)
- Computation-near-Memory (CnM, Figure 1A): Thanks to the 3D Stacked Integrated Circuit technology (3D-SIC) [2], computation and storage are brought closer together, from which the name CnM, by stacking the two units one on top of the other. This technique has a two-fold advantage: Reducing the length of the interconnections and widening the memory bandwidth. However, this approach cannot be considered as true in-memory computing, since computation and storage are still two separate entities, but more as an evolution of conventional architectures based on the von Neumann model. Works belonging to this category are [3,4,5,6,7,8].
- (B)
- Computation-in-Memory (CiM, Figure 1B): The structure of the memory array is not modified, while its intrinsic analog functionality is exploited to perform computation. In particular, in-memory computation is achieved by reading data from the memory which is then sensed by sense amplifiers (SAs). SAs are specifically modified in order to support the computation of a few simple logic operations (AND, OR, ...). The result is then written back in the memory array. Decoders are also adapted in order to read more than one data from the array and execute row-wise (between data on different rows) or column-wise (between data on different columns) operations. Works belonging to this class are [9,10,11,12,13,14] and they all use a resistive non-volatile memory technology (RRAM). The approach followed in [15] is the same but here authors use a commodity volatile memory (DRAM, Dynamic Random Access Memory).
- (C)
- Computation-with-Memory (CwM, Figure 1C): This approach uses memory as a Content Addressable Memory (CAM) to retrieve pre-computed results by means of a Look Up Table (LUT). The working principle of this kind of computation is that any Boolean function involving two or more inputs can be encoded in a memory by storing its truth table. In particular, input combinations are stored in a LUT, while results are stored in a CAM. Then the LUT is accessed through an input combination and an address is retrieved. These addresses are used to access the CAM and obtain the final result. Works that follows this approach are [16,17,18,19,20].
- (D)
- Logic-in-Memory (LiM, Figure 1D): In this case logic is directly integrated inside the memory cell. Differently from the other three approaches, here data are computed locally without the need to move them outside the array (towards a close computing unit as in a CnM approach or towards the peripheral circuitry as in a CiM approach). Internal readings are performed in order to execute operations on data stored in different cells, by exploiting inter-cells connections. Internal writings are executed to locally save the result of the operation. There are a few works belonging to this category, such as [21,22,23,24].
3. Configurable Logic-In-Memory Architecture (CLiMA): Main Ideas
- The idea of an architecture that exploits various approaches to in-memory computing in order to adapt to different requirements and applications (Section 3);
- Configurability, hence flexibility, at different levels:
- -
- The basic block of CLiMA is a 1-bit Configurable LiM (CLiM) cell that can be programmed to perform different logic and arithmetic operations (Section 4.4);
- -
- More 1-bit CLiM cells can be grouped together to from a multi-bit CLiM cell that supports more complex operations such as bit-wise logic operations, multi-bit addition/subtraction, multiplication, shifts (Section 3 and Section 4.4);
- A data flow for Convolutional Neural Networks workload and an inter-cells connection fabric specifically optimized to minimize memory accesses outside CLiMA, to maximize data-reuse inside the CLiM array and to support high parallelism (Section 4.3, Section 4.4 and Section 4.5);
- A pNML-based design of the 1-bit and multi-bit CLiM cells and a small version of the CLiM array (Section 6).
3.1. Overview
- Type of operations (logic, arithmetic);
- Complexity of operations (e.g., a logic function with respect to division);
- Data movement.
3.2. Type of Operations and Data Movement in CLiM Array
- Intra-row computation between cells in the same row (black dashed arrow in Figure 4);
- Intra-column computation between cells in the same column (black solid arrow in Figure 4);
- Inter-row computation between two rows, an instance being an operation between a data stored in row 0 and one stored in row 1;
- Inter-column computation between two columns, an instance being an operation between a data stored in column 0 and one stored in column 1.
4. CLiMA for Quantized Convolutional Neural Networks
- CNNs are an extremely popular application nowadays because they are a powerful method for solving many complex problems such as image recognition and classification, language processing, etc.;
- CNNs are data-intensive, hence, memory accesses represent the bottleneck;
- CNNs are computational-intensive, hence, they require hardware acceleration.
4.1. Convolutional Neural Networks (CNNs)
4.2. ShiftCNN: A Quantized CNN
4.3. CNN Data Flow Mapping Scheme for CLiMA
4.4. CLiM Array Structure
4.5. Weight Dispatching Mechanism
4.6. Data Reuse Possibilities
5. Results and Discussion
- Convolutional layer parameters including input feature map dimensions (), kernel dimensions (K), stride (S) and output feature map dimensions ();
- The number of parallel non overlapping convolution windows;
- The number of execution cycles needed to complete a convolution window.
- The number of cycles to execute shift operations; in CLiMA data are shifted 1 bit at a time. Since weights are 8-bit long, in the worst case scenario eight cycles are needed to complete the operation;
- The number of cycles to execute accumulations:
- -
- One cycle for partial accumulation of data couples (Figure 13, step 3); this term does not depend on the size of the kernel because these accumulations can always be done in parallel;
- -
- cycles for partial accumulation of non-adjacent data (Figure 13, step 4); this term depends on the size of the kernel, in fact, as the convolution window dimension changes the number of non-adjacent data to accumulate changes as well;
- -
- cycles to perform final horizontal accumulations (Figure 13, steps 5 and 6); similarly to the previous term, also this one depends on the size of the kernel.
- read accesses to the input buffer to retrieve input features and weights;
- write accesses to the output buffer to store the convolution results.
6. Beyond CMOS: A pNML Implementation
6.1. pNML Basics
6.2. pNML-Based CLiM Array
7. Conclusions
- In-memory computation: Data are processed directly inside the memory, drastically reducing the need of data movement and favoring their reusing for further computation;
- Parallelism: The array is intrinsically highly parallel and perfect for accelerating compute and data intensive applications;
- Flexibility: The configurability of the cells and the possibility of exploiting inter-cells connections to build complex in-memory functions make CLiMA adaptable to different applications.
- Not all data-flows can be supported in an array-like structure because moving data from any source to any destination is not easy and would require a very complex (but flexible) network of interconnections;
- The control of data movement between cells is complex and must be managed carefully in order to avoid cells receiving/sending wrong data from/to wrong cells.
Author Contributions
Funding
Conflicts of Interest
References
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Fixed Input | S | Cout |
---|---|---|
A = 0 | B ⊕ Cin | B Cin |
A = 1 | B + Cin | |
A = 0 & B = 1 | Cin | |
A = 1 & B = 0 | Cin |
CNN Type | Architecture | Average Cycles | Texec (s) |
---|---|---|---|
AlexNet | CLiMA DL Acc. | 1711 7790 | 0.95 43.2 |
ResNet-18 | CLiMA DL Acc. | 2209 42,939 | 1.2 24 |
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Santoro, G.; Turvani, G.; Graziano, M. New Logic-In-Memory Paradigms: An Architectural and Technological Perspective. Micromachines 2019, 10, 368. https://doi.org/10.3390/mi10060368
Santoro G, Turvani G, Graziano M. New Logic-In-Memory Paradigms: An Architectural and Technological Perspective. Micromachines. 2019; 10(6):368. https://doi.org/10.3390/mi10060368
Chicago/Turabian StyleSantoro, Giulia, Giovanna Turvani, and Mariagrazia Graziano. 2019. "New Logic-In-Memory Paradigms: An Architectural and Technological Perspective" Micromachines 10, no. 6: 368. https://doi.org/10.3390/mi10060368