A Modulation Method for Three-Phase Dual-Active-Bridge Converters in Battery Charging Applications

Abstract

The Three-phase Dual-Active-Bridge (DAB3) converters are a common choice for quick charging stations for batteries in electric vehicles due to their high power density, versatility, and galvanic isolation capability. However, the DAB3 topology has limited soft-switching range, particularly under light load conditions when the voltage conversion ratio differs significantly from unity, resulting in hard switching, increased loss, and higher electromagnetic interference. To address these issues, various techniques have been proposed, but they often lead to other problems such as higher current ripple or unbalanced thermal distribution. In this paper, a new modulation scheme, called symmetric duty-cycle control (SDM), is proposed for DAB3 converters to overcome these issues. A multiaspect comparison of SDM was conducted against two existing techniques, SPS and ADCC, and its superiority was validated through simulation and experimental results. Our proposed SDM scheme provides a current ripple within 10% to 15% of the average current and enables zero current switching for the whole voltage and power ranges. Additionally, a modified version of SDM can even improve overall efficiency by 7% compared to the conventional SPS technique.

1. Introduction

The electric vehicle (EV) quick charging problem has gained increased attention in recent years with the proliferation of EVs. For one, the EVs can be refilled thanks to the charging station; for another, their large-capacity battery can help improve the stability of a weak grid (i.e., vehicle to grid or V2G interface [1,2]). This is done via the charging station that supports V2G according to some protocols (e.g., CHAdeMO, CCS/Combo) [3,4]. In order for a V2G charging station to function, bidirectional converters must be employed. Among various bidirectional converter typologies [5,6], dual active bridge (DAB) appears to be a good option owing to its various advantages [7,8,9,10], such as bidirectional power transmission, inherited soft-switching capability, and galvanic isolation [11,12]. A DAB converter is usually constructed in single-phase (DAB1) or three-phase (DAB3) forms. While DAB1 suffers from high output current ripple and is suitable for low-to-mid power range applications, DAB3 can output current ripple with a lower amplitude and a higher frequency [13,14]. Its power density is also higher, making DAB3 a good choice for high-power applications such as battery charging stations [15,16]. In this study, DAB3 was used as the designated topology for these applications.

As mentioned above, DAB3 converters have a soft-switching capability when modulated by the conventional single-phase-shift (SPS) scheme [7]. However, that capability depends strongly on the working condition. When the voltage conversion ratio is considerably different from the unity, the soft-switching area becomes narrower, and vice versa [11,17]. As a consequence, more unwanted electromagnetic interference (EMI) and power dissipation are generated. In fact, according to [18], the required voltage range at the battery side should be from 150 V to 500 V. Assuming a DC-bus input voltage of 500 V, the voltage gain ratio ranges from 0.3 to 1.0, which is remarkably large. Therefore, improving the DAB3 converters performance under the hard-switching area is a problem that needs to be solved.

From another aspect, AC impedance of a lithium-ion battery increases rapidly as the frequency of the charging current goes beyond its self-resonance frequency [19,20]. When the charging current contains ripple and if the ripple is of high amplitude and high frequency, extra heat may be generated during charging, and battery lifetime may be affected. According to Uddin et al., it is critical that high-frequency current remains small to prolong the battery life [21]. Therefore, to enhance the overall system performance, not only should soft-switching capability be improved, but the modulation strategy should have the ability to reduce the current ripple at the output side of the converters.

Unlike the DAB1 counterpart, advanced control techniques applicable for DAB1 to extend the soft-switching area, such as EPS [22,23], DPS [24], and TPS [25], cannot be straightforwardly be applied to DAB3. Some efforts dedicated for DAB3 to expand the operation range have been reported in the literature. In 2013, Hoek et.al. proposed treating the DAB3 as a DAB1 converter by controlling two phases among three in parallel [26]; however, in this configuration, the advantage of low-current ripple has to be compromised. Moreover, losses and stresses are not evenly distributed among switches and transformers.

A technique called ADCC (asymmetric duty-cycle control) was reported in [27,28] to extend the soft-switching range under a wide voltage range. In this method, duty cycles of the high side and low side switches are made to be complementary. As a result, transformer voltage and current become asymmetric. Although the soft-switching region can be extended, ADCC causes unbalanced loss distribution and unequal stress on switches that may result in difficulties in thermal management. Therefore, the thermal balancing technique needs to be applied, thus increasing the complexity of this modulation. Moreover, the output current ripple is always discontinuous when the converter is modulated with the ADCC method. Hence, when the input power increases, the output current ripple also increases significantly. Not only does this have a negative effect on the battery life, but the size of output capacitors also becomes larger. Combining the ADCC and SPS methods is also a problem because the two obtained power characteristics are not seamlessly transitable.

Another technique, DCC (duty-cycle control) was proposed in [29]. In fact, DCC is an optimized version of ADCC in which three modulation variables are obtained by minimizing the conduction loss of the converter. As reported in the paper, the soft-switching area was extended, and the converter efficiency was improved. However, the control system suffers from high computational burden in solving the nonlinear optimization problem, and although soft switching can be achieved, the output current is discontinuous, or in other words, a high-current ripple forms on the output side.

In this article, a symmetric duty-cycle control (SDM) is proposed, which is easily to implement, extends the soft-switching range, and reduces the output current ripple at the secondary inverter over a whole range of the buck region. In contrast to the multicontrol variables used in the ADCC or DCC techniques, the proposed SDM modulation uses only one variable (duty cycle). However, phase currents under the SDM technique are always made symmetrically. Therefore, the stress on all switches is automatically balanced, and the advanced thermal balancing technique is no longer required. For this reason, the SDM technique can be implemented easily. Furthermore, the phase currents are made discontinuous. Zero-current turn-on can be always achieved, and thus in theory, the soft-switching area can be extended to the whole voltage range. Additionally, as seen later in the paper, the output current ripple is small compared to that obtained with the existing methods.

However, it should be noted that in practical implementation, since the dead-time interval of the SDM method is relatively large in making the current freewheel through the body diode and attenuate completely to zero. In this interval, the power dissipation on the body diode decreases the efficiency of the converter. This is not a problem if the hardware uses the low-forward=voltage drop of the body diode, such as in the Si MOSFET, IGBT, or a type of Schottky diode connected in parallel with the switches [30,31,32]. Unfortunately, the modern silicon carbine (SiC) switches have the body diode with a high-forward-voltage drop (i.e., the CREE C2M0025120D is about 3 V). Therefore, the SDM modulation significantly decreases the system efficiency.

Beyond the work presented in [33,34], this paper provides a full close form solution for all modes, extended experimental; results, and analysis. In addition, considering the practical implementation, a modified symmetric duty-cycle control (SDMM) technique is presented to overcome the problem of diode conduction loss. The proposed SDMM aims to avoid the diode conduction period by forcing the current to flow through the source-to-drain channel of the MOSFET using the synchronous rectification mechanism. As a result, higher performance can be attained. A laboratory-scaled prototype of the converter was implemented to verify the proposed concept.

This paper is structured as follows: the detailed analysis of the proposed symmetrical SDM method is provided in Section 2; comparison analysis with several existing methods is presented in Section Section 3, and experimental results are given in Section 4 to demonstrate the proposed modulation strategy.

2. Symmetric Duty-Cycle Modulation Method

2.1. Three-Phase Dual-Active-Bridge Converters

Figure 1 shows the circuit diagram of a DAB3 converter. Conventionally, the single-phase shift (SPS) technique is used to modulate the converter. According to [11], the soft-switching area of the converter modulated by the SPS is strongly affected by the voltage conversion ratio. When it is other than the unity, the soft-switching area becomes narrower. The ds symmetric duty-cycle modulation (SDM) method is here proposed to be used where the conventional SPS method suffers from hard switching.

In the SDM method, the phase shift $\mathrm{\phi }$ is always set to zero, with only duty cycle D being manipulated. The duty cycle D is defined by $D=t_{on}{f}_s$, where $t_{on}$ is the on-time of the active switches, and $f_s$ is the switching frequency. The variation range of D is from 1/6 to 1/2. For the range of D from 0 to 1/6, there is only one phase triggered in a one-sixth period; thus, the phase current has no circuits to conduct. Based on the value of D and the voltage conversion ratio M, $M=V_1/n{V}_2$ with $V_1$ and $V_2$ are the DC terminal voltages, and there are six operation modes in total. Their boundaries in the $(D-M)$ frame are illustrated in Figure 2. Explanation of the boundaries and modes are detailed later in the paper.

The theoretical waveform of all modes is presented in Figure 3. Zero-current turn-on can be achieved for all modes from 1 to 4 as shown in Figure 3a–d because the phase current is discontinuous. In Modes 5 and 6, however, the current is continuous, and the secondary inverter suffers from hard switching as can be seen in Figure 3e,f. Therefore, these two modes are excluded from consideration. The details for the analysis of Mode 1 follow below. The same method can be applied to investigate the operation of other modes.

2.2. Steady-State Analysis of the Proposed SDM Method

It is worth making some assumptions to simplify the analysis: (i) switches are that can transit without transients are ideal; (ii) series resistances of transformers can be ignored; and (iii) input and output voltages are constant in a switching cycle. Let us consider Mode 1 for example. Current waveform and gate signals are given in Figure 3a. Phase currents are denoted as continuous, dashed and dot-dashed lines represent phases A, B, and C, respectively; shaded areas denote diode conduction intervals; rectangles with continuous edges represent gate signals of odd group switches; and those with dashed edges represent gate signals of even numbered switches. There are nine states in the first half cycle in Mode 1. The primarily referred diagrams of all states are given in Figure 4. Let t be the present time instant:

In this state, $Q_1,Q_6,Q_5$ of the primary inverter and $S_1,S_6,S_5$ of the second inverter conduct. The primary referred equivalent diagram of this state is given in Figure 4a. Phase currents in this state are as follows:

$$\mathit{i}\left(t\right)={\mathit{I}}_0+\frac{V_1}{3f_s{L}_k}\left[\begin{array}{c}1-M\\ -2+2M\\ 1-M\end{array}\right]t$$

(1)

where $\mathit{i}\left(t\right)$ is the instantaneous phase current vector, and $\mathit{i}\left(t\right)={[i_a\left(t\right),i_b\left(t\right),i_c\left(t\right)]}^T$; and ${\mathit{I}}_0$ is the transition current vector at the beginning of the switching period, ${\mathit{I}}_0={[i_{a0},i_{b0},i_{c0}]}^T$.

2.2.1. State 2: $D-1/3\le t·f_s\le D-1/3+D_{off}$

When $t·f_s=D-1/3$, $Q_5$ and $S_5$ turn off, there are no gate signals to switches of phase C in both sides. Phase C current flows through the body diode of $Q_2$ and $S_5$ to maintain its direction. Since there is no more energy supply to phase C, $i_C\left(t\right)$ attenuates after some time. Let $(D_{off}/f_s)$ be the required time for the current to attenuate to zero. The equivalent circuit of State 2 is shown in Figure 4a, and phase currents are determined by (2). This state ends when $(t·f_s)=(D-1/3+D_{off})$; then, the system proceeds to State 3.

$$\mathit{i}\left(t\right)={\mathit{I}}_1+\frac{V_1}{3f_s{L}_k}\left[\begin{array}{c}2-M\\ -1+2M\\ -1-M\end{array}\right]\left(t-\left(D+{\displaystyle \frac{1}{3}}\right){\displaystyle \frac{1}{f_s}}\right)$$

(2)

where ${\mathit{I}}_1$ is the transition current vector at the end of State 1.

2.2.2. State 3: $(D-1/3+D_{off}\le t·f_s\le 1/6)$

When $(t·f_s)=(D-1/3+D_{off})$, phase C current is zero. It then starts to oscillate between the parasitic capacitor of the transistors and the leakage inductance of the transformers causing resonance in the phase C voltage and current. This phenomenon is popular for discontinuous current mode converters and, in theory, causes no power loss but may have an EMI issue. By ignoring the resonance, the equivalent circuit can be simplified as depicted in Figure 4c, and the phase currents can be computed in the following fashion:

$$\mathit{i}\left(t\right)={\mathit{I}}_2+\frac{V_1}{3f_s{L}_k}\left[\begin{array}{c}1-M\\ -1+M\\ 0\end{array}\right]\left(t-\left(D-D_{off}+{\displaystyle \frac{1}{3}}\right){\displaystyle \frac{1}{f_s}}\right)$$

(3)

where ${\mathit{I}}_2$ is the transition current at the end of State 2.

The operations in States 4 to 6 and States 7 to 9 are similar, but the attenuating phase is B and A, respectively. Figure 4d–i show the theoretical waveform in those modes. If a similar analysis is applied, the conditions and phase currents of States 4 to 9 can be obtained. At the steady state, the current at the end of State 9, ${\mathit{I}}_9$, must be equal to that at the beginning of State 1, ${\mathit{I}}_0$. By solving ${\mathit{I}}_0$ = ${\mathit{I}}_9$, all the transition currents can be obtained. From this, the diode conduction period $D_{off}$ and the transmission power can be calculated as (4) and (5), where $P_m=V_1^2/\left(12f_s{L}_k\right)$ is as follows:

$$\begin{array}{cc}\hfill D_{off}& =\frac{1-M}{1+M}\left(D+{\displaystyle \frac{1}{6}}\right)\hfill \end{array}$$

(4)

$$\begin{array}{cc}\hfill P_1& =\frac{M{P}_m}{3}·\frac{1-M}{1+M}·{(6D+1)}^2\hfill \end{array}$$

(5)

Analogously, the output power and boundary of all modes can be obtained as listed in

Table 1. Mode boundaries and output power.

Mode 1:	$\begin{array}{cc}& {\displaystyle \frac{1}{3}}\le D\le {\displaystyle \frac{1}{6}}+{\displaystyle \frac{M}{3}}\hfill \\ & P_1={\displaystyle \frac{M{P}_m}{3}}\times {\displaystyle \frac{1-M}{1+M}}\times {\left(6D+1\right)}^2\hfill \end{array}$
Mode 2:	$\begin{array}{cc}& \left({\displaystyle \frac{1+M}{6}}\le D\right)\cup \left(D\le {\displaystyle \frac{1}{3}}\right)\cup \left(D\le {\displaystyle \frac{1+M}{3(2-M)}}\right)\hfill \\ & P_2=M{P}_m\times \left(18\times {\displaystyle \frac{2-M}{1+M}}{D}^2-1\right)\hfill \end{array}$
Mode 3:	$\begin{array}{cc}& {\displaystyle \frac{1}{6}}\le D\le {\displaystyle \frac{1+M}{6}}\hfill \\ & P_3={\displaystyle \frac{P_m}{2}}\times (1-M)\times {(6D-1)}^2\hfill \end{array}$
Mode 4:	$\begin{array}{cc}& {\displaystyle \frac{1+M}{3(2-M)}}\le D\le {\displaystyle \frac{1}{4}}+{\displaystyle \frac{M}{6}}\hfill \\ & P_4={\displaystyle \frac{M{P}_m}{6}}\times \left({\displaystyle \frac{2-M}{2+M}}{\left(12D+1\right)}^2-9\right)\hfill \end{array}$
Mode 5:	$\begin{array}{cc}& {\displaystyle \frac{1}{4}}+{\displaystyle \frac{M}{6}}\le D\le {\displaystyle \frac{1}{3}}\hfill \\ & P_5={\displaystyle \frac{M{P}_m}{6}}\times \left(7-9{(4D-1)}^2\right)\hfill \end{array}$
Mode 6:	$\begin{array}{cc}& \left(D\le {\displaystyle \frac{1}{2}}\right)\cup \left({\displaystyle \frac{1}{3}}\le D\right)\cup \left({\displaystyle \frac{1}{6}}+{\displaystyle \frac{M}{3}}\le D\right)\hfill \\ & P_6={\displaystyle \frac{M{P}_m}{3}}\times \left(4-{(6D-1)}^2\right)\hfill \end{array}$

. Figure 2 shows the product of plotting the boundaries in the $D-M$ frame. The power characteristics of Modes 1 to 4 are illustrated in Figure 5a. As can be seen, the union of the area limited by the power curves of Modes 1 to 4 perfectly covers the hard-switching zone created by the SPS method. Therefore, by hybridizing SDM Modes 1 to 4 and SPS, the whole voltage and power ranges can be fulfilled and soft switching achieved.

3. Comparison

In order to demonstrate the advantage of the proposed modulation technique, a comparison to SPS and ADCC methods was conducted which considered several aspects described below.

3.1. Soft-Switching Range

Figure 5 shows the power characteristics obtained with SPS, SDM, and ADCC. When $M\le 0.5$, SPS is not applicable and both ADCC and SDM can be applied. Figure 5b shows the soft-switching boundaries of the SPS and ADCC methods. The boundary curves cross each other, limiting a hard-switching area that cannot be covered by either SPS or ADCC as discussed and reported in [26,27]. Meanwhile, the soft-switching boundaries of the proposed SDM scheme divide the hard-switching zone of SPS into subzones that are seamlessly and perfectly fitted to each other, as shown in Figure 5a.

3.2. Power Flow with Mode Changing

Figure 6 shows the power characteristics with respect to the duty cycle D (for SDM, SDMM, and ADCC) or the normalized phase shift $D_{\mathrm{\phi }}$ (for SPS, $D_{\mathrm{\phi }}=\mathrm{\phi }/\left(2\pi \right)$, where $\mathrm{\phi }$ is the phase shift) at some given voltage conversion ratios. Although the power curves obtained with SDM are divided into subsections due to the presence of submodes, the sections are relatively linear and exhibit monotonic increasing. Moreover, the maximum power reached by SDM is suits the minimum covered with SPS. Combining SPS and SDM allows for the continuous power characterization the converter. The power characteristics of the ADCC method are, however, relatively nonlinear and nonmonotonic. For a given voltage conversion ratio, there is a gap between the power generated with ADCC and SPS, as shown in Figure 6. This may make mode selection and shifting from ADCC to SPS (and vice versa) complicated.

3.3. Output Current Ripple

As mentioned above, the current ripple is critical for battery charging applications. Therefore, it is worth considering the output current ripple generated by the modulation techniques. Figure 7 demonstrates the root-mean-square (RMS) output ripple current (or capacitor current) of the aforementioned methods. At any given power transmission, the current ripple generated by ADCC is higher than that caused by the proposed SDM. The current ripple obtained by SDM ranges from 10 to 15% of the $I_m$, where $I_m=V_1/\left(18f_s{L}_k\right)$. Particularly, when $M=0.5$, the current ripple is eliminated under SDM at half of $P_m$. When $M>0.5$, $\Delta I_{out,rms}$ of ADCC is even much greater than that of the conventional SPS method.

4. Diode Loss Elimination Technique

4.1. Proposed SDMM Technique

As analyzed above, in State 8 of Mode 1, the phase A current attenuates to zero through the body diode of $Q_4$ and $S_1$, causing conduction loss. For switching devices with a high-voltage drop on the body diode (such as C2M0025120D from Woldspeed), loss caused by diode conduction might be significant and affect the overall converter performance.

The diode loss can, however, be eliminated by making the current flow through the source-drain channel of the FET. By using (4), the diode conduction interval can be estimated. During $\left(D_{off}/f_s\right)$ interval, the corresponding FET is forced ON for the current to flow. Hence, the loss on the switch is now proportional to its ON resistance instead of the forward voltage on the diode. By using low ON-resistance devices or connecting them in parallel, the conduction loss can be reduced. This technique is named modified SDM or SDMM.

Figure 8 shows the typical gate signal of phase A switches. In the original SDM, after the duty cycle D, both $Q_1$ and $S_1$ are OFF, and the current starts its freewheeling. Here, in the SDMM method, $S_1$ remains ON in an extra duty cycle of $D_{off}$. In the meantime, $Q_4$ is forced ON to conduct the freewheeling current. A small dead time is added between the transition of $Q_1$ and $Q_4$ to avoid a shoot-through. Zero-voltage turn-on is thus achieved for $Q_4$. After $(D_{off}/f_s)$ seconds, the phase A current reaches zero, and then both $Q_4$ and $S_1$ are OFF. Hence, zero-current turn-off is obtained for $Q_4$ and $S_1$. Note that SDMM does not introduce new switching states; therefore, all the above analyses remain valid.

This idea is motivated by the synchronous rectification technique which is commonly used in LLC converters. However, in the SDMM method, modulation patterns of both sides are modified, making it relatively complicated to implement because primary switches transit twice in a switching cycle. Additionally, $D_{off}$ determined by (4) is highly nonlinear and system state-dependent ($D_{off}$ depends on M).

The above presents the implementation of SDMM using a software approach; that is, the modulation pattern is created by computing the conduction period manually with mathematics equations obtained from theoretical analysis. To be feasible, this approach requires certain conditions:

i

Precise determination of the present voltage gain M. The DC terminal voltages are sensed and from this, the voltage gain ratio M is calculated. A mismatch in determining M may lead to early or late turn-off of the corresponding switch that may reduce the effect of the proposed method.

ii

A high-resolution pulse-width modulation (PWM) module of the microcontroller. For instance, in this study, an STM32G474RE microcontroller from STMicroelectronics was used to generate the SDMM modulation pattern.

iii

Finally, the microcontroller with a floating-point unit (FPU). This is needed because the calculation of the diode conduction interval consists of some division and multiplication operations.

If the above conditions cannot be met, hardware implementation can be considered. For example, a special gate driver design which allows automatic generation of a synchronous rectification signal based on the sensing current can be used. This problem is, however, beyond the scope of this paper. It will be readdressed in future publications.

4.2. Loss Breakdown Analysis

This loss breakdown analysis employs the loss models presented in [35] by the same author, specifically, power dissipation, including the power electronic loss (conduction and switching losses) and transformer loss (core and copper losses). The conduction loss is easy to determine with the RMS phase current. These current equations can be found in [35,36]. The switching loss is calculated by using the rising and falling time in the datasheet, i.e., CREE C2M0025120D SiC MOSFET for both sides of inverter systems. The core loss of transformer is estimated by using the Steinmetz equation [37], and the winding loss is estimated for the Lizt wire, with considerations given to the skin and proximity effects. From this, the loss models of the SDM, SDMM, SPS, and ADCC were determined and compared.

Figure 9 shows the loss distribution under three case studies: (1) M = 0.8 & P = 0.34 p.u; (2), M = 0.7 & P = 0.21 p.u; and (3), M = 0.6 & P = 0.15 p.u. Note that all the power here is expressed per unit with respect to $P_m$, $P_m=V_1^2/\left(12f_s{L}_k\right)$. In the first case study, power is transferred at a high-voltage conversion ratio. The calculated efficiencies in this case are 96.27%, 94.99%, 93.64%, and 92.93% for SPS, SDMM, SDM, and ADCC, respectively. As shown in Figure 5, the point $M=0.8$ and $P=0.34$ p.u. are located in the hard-switching area of SPS, whereas, in the SDM and ADCC regions, the point belongs to SDM-Mode 1 and ADCC-TRAP, respectively. Despite this, SPS appears to be the most efficient modulation scheme, as the generated loss is the lowest compared to that caused by the other techniques. This is because even if hard switching occurs under SPS modulation, the extra turn-on loss is still much lower than the turn-off loss generated by SDM (and SDMM) and ADCC, for which phase current is discontinuous (i.e., turn off loss is considerably increased). While the transformer loss is comparable for all schemes, switching loss and, in particular, the conduction loss generated by ADCC, is more than that generate by SPS, SDM, and SDMM. However, in term soft diode loss, SDM is the worst, while the others cause no diode loss.

In the second case study, the calculated efficiencies are 93.79%, 94.35%, 92.02%, and 89.38% for SPS, SDMM, SDM, and ADCC, respectively. Figure 5 shows that points $M=0.7$ and $P=0.21$ p.u. belong to either SPS hard switching, SDM-Mode 2, or DCC-Trap mode. In this condition, SDMM appears to be superior to ADCC. Switching loss obtained with ADCC is remarkably high while that obtained with SDM (and SDMM) is much lower. As SPS goes further into the hard-switching zone, the generated switching loss is now higher even though it is still less than that obtained with SDM and SDMM for the same reason mentioned in the previous case study.

In the last case study, where $M=0.6$ and $P=0.15$ p.u., the working regions observed in Figure 5 are SPS hard switching, SDM-Mode 2, and ADCC-TRI-Buck. The computed efficiencies are 88.41%, 93.66%, 89.99%, and 95.56% for SPS, SDMM, SDM, and ADCC, respectively. Under this condition, ADCC, however, is the best choice in terms of converter efficiency. Both the conduction and switching losses caused by ADCC are the lowest. SDMM appears to be second best in terms of efficiency. Although it generates a comparable conduction loss as that of ADCC, SDMM results in an almost doubling of switching loss. SPS operates deeply inside the hard-switching zone with remarkably high conduction loss, making it the worst in terms of converter efficiency.

From the above evaluation, it can be concluded that the performance of the modulation schemes depends highly on working conditions. ADCC is good at light load where TRI-Buck mode is employed, but it performs less well when the power is higher, and then TRAP-Mode must be used. SPS is superior when near its boundary, but away from this, its performance declines rapidly. SDMM shows the best performance at the light-to-mid power range and has a particularly stable efficiency, ranging from 93.66% to 94.99% in all investigated cases.

5. Experimental Results

An experimental system was built to evaluate all the modulation methods. The key parameters are listed in

Table 2. The key parameters of the DAB3 converter.

Parameters	Symbol	Value
Input voltage	$V_1$	100 V
Output voltage	$V_2$	60–100 V
Scale down power	$P_{in}$	2 kW
Frequency	$f_s$	50 kHz
Turn ratio	n	1
Leakage inductance	$L_k$	12.5 $\mathsf{\mu }$H
Wire		Lizt 1650AWG38
Core		EE42/21/15 (N87)
SiC MOSFET		CREE C2M0025120D

. The DC-bus voltage at the input side was connected to a programmable power supply (MR50040 from BK Precision), whereas the output was linked to an electronic load (62120D from Chroma) configured in the constant-voltage mode. Due to the limitation of experimental equipment, scaled down experiments with specification of $V_1$ = 100 V, and $V_2$ = 60 to 100 V were conducted. SiC MOSFETs of C2M00025120D from CREE was used for both inverters. The three-phase transformer was constructed with three single-phase transformers. The equivalent leakage inductance seen from the inverter was thus about 4.16 $\mathsf{\mu }$H. An STMicroelectronics NUCLEO-STM32G474RE board was used to generate the switching pattern of all modulation techniques. In the experiments, the input voltage was always fixed at 100 V (i.e., $P_m=V_1^2/\left(12f_s{L}_k\right)=4000$ W), whereas, the output voltage was changed to test the modulation methods at various conversion ratios. Duty cycles and phase shift were set manually for open-loop tests. An image of the system is illustrated in Figure 10.

Figure 11 shows the measured voltage and current of the ADCC and SDM methods with $M=0.8$. The measured waveform of ADCC TRI Buck, SDM Mode 2, and SDMM Mode 2 when transmitting 500 W (P = 0.125 p.u.) are depicted in Figure 11a,c, and e, respectively. In all cases, ZCT was achieved. However, while the drain-source voltage obtained with the ADCC method was clear with low ringings, that obtained with SDM and SDMM contained ringings with a frequency of about 1 MHz due to the resonance between leakage inductances and parasitic capacitors of the FETs. Although the ringings occurred at zero current, causing no loss, they contributed to a louder noise emitted by the converter.

The current waveform shown in Figure 11c,e is symmetrical with a clear zero interval that ensures ZCT of the switches. The zero-current interval observed in Figure 11a, however, appears to have a small bias. This might be due to the magnetizing current, parasitic elements, and dead time [36]. Moreover, since the duty-cycle value used in the ADCC method is highly dependent on the voltage ratio M, a small mismatch on its determination may lead to the hard switching of the transistors modulated by ADCC. Nevertheless, ADCC-TRI-Buck performs better than do both SDM and SDMM at a light load, as shown in Figure 12b. At 500 W, the overall system efficiency obtained with ADCC is mostly 97.2%, whereas that with SDM is 95.4%. The diode conduction loss is responsible for the inferior performance of SDM against ADCC.

The current waveform obtained with SDMM was the same as that obtained with SDM, as shown in Figure 11c,e. The additional pulse of the gate signal helps eliminate the diode conduction interval. As a result, the efficiency obtained with SDMM improves to about 96.7% at 500 W operation. Nonetheless, it is 0.5% less than that obtained with ADCC. The reason for this is that SDMM requires the switches to transit nine times in a half cycle (corresponding to nine switching states) compared to only six of the ADCC method. Therefore, at a low-power range, the lower switching loss of ADCC makes it slightly better than SDMM. This result confirms the conclusion of the loss breakdown analysis of case study 3 in the previous section.

Figure 11b,d,f show the measured waveform obtained with ADCC TRAP, SDM Mode 1, and SDMM Mode 1, respectively, at $M=0.8$ and 1.2 kW (i.e., 0.3 p.u.). This experiment was conducted to confirm the conclusion of case study 1 and 2 in the previous section. Analogous observations to those of the previous experiment were obtained. Ringings were still present in the drain-source voltage obtained with SDM and SDMM; however, its amplitude was smaller. At this power, conduction loss is dominant. As shown in Figure 12, at 1200 W, the overall system efficiency recorded with ADCC, SDM, SDMM, and SPS are 94.6%, 94.3%, 95.7%, and 95.4%, respectively. SDMM appears to be superior over the other methods. As the power increases, the performance of ADCC reduces dramatically, whereas SDMM can maintain the efficiency around 95.7%. Therefore, it can be concluded that at a high power range, SDMM outperforms ADCC in term of system efficiency.

Figure 12a–c show the system efficiencies at $M=0.6$, $M=0.8$, and $M=0.9$, respectively. Observation from the figures reinforces the conclusions from the loss breakdown analysis. When $M=0.6$, ADCC-TRI-Buck is superior under 800 W (i.e., 0.2 p.u.; this is also the upper boundary of ADCC-TRI-Buck mode) power transmission as predicted in case study 3 in Section 4.2. Efficiency declines rapidly when the power increases and the converter enters ADCC-TRAP mode. With SPS, since the system operates in the hard-switching zone, efficiency is remarkably low. When the converter enters the vicinity of the SPS soft-switching area (>1800 W), the converter is most benefited by SPS as observed in case study 1 of the previous section. Because of the diode loss, SDM appears to be the worst in most cases. However, owing to the elimination of the diode conduction interval, SDMM is shown to be the best in terms of efficiency when the power is greater than 800 W.

When $M=0.8$, the above observation is still true. ADCC is still the best under the light-load condition with ADCC-TRI-Buck ($P<700$ W or 0.175 p.u.—the upper boundary of the TRI-Buck mode) as shown in Figure 12b. However, the performance declines rapidly in the ADCC-TRAP mode when the power increases. SPS is still superior in its soft-switching area ($P>1400$ W or 0.35 p.u.). In the mid-power range, SDMM appears to be the best. Interestingly, SDMM can maintain a quite stable performance throughout the power range with an average efficiency of about 96%. The same conclusion can also be drawn from the experiment results shown in Figure 12c when $M=0.9$. In all cases, combining SDMM and SPS helps to cover the whole power range with high efficiency. The efficiency profile of the combined SPS-SDMM method is highlighted in yellow in Figure 12.

Figure 13 shows a current ripple comparison between ADCC and SDM. The ripple is measured at the output of the secondary bridge before the filter capacitors. Lower current ripple means lower loss on output caps and cleaner output current to the battery. As can be seen, SDM (and thus SDMM) provides better ripple characteristics. In the SDM method, although the phase current is discontinuous (Figure 3), except for Mode 3, the output current in all other modes is continuous with a low ripple. The current ripple obtained with SDM is always around 10% to 15% in all investigated cases, which is consistent with theoretical analysis shown in Figure 7. In contrast, the current ripple obtained with ADCC is always higher than that obtained with SDM. For instance, at 1200 W power transmission, the measured current ripple with ADCC is almost 60%, which is nearly six times higher than that obtained with the proposed SDM method.

Figure 14 summarizes the comparison across several areas. The larger area implies a better performance. In terms of current ripple, soft-switching, and power ranges, SDM (and thus SDMM) proved to be the best, as it generated the lowest current ripple. The combination of SPS and SDM can cover the whole power and soft-switching ranges. SDM and SPS methods occupy only one modulation variable; therefore, they are ranked highest in terms of robustness and feasibility. SDMM and ADCC, however, depend on the voltage conversion ratio to compute modulation parameters; therefore, they are less robust than are the other two methods. Compared to the other techniques, SDMM uses the most complicated modulation pattern; hence, it ranks the lowest in terms of feasibility. Efficiency is the weakest point of SDM due to the diode conduction loss. As SDMM can overcome this weakness, despite its inferior performance compared to ADCC under the light load, its performance is better under the heavy-load condition; thus, it is ranked the same as ADCC. To conclude, SDM has the largest area implying the best performance. SDMM ranks second overall, with the advantage of efficiency over SDM at the cost of feasibility and robustness.

6. Conclusions

This paper proposes a new modulation method, SDM, as well as its improved version, to be applied for three-phase DAB converters. The performance of the proposed method was compared to other well-known methods, both in theoretical analysis and experiments. Results confirmed that SDM can extend the soft-switching area of DAB3 converters. In particular, a combination of SDM and SPS can cover the whole voltage and power range for the cases in which the voltage conversion ratio is less than the unity. Phase currents are symmetrical; thus, loss can be evenly distributed among switches and transformer winding. Furthermore, SDM can help reduce the output current ripple (up to six times less than that of the ADCC method), which is essential for battery charging applications. However, the original SDM is inferior due to the presence of the diode conduction period. The SDMM method was thus proposed to solve this problem by modifying the switching pattern. Under this modified method, the converter efficiency could be improved up to 7%, and the SDMM technique was found to be the superior choice at the midrange of power for improving the converter efficiency. Therefore, a hybridization of SPS and SDMM is the best modulation method for overcoming most of the weaknesses of the other modulation techniques.