Design and Implementation of a High Step-Up DC-DC Converter Based on the Conventional Boost and Buck-Boost Converters with High Value of the Efficiency Suitable for Renewable Application

Abstract

This paper introduces a novel topology of the proposed converter that has these merits: (i) the topology of the converter is based on conventional boost and buck-boost converters, which has caused its simplicity; (ii) the voltage gain of the converter has provided higher values by the lower value of the duty cycle; (iii) due to the use of high-efficiency conventional topologies in its structure, the efficiency of the converter keeps its high value for a great interval of duty cycle; (iv) besides the increase of the voltage gain, the current/voltage stresses of the semiconductors have been kept low; (v) the continuous input current of this converter reduces the current stress of the capacitor in the input filter. It is worth noting that the proposed converter has been discussed in both ideal and non-ideal modes. Moreover, the operation of the converter has been discussed in both continuous/discontinuous current modes. The advantages of the converter have been compared with recently suggested converters. In addition, the different features of the converter have been discussed for different conditions. In the small-signal analysis, the appropriate compensator has been designed. Finally, the simulation and experimental results have been reported for 90 W output power, 90 V output voltage, 3-times voltage gain, and 100 kHz switching frequency.

1. Introduction

Renewable applications require a high efficiency, high gain, and low volume converter. The buck-boost and boost converters are conventional converters that are capable of increasing their input voltage [1]. These converters are appropriate for high-efficiency applications. In addition, the simplicity of their topology has caused their popularity as well as their efficiency. To provide high values of the voltage gain, the duty cycle’s percentage has to approach 100 percent. However, such a high value of the duty cycle results in a dramatic switch loss besides the high value of the semiconductors’ current/voltage stresses [2,3,4]. Moreover, the resulted voltage gain is not the same as the prediction of their voltage gain equation. According to Figure 1a, an increase in the duty cycle can not always increase the voltage gain. Moreover, the very close value of the duty cycle to unity results in a decreasing behavior of the voltage gain. Furthermore, the output power is the other effective factor. Based on Figure 1b,c, the increase of the output power besides a constant voltage decreases the maximum voltage gain. Moreover, an increase in the output power decreases the corresponding interval of rising behavior of the voltage gain. The high duty cycle has a destroying effect on efficiency. As has been presented in Figure 1d, the high value of the duty cycle provides poor values of efficiency. Consequently, providing a high value of the voltage gain by the low value of the duty cycle is not possible [5,6,7,8].

Employing high-frequency transformers can be a solution to increase the voltage gain [9]. In other words, the turn ratio of coils can be step-up isolated from the input source. Therefore, the load is isolated from the input source. Therefore, the load will be protected from happening faults on the input side [10]. However, the switches of this kind of converter suffer from high current stresses due to the current inertia of the leakage inductance [11]. Such a shortage can be solved by applying snubber circuits which increase the number of elements [12]. The shortage of transformer base converters does not stop here and EMI is another one. Furthermore, the high volume, mass, and cost of this kind of converter is another disadvantage [13]. Consequently, the use of this kind of converter is not recommended for applications that do not require the isolation of the load from the input source. Switch-capacitor topologies are the solution for increasing the voltage gain [14]. In this kind of converters, switching of switches copies the voltage in parallel connected capacitors and then, the series connection of capacitors results in a high output voltage. However, the parallel switching of capacitors causes inrush currents that the semiconductors suffer from the resulted current stress [8,11,12,14].

The quadratic DC-DC converters are another solution to increase the voltage gain. These topologies can be easily made by cascading or restructuring conventional converters. In [15,16,17,18,19,20,21,22,23,24,25,26], recently suggested quadratic DC-DC converters have been reported. The reported converters of [15,16,17,18,19,20,21,22,23,24,25,26] can be divided into three groups based on the equation of their voltage gain. The voltage gain of [15,16,17,18,19,20,21] is 1, while the percentage of the duty cycle becomes 50 percent. Moreover, the output voltage is twice the input source in [22,23,24,25]. Furthermore, a 50 percent duty cycle increases the input voltage to three times more than itself. The quadratic buck-boost converter of [15] has used three inductors. In other words, its dimension has been increased. Moreover, besides the high number of the inductors and low value of the resulted voltage gain, the conduction loss of the inductors has a high value. Moreover, the corresponding losses of the switches and diodes are high as well as the voltage stress of the semiconductors is dramatically high. The proposed converter in [16] has been made up of a simple cascaded two buck-boost converter. In comparison with [15], it has two inductors. Unlike the presented converter in [15] the input current is discontinuous. The voltage stress of the second switch and diode is higher than the resulted voltage level of the output. Moreover, the switch and diode losses have become high. The suggested topology in [17] has achieved a continuous input/output current. However, the semiconductors suffer from high voltage/current stresses. Moreover, the use of three inductors has increased its volume. Furthermore, the different kinds of losses are high and undesired. Same as the topology of [17], the represented topology in [18] has continuous input/output currents. The topology of this converter has employed PNP and NPN MOSFETs. Such different kinds of switches result in different driving circuits. Moreover, its volume has been increased due to its three inductors. Furthermore, the corresponding loss of the inductors has been increased. Additionally, the second switch and diode of this converter suffer from high voltage stress. The reported topology in [19] is a simple cascade of two buck-boost converters. The same as the converters of [16,18], PNP and NPN MOSFETs have been used in this topology. It is worth noting that, due to the use of buck-boost converters in its topology, the input current is discontinuous. Additionally, the second switch and diode experience a voltage higher than the output voltage of the converter. In comparison with [16], the corresponding loss of the inductors is high. Other combinations of the buck-boost converter have been reported in [20,21]. It is worth noting that the combination of the conventional converters has been done in a way that has caused the continuity of the input current. It is good to mention that two different driver circuits have to be used in the suggested converters of [20,21] due to the use of PNP and NPN MOSFETs together. The proposed topology in [21] has a lower inductor/switch loss in comparison with [20]. Additionally, the semiconductor in these two topologies suffers from high voltage stress. Another type of quadratic converter with continuous input current has been reported in [22]. It is worth noting that the topology of this converter is in a way that causes high voltage stress on the switches. Moreover, the corresponding losses of the switches and diodes have become increased. Furthermore, the first switch suffers from high current stress. The reported topology in [23] has the same number of components as in [22]. In addition, three inductors have made it high-measured. Moreover, the voltage stress of the second switch and diode has been increased dramatically. The suggested topology in [24,25,26] has the same component count. Most of the semiconductors in these topologies suffer from high current/voltage stress. Besides the low inductor and switch losses in [25,26], their diode loss is high. It is good to mention that all types of losses in [24] are not desired.

The quadratic converters increase the degree of the relation of the voltage gain from one to two. Consequently, the provided voltage gain by the conventional converters becomes squared. However, such a modified form increases the degree of the relation of the average current of the inductors. As a result, the decrease of efficiency concerning the increase of the duty cycle takes place rapidly. In other words, the efficiency loses its high value in the shorter interval of the duty cycle. According to Figure 1d, the efficiency of the conventional converters remains more than 90 percent while the duty cycle varies from 0 to 80 percent. However, this interval of the duty cycle gets shorter. Therefore, the conventional topologies with high efficiency have to be combined with themselves besides the increase of the voltage gain and without the increase of the loss intensity. In this paper, the conventional boost and buck-boost converters are combined so that their output voltages are summed with each other. Consequently, the voltage gain has been increased without any difference in the losses of each circuit component. Additionally, the proposed converter is capable of providing a higher value of efficiency for a wide span of the duty cycle. This concept states the better functioning of this converter in comparison with the suggested converters of [15,16,17,18,19,20,21,22,23,24,25,26]. It is worth noting that the detailed expressions have been reported in the fourth and fifth sections. Due to the use of the conventional topologies in the presented converter, its simplicity is a brilliant feature. The higher value of the voltage gain besides the high efficiency, low voltage/current stress of the semiconductors, and use of a low value of the duty cycle is a remarkable point in comparison with [15,16,17,18,19,20,21,22,23,24,25,26] which has been deeply explained in the fourth and fifth sections. The detailed expression of the converter and its operation parameters have been discussed in the second section. In the third section, the operation of the converter in the discontinuous current mode (DCM) has been explained. The appropriate voltage gain of the converter in the non-ideal mode of the circuit components has been extracted and compared with the recently suggested converters of [15,16,17,18,19,20,21,22,23,24,25,26] in the fourth section and the better behavior of the converter for a longer interval of the duty cycle has been discussed. The fifth section is devoted to the discussion of efficiency. Different parameters such as current/voltage stress of the semiconductors, different kinds of losses, topological features, and storage energy of the converters have been compared and remarkable points of the proposed topology have been discussed in the sixth section. The small-signal analysis has been done in the seventh section. Finally, the simulation and experimental results have been extracted and discussed in the eighth section.

2. Proposed Converter

The topology of the proposed converter has been presented in Figure 2a. According to Figure 2b, the conventional boost and buck-boost converters have composed the topology. The same semiconductor-based components are activated and inactivated synchronously. It is worth noting that, during the activation of the switches, the diodes are OFF. To discuss this converter in this section, some assumptions have to be considered as follows:

• The operation of the converter takes place in the continuous conduction mode (CCM).
• All the circuit components are ideal and their parasitic components are neglected.
• The capacitors are large enough to keep their voltage constant.

The first operation mode of the converter is started by activation of both switches. According to Figure 2c, the diodes are in their reverse biased. It is worth noting the inductors are magnetized due to their positive voltage as well as the capacitors are discharged due to their negative current. The inactivation of switches and the activation of the diodes start the second operation mode. The equivalent circuit of the converter in this mode has been illustrated in Figure 2d. The inductors’ voltage and capacitors’ current during both operation modes are (1):

$$\left\{\begin{array}{c}{L}_1{\displaystyle \frac{d{i}_{L1}}{dt}}=D{v}_{in}+(1-D)(v_{in}-v_{c_1})\hfill \\ L_2{\displaystyle \frac{d{i}_{L2}}{dt}}=D{v}_{in}+(1-D)(-v_{c_2})\hfill \\ C_1{\displaystyle \frac{d{v}_{c1}}{dt}}=-D\left({\displaystyle \frac{V_o}{R}}\right)+(1-D)(i_{L_1}-{\displaystyle \frac{V_o}{R}})\hfill \\ C_2{\displaystyle \frac{d{v}_{c2}}{dt}}=-D\left({\displaystyle \frac{V_o}{R}}\right)+(1-D)(i_{L_2}-{\displaystyle \frac{V_o}{R}})\hfill \end{array}\right.$$

(1)

According to the voltage second balance, the inductors’ average voltage is zero as well as the current second balance concludes the zero average currents of capacitors. Therefore, based on Equation (1), the average voltage of the capacitors and average current of inductors can be expressed as (2):

$$\left\{\begin{array}{c}{V}_{C1}={\displaystyle \frac{V_{in}}{1-D}},V_{C2}={\displaystyle \frac{V_{in}D}{1-D}},V_{Co}={\displaystyle \frac{1+D}{1-D}}{V}_{in}\hfill \\ I_{L_1}=I_{L_2}={\displaystyle \frac{1}{1-D}}{\displaystyle \frac{V_o}{R}},I_{in}={\displaystyle \frac{1+D}{1-D}}{\displaystyle \frac{V_o}{R}}\hfill \end{array}\right.$$

(2)

The voltage stress of the semiconductors can be expressed according to their inactivation mode as well as their current stress can be expressed according to their activation mode as (3):

$$\left\{\begin{array}{c}{V}_{S_1}=V_{S_2}=V_{D_1}=V_{D_2}={\displaystyle \frac{V_{in}}{1-D}}\hfill \\ I_{S_1}=I_{S_2}={\displaystyle \frac{D}{1-D}}{\displaystyle \frac{V_o}{R}},I_{D_1}=I_{D_2}={\displaystyle \frac{V_o}{R}}\hfill \end{array}\right.$$

(3)

The simplified relation of the inductors’ current ripple can be expressed according to their applied voltage during the operation modes. Moreover, the simplified relation of the capacitors’ voltage ripple can be expressed according to the crossing currents through them as (4):

$$\Delta i_{L_1}=\Delta i_{L_2}={\displaystyle \frac{D{V}_{in}}{L_{1,2}{f}_s}},\Delta v_{c_1}=\Delta v_{c_2}={\displaystyle \frac{D{I}_o}{C_{1,2}{f}_s}}$$

(4)

3. DCM Mode

In the second section, the extracted relation of voltage gain has been expressed for the continuous current mode. Another time interval exists when both the switches and diodes are inactive in the discontinuous current mode. The duty cycle represents the ratio of the ON-time over the entire period and is denoted by D. Moreover, the ratio of the time interval of ON mode of diodes over the whole period has been illustrated by $D_1$. The time interval of the OFF mode of all semiconductors over the whole period has been illustrated by $D_2$. The relation of D, $D_1$, and $D_2$ is as below:

$$D+D_1+D_2=1$$

(5)

Based on the mentioned concepts, the voltage gain of the proposed converter in DCM, has been expressed as below:

$${\displaystyle \frac{V_o}{V_{in}}}={\displaystyle \frac{2D+D_1}{D_1}}$$

(6)

The operation of the converter in DCM or CCM depends on the value of the inductors and their average currents. To ensure the proper operation of the proposed converter in CCM, the boundary value of the inductors has been expressed as (7):

$$L_1>{\displaystyle \frac{RD(1-D)}{2f_s(1+D)}},L_2>{\displaystyle \frac{RD(1-D)}{2f_s(1+D)}}$$

(7)

According to Figure 3a,b, the operation of the converter in CCM or DCM regions has been presented based on the value of the output current and duty cycle. It is worth noting that Figure 3a has been extracted for a constant output voltage as well as Figure 3b has been extracted for a constant input voltage.

4. Non-Ideal Voltage Gain

The Relation of the Non-Ideal Voltage Gain

In the second section, the ideal mode of the circuit components has been assumed and the voltage gain was extracted. To explain the real behavior of the proposed converter with the mathematical relations, the series resistance of the inductors, and switches besides the voltage drop of the diodes have been considered and the non-ideal voltage gain has been extracted as below:

$$\left\{\begin{array}{c}CCM:{\displaystyle \frac{V_o}{V_{in}}}={\displaystyle \frac{1+D}{1-D}}\left(1-{\displaystyle \frac{r_L}{R}}{\displaystyle \frac{2}{{(1-D)}^2}}-{\displaystyle \frac{r_{DS}}{R}}{\displaystyle \frac{2D}{{(1-D)}^2}}-{\displaystyle \frac{r_D}{R}}{\displaystyle \frac{2}{1-D}}\right)\hfill \\ DCM:{\displaystyle \frac{V_o}{V_{in}}}={\displaystyle \frac{D_1+2D}{D_1}}\left(1-{\displaystyle \frac{r_L}{R}}\left(2{\left({\displaystyle \frac{D_1+D}{D_1}}\right)}^2\right)-{\displaystyle \frac{r_s}{R}}\left({\displaystyle \frac{2D(D+D_1)}{D_1^2}}\right)-{\displaystyle \frac{r_D}{R}}\left({\displaystyle \frac{2(D_1+D)}{D_1}}\right)\right)\hfill \end{array}\right.$$

(8)

where the $r_L$, $r_{SD}$, and $r_D$ refer to equivalent series resistance of the inductors, equivalent series resistance of the switches, and voltage drop of the diodes respectively.

According to Equation (8), the voltage gain of the converter in both ideal and non-ideal modes has been compared in Figure 4a. It is worth noting that the ideal and non-ideal voltage gains behave as same as each other, while the duty cycle varies from 0 to 80 percent. Moreover, the maximum voltage gain has occurred at the 93 percent duty cycle. It is worth noting that the behavior of the voltage gain in the non-ideal mode of components depends on the quality of the circuit elements and output power. According to Figure 4b, the increase of the output power besides a constant output voltage decreases the maximum value of the voltage gain as well as its corresponding duty cycle. In Figure 4c, the behavior of the voltage gain has been presented varying both duty cycle and output power. It can be understood that the resulted voltage gain is the same at lower values of the duty cycle for all output power values. In addition, increasing the duty cycle to higher values causes more differences in the corresponding voltage gain of various output powers.

In Figure 4d, the voltage gain of the proposed converter and [15,16,17,18,19,20,21,22,23,24,25,26] have been compared in their non-ideal mode. While the duty cycle varies from 0 to 50 percent, the voltage gain of the proposed topology provides higher values in comparison with [15,16,17,18,19,20,21,22,23,24,25,26]. In addition, while the duty cycle varies from 50 to 60 percent, the voltage gain of the suggested converter is higher than [15,16,17,18,19,20,21,22,23,24,25]. Moreover, the increase of the duty cycle from 60 to 7 percent, makes the voltage gain of this converter higher than [15,16,17,18,19,20,21]. It is worth noting that, while the duty cycle varies from 70 percent to 85 percent, the maximum value of the voltage gain takes place for all converters of [15,16,17,18,19,20,21,22,23,24,25,26]. Unlike the converters of [15,16,17,18,19,20,21,22,23,24,25,26], the voltage gain of the converter keeps its rising behavior until the percentage of the duty cycle becomes 93 percent.

5. Efficiency

5.1. Mathematical Relations of the Efficiency

To define the efficiency of the proposed converter, the inductor loss, the switch loss, and the diode loss have been expressed, and magnetic and eddy current loss of inductors have been ignored. In the expressed relations of the power losses, $r_L$, $r_{SD}$, $v_{DF}$, $t_{off}$, R, and $P_o$ refer to the resistance of the inductor, the dynamic resistance of the switch, the threshold voltage of the diodes, the turn OFF delay time, load, and the output power, respectively.

The inductor loss of the proposed converter has been expressed as below:

$$P_L=\sum _{n=1}^2{r}_{L_n}{I^2}_{rm{s}_n}=\left({\displaystyle \frac{r_{L_1}+r_{L_2}}{{(1-D)}^2}}\right){\displaystyle \frac{P_o}{R}}$$

(9)

The conduction loss of the switches can be expressed as below:

$$P_{SC}=\sum _{n=1}^2{r}_{{DS}_n}{I^2}_{Sn,rms}=\left({\displaystyle \frac{(r_{DS1}+r_{DS2})D}{{(1-D)}^2}}\right){\displaystyle \frac{P_o}{R}}$$

(10)

The switching loss of the switches has been expressed as below:

$$P_{SS}=\sum _{n=1}^2{\displaystyle \frac{1}{2}}{I}_{S_n}{V}_{S_n}{t}_{offn}{f}_s={\displaystyle \frac{D{P}_o{f}_s(t_{off1}+t_{off2})}{2{(1-D)}^2}}$$

(11)

The diode loss of the proposed converter has been written as below:

$$P_D=\sum _{n=1}^2{V}_{DFn}{I}_{Dn}=(V_{DF1}+V_{DF2})I_o$$

(12)

The efficiency of the proposed converter can be expressed as below:

$${\displaystyle \frac{P_o}{P_o+P_L+P_D+P_{SC}+P_{SS}}}$$

(13)

According to the expressed equations of losses and efficiency, the quality of the circuit components and output power affect the efficiency value. In Figure 5a,b, the efficiency of the converter has been extracted for the different output powers. According to Figure 5a, the efficiency of the converter is higher than 97.5 percent for 30 W to 180 W output power and the duty cycle varies from 0 to 50 percent. In addition, according to Figure 5b, the efficiency is more than 95 percent while the duty cycle varies from 50 to 70 percent as well as the output power varies from 30 W to 180 W. Moreover, the efficiency of the converter remains more than 90 percent for all the mentioned output powers while the duty cycle is lower than 80 percent. Furthermore, the increase of the duty cycle from 80 percent to 85 percent makes the corresponding efficiency of 120 W to 180 W output power lower than 90 percent. It is worth mentioning that the 3-dimensional figure of the efficiency has been plotted for the varying output power and duty cycle in Figure 5c.

In Figure 5d,e, the efficiency of the proposed converters and the suggested converters in [15,16,17,18,19,20,21,22,23,24,25,26] has been compared. According to Figure 5d, while the duty cycle varies from 0 to 50 percent, the variation of the efficiency is lower than 0.5 percent in the proposed converter. However, the mentioned variation is more than 2 percent. In addition, the efficiency of the proposed converter is approximately constant and equals 98.9 percent. Moreover, the efficiency of the introduced converter is 98.5 percent while the percentage of the duty cycle is 50 percent. According to Figure 5e, while the duty cycle varies from 50 to 85 percent, the efficiency of the converter is still more than 90 percent. However, the suggested converters in [15,16,17,18,19,20,21,22,23,24,25,26] have the same condition while the duty cycle is lower than 60 percent. Consequently, the proposed converter can provide higher voltage gain by the close value of the duty cycle to unity besides the high value of the efficiency.

5.2. Comparison of the Various Losses of the Proposed Converter with the Other Step-Up Topologies While the Duty Cycle Is Varying and Output Power Is 90 W

In Figure 6a,b, the inductor loss of the proposed converter has been compared with the inductor loss of [15,16,17,18,19,20,21,22,23,24,25,26]. In Figure 6a, the duty cycle varies from 0 to 50 percent, and in Figure 6b, the duty cycle varies from 40 percent to 80 percent. In Figure 6a, the inductor loss of the proposed converter is lower than the inductor loss of the converters of [22,24], higher than the remaining converters, and varies from 0.1 W to 0.4 W. In Figure 6b, while the duty cycle varies from 50 percent to 80 percent, the inductor loss of the proposed converter is lower than all the mentioned converters except for the converters of [16,21]. It is worth noting that the inductor loss of the proposed converter becomes lower than the mentioned converters of [16,21] while the duty cycle varies from 67 percent to 80 percent.

In Figure 6c,d, the switching loss of the proposed converter has been compared with the mentioned converters of [15,16,17,18,19,20,21,22,23,24,25,26] while the duty cycle varies from 0 to 50 percent and 45 percent to 90 percent respectively. As can be understood from Figure 6c, the switching loss of the proposed converter is lower than the mentioned converters of [22,24,26]. Moreover, it can be understood from Figure 6d they the switching loss of the proposed converter is lower than the mentioned converters of [17,21,22,24,26].

In Figure 6e, the diode loss of the proposed converter has been compared with the proposed converters of [15,16,17,18,19,20,21,22,23,24,25,26]. As can be understood, while the duty cycle varies from 0 to 50 percent, the diode loss of the proposed converter is lower than the mentioned converter of [24] and while the duty cycle varies from 50 percent to 80 percent, the diode loss of the proposed converter is lower than the mentioned converters of [15,16,17,18,19,20,21,22,23,24,25,26].

5.3. The Efficiency and Losses of the Proposed Converter for the Different Vales of the Output Power

In Figure 7a–f, the percentage of the efficiency and the different kinds of loss have been illustrated for the output power of 30 W, 60 W, 90 W, 120 W, 150 W, and 180 W. It is worth noting the percentage of the duty cycle is 50 percent. As can be understood, the major loss is diode loss. Moreover, an increase in the output power leads to an increase in the inductor loss to more than twice the switching loss. Furthermore, an increase of output power to more than 150 W concludes the higher value of the summation of the inductor and switch loss in comparison with the diode loss. It is worth noting that in all the mentioned output powers, the efficiency is more than 97 percent.

6. Small Signal Analysis

Based on the described relations of the capacitors and the inductors in the second section, the voltage of the inductors and the current of the capacitors can be written as below:

$$\left\{\begin{array}{c}{L}_1{\displaystyle \frac{d{i}_{L1}}{dt}}=<v_{in}>-(1-d)<v_{c1}>\hfill \\ L_2{\displaystyle \frac{d{i}_{L2}}{dt}}=d<v_{in}>-(1-d)<v_{c2}>\hfill \\ C_1{\displaystyle \frac{d{v}_{c1}}{dt}}=(1-d)<i_{L1}>-<{\displaystyle \frac{v_{c1}+v_{c2}}{R}}>\hfill \\ C_2{\displaystyle \frac{d{v}_{c2}}{dt}}=(1-d)<i_{L2}>-<{\displaystyle \frac{v_{c1}+v_{c2}}{R}}>\hfill \end{array}\right.$$

(14)

All the inductors current, capacitors voltage, and the duty cycle can be expressed as the summation of a DC and an AC term. It is worth noting that the mentioned AC term can be neglected as below:

$$\left\{\begin{array}{c}<i_{L_1}>=I_{L_1}+{\widehat{i}}_{L_1},<i_{L_2}>=I_{L_2}+{\widehat{i}}_{L_2},<v_{C_1}>=V_{C_1}+{\widehat{v}}_{C_1},<v_{C_2}>=V_{C_2}+{\widehat{v}}_{C_2},d=D+\widehat{d}\hfill \\ {\widehat{i}}_{L_1}<<I_{L_1},{\widehat{i}}_{L_2}<<I_{L_2},{\widehat{v}}_{C_1}<<V_{C_1},{\widehat{v}}_{C_2}<<V_{C_2},\widehat{d}<<D\hfill \end{array}\right.$$

(15)

The matrices of the space state equations have been expressed as below:

$${\displaystyle \frac{d\widehat{x}}{dt}}=Ax+B\widehat{d}$$

(16)

where

$${\widehat{x}}^t=\left[\begin{array}{c}{\displaystyle \frac{d{\widehat{i}}_{L_1}}{dt}},{\displaystyle \frac{d{\widehat{i}}_{L_2}}{dt}},{\displaystyle \frac{d{\widehat{v}}_{C_1}}{dt}},{\displaystyle \frac{d{\widehat{v}}_{C_2}}{dt}},\end{array}\right]$$

$$A=\left[\begin{array}{cccc}0& 0& {\displaystyle \frac{D-1}{L_1}}& 0\\ 0& 0& 0& {\displaystyle \frac{D-1}{L_2}}\\ {\displaystyle \frac{1-D}{C_1}}& 0& {\displaystyle \frac{-1}{R{C}_1}}& {\displaystyle \frac{-1}{R{C}_1}}\\ 0& {\displaystyle \frac{1-D}{C_2}}& {\displaystyle \frac{-1}{R{C}_2}}& {\displaystyle \frac{-1}{R{C}_2}}\end{array}\right]$$

$$B^t=\left[\begin{array}{c}{a}_1,a_2,a_3,a_4\end{array}\right]C=\left[\begin{array}{c}0,0,1,1\end{array}\right]$$

$$a_1={\displaystyle \frac{V_{C_1}}{L_1}},a_2={\displaystyle \frac{V_{C_2}}{L_2}},a_3={\displaystyle \frac{-I_{L_1}}{C_1}},a_4={\displaystyle \frac{-I_{L_2}}{C_2}}$$

(17)

Based on the matrices, the bode diagram of the proposed converter has been extracted and the phase and gain margin have been extracted −45.1 dB and −88.7 deg respectively. The bode diagram has been illustrated in Figure 8a. Based on the expressed space state equations, the compensator of the mentioned system has been calculated as below by MatLab.

$$C\left(S\right)={\displaystyle \frac{31.11}{s}}$$

(18)

According to the designed compensator, the bode diagram of the converter after compensating as in Figure 8b.

7. The Comparison of the Different Features of the Proposed Converter and Recently Suggested Topologies in an Operating Point

In

Table 1. Comparison of power loss.

	Inductors Loss	Switches Conduction Loss
proposed converters	$P_o{\displaystyle \frac{r_L}{R}}{\displaystyle \frac{2}{{(1-D)}^2}}=0.36$	$P_o{\displaystyle \frac{r_S}{R}}{\displaystyle \frac{2D}{{(1-D)}^2}}=0.18$
[15]	$P_o{\displaystyle \frac{r_L}{R}}{\displaystyle \frac{D^4-2D^3+3D^2-2D+1}{{(1-D)}^4}}=1.26$	$P_o{\displaystyle \frac{r_S}{R}}{\displaystyle \frac{2D^3-2D^2+D}{{(1-D)}^4}}=0.7$
[16]	$P_o{\displaystyle \frac{r_L}{R}}{\displaystyle \frac{2D^4-6D^3+8D^2-4D+1}{{(1-D)}^4}}=0.43$	$P_o{\displaystyle \frac{r_S}{R}}{\displaystyle \frac{2D^3-2D^2+D}{{(1-D)}^4}}=0.7$
[17]	$P_o{\displaystyle \frac{r_L}{R}}{\displaystyle \frac{3D^4-5D^3+7D^2-4D+1}{{(1-D)}^4}}=1$	$P_o{\displaystyle \frac{r_S}{R}}{\displaystyle \frac{5D^3-4D^2+D}{{(1-D)}^4}}=0.6$
[18]	$P_o{\displaystyle \frac{r_L}{R}}{\displaystyle \frac{2D^4-6D^3+8D^2-4D+1}{{(1-D)}^4}}=1$	$P_o{\displaystyle \frac{r_S}{R}}{\displaystyle \frac{2D^3-2D^2+D}{{(1-D)}^4}}=0.7$
[19]	$P_o{\displaystyle \frac{r_L}{R}}{\displaystyle \frac{2D^2-2D+1}{{(1-D)}^4}}=1.14$	$P_o{\displaystyle \frac{r_S}{R}}{\displaystyle \frac{2D^3-2D^2+D}{{(1-D)}^4}}=0.7$
[20]	$P_o{\displaystyle \frac{r_L}{R}}{\displaystyle \frac{2D^2-2D+1}{{(1-D)}^4}}=1.14$	$P_o{\displaystyle \frac{r_S}{R}}{\displaystyle \frac{2D^3-2D^2+D}{{(1-D)}^4}}=0.7$
[21]	$P_o{\displaystyle \frac{r_L}{R}}{\displaystyle \frac{5D^2-6D+2}{{(1-D)}^4}}=0.43$	$P_o{\displaystyle \frac{r_S}{R}}{\displaystyle \frac{5D^3-6D^2+2D}{{(1-D)}^4}}=0.27$
[22]	$P_o{\displaystyle \frac{r_L}{R}}{\displaystyle \frac{3D^2-4D+2}{{(1-D)}^4}}=0.91$	$P_o{\displaystyle \frac{r_S}{R}}{\displaystyle \frac{2D^3-6D^2+5D}{{(1-D)}^4}}=1.67$
[23]	$P_o{\displaystyle \frac{r_L}{R}}{\displaystyle \frac{2D^4-6D^3+8D^2-4D+1}{{(1-D)}^4}}=0.55$	$P_o{\displaystyle \frac{r_S}{R}}{\displaystyle \frac{2D^3-2D^2+D}{{(1-D)}^4}}=0.4$
[24]	$P_o{\displaystyle \frac{r_L}{R}}{\displaystyle \frac{D^2-2D+2}{{(1-D)}^4}}=1.6$	$P_o{\displaystyle \frac{r_S}{R}}{\displaystyle \frac{D^3-2D^2+2D}{{(1-D)}^4}}=0.9$
[25]	$P_o{\displaystyle \frac{r_L}{R}}{\displaystyle \frac{2D^2-2D+1}{{(1-D)}^4}}=0.67$	$P_o{\displaystyle \frac{r_S}{R}}{\displaystyle \frac{2D^3-2D^2+2D}{{(1-D)}^4}}=0.4$
[26]	$P_o{\displaystyle \frac{r_L}{R}}{\displaystyle \frac{2D^2-2D+1}{{(1-D)}^4}}=0.36$	$P_o{\displaystyle \frac{r_S}{R}}{\displaystyle \frac{D^3-2D^2+D}{{(1-D)}^4}}=0.45$

,

Table 2. Comparison of power loss.

	Switching Loss of Switches	Diodes Loss	Duty Cycle
proposed converters	${\displaystyle \frac{f_s{P}_o{t}_{off}D}{1-D^2}}=0.06$	$2V_{DF}{I}_o=1$	0.5
[15]	${\displaystyle \frac{f_s{P}_o{t}_{off}(1+D)}{1-D}}=0.04$	${\displaystyle \frac{V_{DF}{I}_o}{1-D}}=1.315$	0.62
[16]	${\displaystyle \frac{f_s{P}_o{t}_{off}}{1-D}}=0.02$	${\displaystyle \frac{V_{DF}{I}_o}{1-D}}=1.31$	0.62
[17]	${\displaystyle \frac{f_s{P}_o{t}_{off}D}{{(1-D)}^2}}=0.04$	${\displaystyle \frac{V_{DF}{I}_o}{1-D}}=1.31$	0.62
[18]	${\displaystyle \frac{f_s{P}_o{t}_{off}}{1-D}}=0.02$	${\displaystyle \frac{V_{DF}{I}_o}{1-D}}=1.31$	0.62
[19]	${\displaystyle \frac{f_s{P}_o{t}_{off}}{1-D}}=0.02$	${\displaystyle \frac{V_{DF}{I}_o}{1-D}}=1.31$	0.62
[20]	${\displaystyle \frac{f_s{P}_o{t}_{off}}{1-D}}=0.02$	${\displaystyle \frac{V_{DF}{I}_o}{1-D}}=1.31$	0.62
[21]	${\displaystyle \frac{f_s{P}_o{t}_{off}(3D-1)}{D(1-D)}}=0.11$	${\displaystyle \frac{V_{DF}{I}_o}{1-D}}=1.31$	0.62
[22]	${\displaystyle \frac{f_s{P}_o{t}_{off}(1+D)}{1-D}}=0.03$	${\displaystyle \frac{V_{DF}{I}_o(1+D)}{1-D}}=1.8$	0.57
[23]	${\displaystyle \frac{f_s{P}_o{t}_{off}(1+D)}{1-D}}=0.03$	${\displaystyle \frac{V_{DF}{I}_o}{1-D}}=1.15$	0.57
[24]	${\displaystyle \frac{f_s{P}_o{t}_{off}(1+D)}{1-D}}=0.03$	${\displaystyle \frac{V_{DF}{I}_o(2-D)}{1-D}}=1.65$	0.57
[25]	${\displaystyle \frac{f_s{P}_o{t}_{off}(1+D)}{1-D}}=0.03$	${\displaystyle \frac{V_{DF}{I}_o}{1-D}}=1.15$	0.57
[26]	${\displaystyle \frac{f_s{P}_o{t}_{off}}{(1-D)(2-D)}}=0.01$	${\displaystyle \frac{V_{DF}{I}_o(1+D)}{1-D}}=1.5$	0.5

,

Table 3. Comparison of voltage stress.

	${\displaystyle \frac{V_{S1}}{V_O}}$	${\displaystyle \frac{V_{S2}}{V_O}}$	${\displaystyle \frac{V_{D1}}{V_O}}$	${\displaystyle \frac{V_{D2}}{V_O}}$
proposed converter	${\displaystyle \frac{1}{1+D}}=0.67$	${\displaystyle \frac{1}{1+D}}=0.67$	${\displaystyle \frac{1}{1+D}}=0.67$	${\displaystyle \frac{1}{1+D}}=0.67$
[15]	${\displaystyle \frac{1-D}{D^2}}$ = 1	1	${\displaystyle \frac{1-D}{D^2}}$ = 1	${\displaystyle \frac{1}{D}}$ = 1.61
[16]	${\displaystyle \frac{1-D}{D^2}}$ = 1	${\displaystyle \frac{1}{D}}$ = 1.61	${\displaystyle \frac{1-D}{D^2}}$ = 1	${\displaystyle \frac{1}{D}}$ = 1.61
[17]	${\displaystyle \frac{1}{D^2}}$ = 2.68	${\displaystyle \frac{1}{D}}$ = 1.61	${\displaystyle \frac{1-D}{D^2}}$ = 1	${\displaystyle \frac{1}{D}}$ = 1.61
[18]	${\displaystyle \frac{1-D}{D^2}}$ = 1	${\displaystyle \frac{1}{D}}$ = 1.61	${\displaystyle \frac{1-D}{D^2}}$ = 1	${\displaystyle \frac{1}{D}}$ = 1.61
[19]	${\displaystyle \frac{1-D}{D^2}}$ = 1	${\displaystyle \frac{1}{D}}$ = 1.61	${\displaystyle \frac{1-D}{D^2}}$ = 1	${\displaystyle \frac{1}{D}}$ = 1.61
[20]	${\displaystyle \frac{1-D}{D^2}}$ = 1	${\displaystyle \frac{1}{D}}$ = 1.61	${\displaystyle \frac{1-D}{D^2}}$ = 1	${\displaystyle \frac{1}{D}}$ = 1.61
[21]	${\displaystyle \frac{1-D}{D^2}}$ = 1	${\displaystyle \frac{1}{D}}$ = 1.61	${\displaystyle \frac{1-D}{D^2}}$ = 1	${\displaystyle \frac{1}{D}}$ = 1.61
[22]	${\displaystyle \frac{1-D}{D^2}}$ = 1.32	${\displaystyle \frac{2D-1}{D}}$ = 1.61	${\displaystyle \frac{1-D}{D}}$ = 0.75	1
[23]	${\displaystyle \frac{1-D}{D}}$ = 0.75	${\displaystyle \frac{1}{D}}$ = 1.61	${\displaystyle \frac{1-D}{D}}$ = 0.75	${\displaystyle \frac{1}{D}}$ = 1.75
[24]	${\displaystyle \frac{1-D}{D}}$ = 0.75	1	${\displaystyle \frac{1-D}{D}}$ = 0.75	1
[25]	${\displaystyle \frac{1-D}{D}}$ = 0.75	${\displaystyle \frac{1}{D}}$ = 1.75	${\displaystyle \frac{1-D}{D}}$ = 0.75	${\displaystyle \frac{1}{D}}$ = 1.75
[26]	${\displaystyle \frac{1-D}{D(2-D)}}$ = 0.67	${\displaystyle \frac{1}{D(2-D)}}$ = 1.33	${\displaystyle \frac{1-D}{D(2-D)}}$ = 0.67	${\displaystyle \frac{1}{D(2-D)}}$ = 1.33

,

Table 4. Comparison of current stresses.

	${\displaystyle \frac{I_{S1}}{I_{in}}}$	${\displaystyle \frac{I_{S2}}{I_{in}}}$	${\displaystyle \frac{I_{D1}}{I_{in}}}$	${\displaystyle \frac{I_{D2}}{I_{in}}}$	D
proposed converter	${\displaystyle \frac{D}{1+D}}=0.34$	${\displaystyle \frac{D}{1+D}}=0.34$	${\displaystyle \frac{1-D}{1+D}}=0.34$	${\displaystyle \frac{1-D}{1+D}}=0.34$	0.5
[15]	1	${\displaystyle \frac{1-D}{D}}$ = 0.61	${\displaystyle \frac{1-D}{D}}$ = 0.61	${\left({\displaystyle \frac{1-D}{D}}\right)}^2$ = 0.34	0.62
[16]	1	${\displaystyle \frac{1-D}{D}}$ = 0.61	${\displaystyle \frac{1-D}{D}}$ = 0.61	${\left({\displaystyle \frac{1-D}{D}}\right)}^2$ = 0.34	0.62
[17]	1	${\displaystyle \frac{2D-1}{D}}$ = 0.61	${\displaystyle \frac{2D-1}{D}}$ = 0.61	${\left({\displaystyle \frac{1-D}{D}}\right)}^2$ = 0.34	0.62
[18]	1	${\displaystyle \frac{1-D}{D}}$ = 0.61	${\displaystyle \frac{1-D}{D}}$ = 0.61	${\left({\displaystyle \frac{1-D}{D}}\right)}^2$ = 0.34	0.62
[19]	1	${\displaystyle \frac{1-D}{D}}$ = 0.61	${\displaystyle \frac{1-D}{D}}$ = 0.61	${\left({\displaystyle \frac{1-D}{D}}\right)}^2$ = 0.34	0.62
[20]	1	${\displaystyle \frac{1-D}{D}}$ = 0.61	${\displaystyle \frac{1-D}{D}}$ = 0.61	${\left({\displaystyle \frac{1-D}{D}}\right)}^2$ = 0.34	0.62
[21]	1	${\displaystyle \frac{1-D}{D}}$ = 0.61	${\displaystyle \frac{1-D}{D}}$ = 0.61	${\left({\displaystyle \frac{1-D}{D}}\right)}^2$ = 0.34	0.62
[22]	$2-D$ = 1.43	$1-D$ = 0.43	${\displaystyle \frac{1-D}{D}}$ = 0.75	${\displaystyle \frac{{(1-D)}^2}{D}}$ = 0.34	0.57
[23]	D = 0.57	$1-D$ = 0.43	$1-D$ = 0.43	${\displaystyle \frac{{(1-D)}^2}{D}}$ = 0.34	0.57
[24]	1	$1-D$ = 0.43	${\displaystyle \frac{1-D}{D}}$ = 0.75	${\displaystyle \frac{{(1-D)}^2}{D}}$ = 0.34	0.57
[25]	D = 0.57	$1-D$ = 0.43	$1-D$ = 0.43	${\displaystyle \frac{{(1-D)}^2}{D}}$ = 0.34	0.57
[26]	${\displaystyle \frac{1}{D(2-D)}}$ = 1.34	${\displaystyle \frac{1-D}{2-D}}$ = 0.34	${\displaystyle \frac{1-D}{D(2-D)}}$ = 0.67	${\displaystyle \frac{{(1-D)}^2}{D(2-D)}}$ = 0.34	0.5

,

Table 5. Comparison of components number and voltage gain.

	No. L	No. C	No. S	No. D	No.
[15]	3	3	2	2	10
[16]	2	2	2	2	8
[17]	3	3	2	2	10
[18]	3	3	2	2	10
[19]	2	2	2	2	8
[20]	2	2	2	2	8
[21]	2	2	2	2	8
[22]	3	3	2	2	10
[23]	3	3	2	2	10
[24]	2	2	2	2	8
[25]	2	2	2	2	8
[26]	2	2	2	2	8
proposed	2	2	2	2	8

and

Table 6. Comparison of stored energy.

	Stored Energy of Inductors
proposed converters	${\displaystyle \frac{2D}{1+D}}{\displaystyle \frac{{V^2}_o}{2k{f}_{s}R}}=1$ mJ
[15]	${\displaystyle \frac{1+D}{D}}{\displaystyle \frac{{V^2}_o}{2k{f}_{s}R}}=3.91$ mJ
[16]	$2{\displaystyle \frac{{V^2}_o}{2k{f}_{s}R}}=3$ mJ
[17]	$2{\displaystyle \frac{{V^2}_o}{2k{f}_{s}R}}=3$ mJ
[18]	$2{\displaystyle \frac{{V^2}_o}{2k{f}_{s}R}}=3$ mJ
[19]	$2{\displaystyle \frac{{V^2}_o}{2k{f}_{s}R}}=3$ mJ
[20]	$2{\displaystyle \frac{{V^2}_o}{2k{f}_{s}R}}=3$ mJ
[21]	$2{\displaystyle \frac{{V^2}_o}{2k{f}_{s}R}}=3$ mJ
[22]	$(1+D){\displaystyle \frac{{V^2}_o}{2k{f}_{s}R}}=2.35$ mJ
[23]	$(1+D){\displaystyle \frac{{V^2}_o}{2k{f}_{s}R}}=2.35$ mJ
[24]	$(1+D){\displaystyle \frac{{V^2}_o}{2k{f}_{s}R}}=2.35$ mJ
[25]	$(1+D){\displaystyle \frac{{V^2}_o}{2k{f}_{s}R}}=2.35$ mJ
[26]	${\displaystyle \frac{2}{2-D}}{\displaystyle \frac{{V^2}_o}{2k{f}_{s}R}}=2$ mJ

, different features have been compared for 90 W output power, the corresponding duty cycle of three times voltage gain, and 1 A output current. It is worth noting that the inductors loss and conduction loss of switches have been compared. It can be understood that the proposed converter has the lowest inductor loss as well as the switch loss in comparison with [15,16,17,18,19,20,21,22,23,24,25,26]. Moreover, the switching loss of the switches, diode loss, corresponding duty cycle, and efficiency have been reported in Table 2. It is worth noting that the switching loss of the proposed converter is more than in [15,16,17,18,19,20,21,22,23,24,25,26]. However, the diode loss of the proposed converter has achieved the lowest value. Moreover, the proposed converter employs a lower value of the duty cycle in comparison with [15,16,17,18,19,20,21,22,23,24,25]. In the third and fourth tables, the normalized values of the voltage/current stresses of semiconductors have been reported and compared. It is worth noting that the output voltage and input current have been considered as the base values of the voltage/current stresses respectively. It can be understood that the voltage stress of the second switch and diode has the lowest value in comparison with [15,16,17,18,19,20,21,22,23,24,25,26]. Moreover, the voltage stress of the first switch and diode has a lower value in comparison with [15,16,17,18,19,20,21,22,23,24,25]. Furthermore, according to Table 3, the current stress of the first switch and diode has the lowest value among [15,16,17,18,19,20,21,22,23,24,25,26]. It is worth noting that the current stress of the second switch in the proposed converter is lower than in [15,16,17,18,19,20,21,22,23,24,25]. It has to be remembered that the current stress of the second diode is the same in all converters. In the fifth table, the number of the circuit components has been compared. It can be understood that the proposed converter has two inductors, capacitors, switches, and diodes, which is the as same as [16,19,20,24,25,26]. In other words, the rest of them have three inductors and capacitors and two switches and diodes. In the sixth table, the stored energy of the inductors has been calculated and reported. It can be understood that the proposed converter has the lowest storage energy. It is worth noting that the dimension of the converter is relative to the stored energy of the converter. Consequently, it can be stated that the proposed converter has the lowest dimension among [15,16,17,18,19,20,21,22,23,24,25,26].

8. Simulation and Experimental Results

To simulate the proposed converter, the inductors’ and capacitors’ values have to be found. Therefore, the expressed equations of current/voltage ripples in (4) are used. In addition, the switching frequency and percentage of current/voltage ripples have to be valued. Due to equipment limits, the frequency has been assumed 100 kHz. Moreover, the current ripple of the inductors and voltage ripple of the capacitors have been considered 30 and 5 percent respectively. It is worth noting that, to use the percentage of the current/voltage ripples with their corresponding equations, the average current of the inductors and average voltage of capacitors have been calculated as (19):

$$\left\{\begin{array}{c}{V}_{in}=30\mathrm{V},V_{C1}=60\mathrm{V},V_{C2}=30\mathrm{V},D=0.5\hfill \\ I_{L1}=I_{L2}=2\mathrm{A},I_o=1\mathrm{A}\hfill \end{array}\right.$$

(19)

PLECS software has been used to extract the simulation outcomes. The version of the employed software is 4.1.2. The inductors and capacitors value based on (4), (19) are as (20):

$$L_1=L_2>250\mathsf{\mu }\mathrm{H},C_1>1.6\mathsf{\mu }\mathrm{F},C_2>3.2\mathsf{\mu }\mathrm{F}$$

(20)

The inductors current and capacitors voltage have been presented in Figure 9a–e. The average current of the inductors and average voltage of the capacitors are as (21):

$$I_{L1}=2\mathrm{A},I_{L2}=1.8\mathrm{A},V_{C1}=59.9\mathrm{V},V_{C2}=30.1\mathrm{V},V_o=90\mathrm{V}$$

(21)

A comparison between (21) and (19) defines their compatibility. Therefore, the validity of the expressed relations of (2) and (4) is improved. In Figure 9f–i, the current waveforms of the switches and diodes have been illustrated. According to these figures, the average current of the semiconductors is 1 A. Moreover, it can be understood that the switches and diodes operate asynchronously as well as stated in the second section. According to (1), the applied voltage to the inductors is 30 V and −30 V in the first and second modes respectively. It is worth noting that these values are compatible with Figure 9j,k. Moreover, in the first mode, the crossing current from the capacitors is $-I_o$. Furthermore, in the second mode $I_L-I_o$ crosses the capacitors. It is worth noting that the current waveforms of Figure 9l,m are compatible with the mentioned concepts. It is also worth noting that the applied voltage to the semiconductors during their inactivation mode is compatible with the extracted equations in (3). In Figure 10, the boost and buck-boost converters have been simulated to increase 30 V input source to 90 V output. It is worth noting that 66 percent and 75 percent duty cycles cause the voltage gain of three in the boost and buck-boost converters respectively. The presented results in Figure 10a–h are for the boost converter and the remaining is for the buck-boost one. In comparison with the proposed converter, the boost and buck-boost converters require a higher duty cycle to have a three times voltage gain. Moreover, according to Figure 10g,h,o,p the semiconductors experience higher voltage during their inactivation mode. Furthermore, based on Figure 10e,f,m,n the semiconductors experience higher current during their activation. Consequently, the proposed converter provides the mentioned voltage gain with a lower duty cycle and semiconductors’ current/voltage stresses. In Figure 11, the details of the used drivers have been presented. Moreover, IRF540 and 2015OCT are the types of MOSFETs and diodes used. Furthermore, all the used capacitors are MKT capacitors with a low equivalent series resistance (ESR). In Figure 12, the experimental results of the proposed converter have been illustrated. Based on the expressed values of the inductors and capacitors in (20), the voltage waveforms of the capacitors and current waveforms of the inductors have been illustrated. In addition, their average values have been expressed in (21):

$$I_{L1}=I_{L2}=2\mathrm{A},V_{C1}=60\mathrm{V},V_{C2}=30\mathrm{V},V_o=90\mathrm{V}$$

(22)

A comparison between the extracted values from experimental and simulation results defines their compatibility. Moreover, according to Figure 12d,e, the current of capacitors and the voltage of the inductors have been presented. Furthermore, their average value is zero and compatible with the current/voltage second balance. It is worth noting that the current/voltage waveforms of the semiconductors have been presented in Figure 12c,d. The average value of their currents is 1 A and compatible with the extracted equation in (3). Furthermore, the applied voltage during inactivation mode is as same as simulation results.

It is worth noting that the voltage gain of the converter has been extracted for different values of the duty cycle from the prototype and compared with the theoretical relation of the non-ideal voltage gain in Figure 13. It can be understood that both results are the same as each other while the duty cycle varies from 67 percent. Moreover, as the duty cycle increases from 67 percent, a difference takes place between the theoretical and experimental results. In Figure 14, the efficiency of the converter has been extracted for the different values of the output powers and 50 percent duty cycle based on the theory and experiment. It is worth noting that the efficiency of the proposed converter varies from 99 to 97.8 percent while the output power varies from 30 W to 180 W. However, based on the experimental results, the efficiency varies from 95.2 to 89 percent in the mentioned interval of the duty cycle. It is good to mention that the differences in the extracted results have occurred due to neglecting some kinds of loss and quality of the used circuit components. This difference is more obvious in Figure 15 where the efficiency has been extracted from the theoretical relations and experimental results for the varying duty cycle from 20 to 80 percent. It is also good to mention that the prototype of the converter has been presented in Figure 16.

9. Conclusions

In this paper, a novel combination of the conventional DC-DC converters was proposed. Due to the use of conventional converters, it was capable of providing a high value of the voltage gain besides a high value of the efficiency. It was discussed that the proposed converter was capable of providing an efficiency higher than 90 for a great interval of the duty cycle. Moreover, the different kinds of losses and current/voltage stresses were expressed and compared with the recently suggested converters in an operating point. Furthermore, the stored energy of the converter was compared with other high gain converters and the lower dimension of the proposed topology was concluded. Additionally, the voltage gain and efficiency of the proposed converter were compared with other high gain converters for all values of the duty cycle. In all the mentioned comparisons the better function of the proposed converter was deduced. It is worth noting that the small-signal analysis was done and a suitable compensator was designed. Finally, the simulation results of the proposed converter were extracted as well as the conventional converters by PLECS and compared with each other. Furthermore, the advantages of the proposed converter were discussed in comparison with the boost and buck-boost converters according to the simulation results. Furthermore, the experimental results were discussed and compared with the simulation results and theoretical considerations. Additionally, the efficiency of the converter was compared based on the theoretical and experimental results, and their differences were discussed for a varying output power besides a constant duty cycle as well as the duty cycle is varying besides a constant output power. It is worth noting that the same study was done for the voltage gain and the extracted equation of the non-ideal voltage gain was validated. It is good to mention that due to the use of buck-boost and boost with each other in the proposed converter, the continuous input current of the proposed converter was provided beside a high current ripple. In future work, the ZVS and ZCS techniques are going to be investigated in the proposed topology, and a strong control method to be applied to its controlling concepts. As the last concept, this converter is not suitable for high power applications and it is recommended to employ this topology for output powers that are lower than 200 W.