Effects of Annealing Temperature Combinations in InO_x/AlO_x Heterostructure for High-Performance and Stable Solution-Processed Junctionless Transistors

Abstract

Junctionless (JL) thin-film transistors (TFTs) are promising candidates for low-cost, large-area electronic devices, but improvements in mobility and bias stability are still required. In this study, the effects of independent annealing of the indium oxide (InO_x) channel layer and the aluminum oxide (AlO_x) capping layer (CL) on the performance and reliability of InO_x/AlO_x heterostructure JL TFTs are examined. Devices were fabricated via solution deposition and photopatterning, and the InO_x and AlO_x layers were annealed at 250 °C and 400 °C. Increasing the annealing temperature from 250 °C to 400 °C, the InO_x layer crystallized and densified. The AlO_x layer remained amorphous at both temperatures, but its metal-hydroxyl content decreased with higher annealing. For both layers, JL TFTs annealed at 400 °C exhibited the best electrical performance (threshold voltage = 1.82 ± 0.40 V, subthreshold swing = 0.50 ± 0.07 V dec⁻¹, saturation mobility = 1.57 ± 0.37 cm² V⁻¹ s⁻¹). The threshold voltage shift under positive bias stress was 1.70 V, which demonstrates excellent bias stability. These results show that simultaneous high-temperature annealing of the channel and CL is essential to reduce trap-assisted scattering and stabilize electrostatics in JL TFTs, providing practical process guidelines for bias-stable and high-performance oxide electronics.

1. Introduction

Oxide semiconductor (OS)-based thin-film transistors (TFTs) have emerged as key building blocks for next-generation electronics owing to their wide bandgap nature that enables high optical transparency, strong stability under high electric fields, and high breakdown voltage, as well as their inherent advantages of very low leakage current and compatibility with low-temperature (<400 °C) processing [1,2,3,4]. OS technology has successfully replaced hydrogenated amorphous silicon in displays and has become the standard backplane for organic light-emitting diode panels [5]. Beyond displays, OS TFTs show strong potential for back-end-of-line compatible transistor applications in monolithic three-dimensional integration and are increasingly investigated for optoelectronics, sensors, and neuromorphic computing [6,7,8].

OS-based junctionless (JL) TFTs are attracting attention because their architecture simplifies fabrication by eliminating source-drain (S-D) junction formation and reducing the overall process complexity and cost [9,10]. The advantages of JL TFTs become even greater when they are implemented through solution process with solution-compatible, photolithography-free patterning methods. However, conventional OS TFTs are typically fabricated via mature vacuum processes (e.g., sputtering) and conventional photolithography [11,12,13]. These OS TFTs generally exhibit excellent electrical characteristics and reliability. Recent studies have reported field-effect mobility comparable to that of low-temperature polycrystalline silicon TFTs [14,15]. In contrast, OS TFTs fabricated using solution process often exhibit relatively low mobility and reliability [16]. This suggests that while using solution process is attractive to maximize the benefits of JL TFTs, improvements in electrical performance and reliability are still required.

In solution-processed JL TFTs, the channel and conductive S–D regions are defined by the selective formation of an oxide capping layer (CL) that modulates carrier concentration of the channel. Heterostructures such as indium oxide/aluminum oxide (InO_x/AlO_x) are promising, as the AlO_x CL both passivates the back channel and suppresses excess carriers in the InO_x channel [17]. Precise control of carrier concentration in the channel and S–D regions is crucial, since excessive conductivity prevents full depletion under negative gate bias, while overly resistive S–D regions reduce on current and saturation mobility (μ_SAT) [18]. Therefore, co-optimizing the channel and CL properties (balancing carrier concentration, trap density, and structural quality) is essential. This requires understanding how thermal treatment of semiconductor and CLs affects electron concentration, defect states, and crystallinity, and consequently determines key device parameters such as threshold voltage (V_T) and subthreshold swing (SS).

In addition, for n-type OS TFT-based display backplanes and integrated driver circuits, robustness under positive bias stress (PBS) is a key performance indicator because the devices are repeatedly subjected to positive gate bias [19]. The threshold voltage shift (ΔV_T) under bias directly affects pixel current accuracy and lifetime uniformity. Therefore, optimizing the thermal annealing of both the semiconductor layer and the CL in JL heterostructures is crucial for ensuring device reliability [20].

In this study, we systematically examine the effects of annealing combinations of the InO_x semiconductor and AlO_x CL on the electrical characteristics and reliability of solution-processed InO_x/AlO_x heterojunction JL TFTs. The devices were fabricated using a minimal and efficient process based on solution deposition and photopatterning. The InO_x and AlO_x layers were each annealed at either 250 °C or 400 °C to generate the target combinations. To clarify how the channel and CL properties affect device behavior, transmission electron microscopy (TEM), X-ray photoelectron spectroscopy (XPS), and X-ray reflectivity (XRR) were employed. The contact and channel resistances were separated using the transmission line method (TLM) to isolate the effect of heat treatment on the resistance components.

The bias stability of the device was then evaluated through PBS test. The results revealed that annealing not only InO_x but also AlO_x significantly improved μ_SAT and reduced SS. Furthermore, simultaneous high-temperature annealing of InO_x and AlO_x produced the most favorable device characteristics—namely, the highest μ_SAT, lowest SS, and an appropriate positive V_T, and the smallest ΔV_T under PBS—thereby providing a clear pathway toward high-performance, bias-stable JL TFTs.

2. Materials and Methods

2.1. Preparation of Oxide Precursor Solutions

InO_x and AlO_x precursor solutions were prepared for JL TFT fabrication. A 0.1 M InO_x solution was synthesized by dissolving indium nitrate hydrate (In(NO₃)₃·xH₂O) in 2-methoxyethanol (2-ME). A 0.3 M AlO_x solution was prepared by dissolving aluminum nitrate nonahydrate (Al(NO₃)₃·9H₂O) in 2-ME. All solutions were prepared 24 h before use. The mixtures were stirred at 50 °C for 12 h and then aged under ambient conditions for 12 h to obtain clear, homogeneous solutions.

2.2. Fabrication of Devices

Heavily doped p-type silicon wafers with a 100 nm thermally grown SiO₂ gate dielectric were cleaned by sequential ultrasonication in acetone, isopropyl alcohol, and deionized (DI) water for 10 min each. Ultraviolet (UV)-ozone treatment was then performed to remove organic residues and improve surface hydrophilicity. The InO_x solution was spin-coated onto the SiO₂/p-type Si substrates at 3000 rpm for 20 s. In this configuration, the p-type Si and SiO₂ serve as the gate and gate insulator, respectively. Patterning of the oxide films was carried out using a water etchant-based photopatterning method previously reported [21]. The substrates were soft-baked at 100 °C for 10 s, followed by UV-ozone treatment through a fine metal mask for 3 min. After exposure, the mask was removed, and the substrates were developed by DI water etching for 1 min. The UV-patterned InO_x layers were pre-annealed at 100 °C for 5 min and then post-annealed at either 250 °C or 400 °C for 1 h in ambient air. The AlO_x solution was spin-coated onto the InO_x layer at 3000 rpm for 20 s. The same photopatterning procedure was used to define the channel regions, with soft-bake and UV exposure times optimized for AlO_x. Since the concentration and thickness of solution-processed films tend to be proportional, the AlOx layer formed under the same coating and annealing conditions was approximately three times thicker than the InO_x layer. The patterned AlO_x CLs were pre-annealed at 100 °C for 5 min and then post-annealed at either 250 °C or 400 °C for 1 h in ambient air. Three types of TFTs were fabricated with different heat-treatment combinations. InO_x films annealed at 250 °C and 400 °C are denoted as InO-250 and InO-400. Likewise, AlO_x films annealed at 250 °C and 400 °C are denoted as AlO-250 and AlO-400. The channel length (L_ch) and width (W_ch) of all devices were 100 μm and 500 μm, respectively.

2.3. Analysis of Thin Films and Devices

The chemical composition of the InO_x and AlO_x films was characterized by X-ray photoelectron spectroscopy (XPS, NEXSA, Thermo Fisher Scientific, Waltham, MA, USA) using an Al Kα radiation source (1486.6 eV). For the quantitative analysis of film density, X-ray reflectivity (XRR, ATX-G, Rigaku, Tokyo, Japan) measurements were performed to evaluate the film density of InO_x and AlO_x. For accurate XRR analysis of film density, a film thickness exceeding 5 nm was required. Both 0.3 M indium oxide and 0.3 M aluminum oxide precursor solutions were used to prepare the films. The density values were extracted by fitting the Kiessig fringes in the XRR spectra, providing reliable and quantitative estimation of the mass density based on electron density contrast. The electrical characteristics of the TFTs were measured with a semiconductor parameter analyzer (4200A-SCS, Keithley, Cleveland, OH, USA). All measurements were conducted at room temperature under dark conditions. V_T was determined by the constant current method, defined as the gate voltage (V_G) that induces a drain current (I_D) = 10 nA × W_ch L_ch⁻¹. SS was obtained from the subthreshold region in the current range of I_D = 1 to 10 nA, based on the following equation:

$$\mathrm{S}\mathrm{S}={\displaystyle \frac{{\mathrm{d}\mathrm{V}}_{\mathrm{G}}}{{\mathrm{d}\mathrm{l}\mathrm{o}\mathrm{g}}_{{\mathrm{I}}_{\mathrm{D}}}}}$$

(1)

The I–V characteristics in the saturation region are described by the following equation [22]:

$${\mathrm{I}}_{\mathrm{D},\mathrm{s}\mathrm{a}\mathrm{t}}={\displaystyle \frac{1}{2}}{\mathsf{\mu }}_{\mathrm{S}\mathrm{A}\mathrm{T}}{\mathrm{C}}_{\mathrm{o}\mathrm{x}}{\displaystyle \frac{\mathrm{W}}{\mathrm{L}}}{\left({\mathrm{V}}_{\mathrm{G}}-{\mathrm{V}}_{\mathrm{T}}\right)}^2$$

(2)

C_OX denotes gate capacitance per unit area of the insulator layer. μ_SAT was extracted at V_G = V_T + 10 V with the drain voltage (V_D) = 30 V. The contact resistance (R_C) and channel sheet resistance (R_SH) were calculated using the transmission line method (TLM) with the following equation [23]:

$${\mathrm{R}}_{\mathrm{T}\mathrm{o}\mathrm{t}\mathrm{a}\mathrm{l}}={\displaystyle \frac{{\mathrm{V}}_{\mathrm{D}}}{{\mathrm{I}}_{\mathrm{D}}}}={\displaystyle \frac{\mathrm{L}}{\mathrm{W}}}{\mathrm{R}}_{\mathrm{S}\mathrm{H}}+2{\mathrm{R}}_{\mathrm{C}}$$

(3)

3. Results and Discussion

3.1. Concept and Operation of JL TFTs

The device proposed in this study is a JL TFT composed of an InO_x semiconductor and an AlO_x CL. Figure 1a,b illustrate the fabrication process flow and the device architecture, respectively. Figure 1c presents an optical microscope image of the fabricated JL TFT, where the L_ch, W_ch, and offset region (L_offset) are defined. Similarly to conventional TFT structures, a short L_ch is desirable for high on-state current, but short-channel effects must be considered. Furthermore, a short L_offset contributes to lowering the contact resistance of the device. In this work, L_ch, W_ch, and L_offset were fixed at 100, 500, and 400 μm, respectively, for all devices. The transfer characteristics of JL TFTs with and without the AlO_x CL are shown in Figure 1d to verify the functional role of the CL. Devices without AlO_x exhibited no discernible switching, indicating which confirms that the CL is essential for enabling switching operation. Figure 1e schematically depicts the underlying mechanism. During thermal annealing, Al and O diffuse into the InO_x layer, suppressing the electron concentration by reducing the oxygen vacancy (V_O) density to a level suitable for TFT operation [24]. The observed decrease in electron concentration near the InO_x/AlO_x interface can be attributed to the strong oxygen affinity of Al. During the capping process, partial Al–O interdiffusion occurs, which suppresses oxygen vacancies in the underlying InO_x layer. As oxygen vacancies act as electron donors in InO_x-based oxides, their reduction lowers the free-electron density and shifts the Fermi level toward the mid-gap. Consequently, the conduction-band minimum is raised, resulting in reduced carrier concentration near the interface [25,26,27]. As a result, the InO_x-only film remains highly conductive and cannot be fully depleted, whereas diffusion from the AlO_x CL modulates the conductivity of InO_x. This CL-driven carrier modulation is the key principle that enables JL TFT operation.

3.2. Effects of Annealing Temperature on the Structural and Chemical Characteristics of the InO_x Semiconductor and AlO_x CL

To investigate the structural effects of annealing temperature on the InO_x/AlO_x stack, cross-sectional TEM analyses were performed. Figure 2a–c show TEM images of InO-250/AlO-250, InO-400/AlO-250, and InO-400/AlO-400 stacked films, respectively. A well-defined bilayer is observed in all cases. The AlO_x layer exhibits a relatively uniform, amorphous phase regardless of annealing condition, which is consistent with the known amorphous nature of AlO_x even at high annealing temperatures. To assess crystallinity, the corresponding fast Fourier transform (FFT) patterns are shown in Figure 2d–f. In the InO-250/AlO-250 sample, the InO_x layer exhibits a diffused halo, which is characteristic of amorphous materials. In contrast, the InO-400/AlO-250 sample exhibits discernible diffraction spots, while the InO-400/AlO-400 sample shows sharper, more distinct spots, indicative of a higher crystalline fraction. These results confirm that InO_x undergoes a significant amorphous-to-crystalline transition at 400 °C, forming an ordered matrix that is expected to reduce structural disorder and facilitate charge transport. By comparison, AlO_x remains amorphous under all annealing conditions, as corroborated by its FFT halos. The absence of grain boundaries in amorphous AlO_x supports its role as a passivation layer that effectively blocks moisture and oxygen from the environment.

XPS was employed to analyze changes in chemical bonding in InO_x and AlO_x as a function of annealing temperature. All spectra were calibrated to the C 1s reference at 284.8 eV. The O 1s envelope was deconvolved into three Gaussian components at approximately 530.15, 530.86, and 532.07 eV, corresponding to lattice metal–oxygen bonds (M–O), V_O, and metal–hydroxide (M–OH), respectively. Figure 3a compares the O 1s spectra of InO-250 (left) and InO-400 (right). The relative fractions of M–O, V_O, and M–OH were 63.7%, 20.3%, and 15.9% for InO-250 and 70.1%, 20.9%, and 8.3% for InO-400, respectively. These results indicate that high-temperature annealing effectively removes hydroxyl species, thereby strengthening M–O bonding and stabilizing the oxide network. A similar trend was observed in AlO_x (Figure 3b), where the M–OH fraction decreased from 32.3% to 29.4% and the M–O fraction increased from 67.7% to 70.8% with higher annealing temperature. Figure 3c,d shows In 3d spectra of InO_x and Al 2p spectra of AlO_x films, respectively. The In 3d spectrum exhibits two well-defined peaks at approximately 444.5 eV (In 3d_5/2) and 452.0eV (In 3d_3/2), corresponding to the spin–orbit doublet characteristic of fully oxidized In³⁺ in InO_x. No metallic indium component was detected, confirming complete oxidation of the InO_x layer. Similarly, the Al 2p spectrum shows a single sharp peak centered at ~74.4 eV, consistent with Al³⁺ in AlO_x. These results indicate that both InO_x and AlO_x films maintain stable stoichiometric oxide states without sub-oxide or metallic phases. XRR data are shown in Figure 3e,f for InO_x and AlO_x, respectively. In InO_x, the density increased from 5.67 g cm⁻³ (InO-250) to 6.19 g cm⁻³ (InO-400), while the thickness decreased from 14.12 nm (InO-250) to 11.43 nm (InO-400) by increasing the annealing temperature. The film thickness, density, and surface roughness of the InO_x and AlO_x films are summarized in

Table 1. The film thickness, density, and surface roughness of the InO_x and AlO_x films.

Samples	Density (g/cm−3)	Thickness (nm)	Roughness (nm)
InO-250	5.66693	14.1193	0.7452
InO-400	6.18673	11.4268	0.7080
AlO-250	2.71072	13.3954	0.7961
AlO-400	2.65632	13.9451	0.6466

. These changes are consistent with densification during annealing and align with TEM and FFT evidence of crystallization at 400 °C. By contrast, AlO_x exhibited negligible changes in density and thickness between 250 °C and 400 °C, supporting the conclusion that annealing strongly affects InO_x crystallinity and densification, while its impact on AlO_x is comparatively minor within this temperature range.

3.3. Electrical Characteristics of InO_x/AlO_x Heterostructure JL TFTs

To correlate structural and chemical evolution with device operation, the electrical characteristics of the three JL TFT types were evaluated. Figure 4a–c present the output characteristics of InO-250/AlO-250, InO-400/AlO-250, and InO-400/AlO-400 JL TFTs, respectively. For these measurements, V_G was varied from 0 to 30 V in 5 V intervals, and V_D was swept from 0 to 30 V at a fixed V_G. All devices exhibited well-defined linear and saturation regions, which confirms proper channel formation. I_D increased monotonically with annealing temperature, consistent with enhanced charge transport resulting from denser, crystallized InO_x and AlO_x films with fewer traps.

Figure 4d–f show the transfer characteristics measured by sweeping V_G from −20 to +30 V at fixed V_D values of 1 V and 30 V. All devices exhibited low off currents and gate leakage currents on the order of 10⁻¹²–10⁻¹⁰ A, which is attributed to effective patterning and isolation of the active region [28]. Figure 4g–i summarize the extracted parameters. The V_T values of InO-250/AlO-250, InO-400/AlO-250, and InO-400/AlO-400 were 2.95 ± 0.89 V, 1.07 ± 0.57 V, and 1.82 ± 0.40 V, respectively (Figure 4g). The largest V_T observed in InO-250/AlO-250 is attributed to the nearly amorphous, poorly conductive InO_x channels containing deep defects [29]. In contrast, the lowest V_T in InO-400/AlO-250 is plausibly linked to the higher electron density of crystallized InO_x combined with hydrogen-related states remaining in low-temperature AlO_x and insufficient suppression of V_O in InO_x by AlO_x diffusion. Annealing AlO_x at 400 °C mitigates –OH–related defects and appropriately reduces electron density, which produces a positive V_T shift and a more stable turn-on even with the same InO-400 channel.

The SS values were 0.48 ± 0.07 V dec⁻¹ (InO-250/AlO-250), 0.62 ± 0.13 V dec⁻¹ (InO-400/AlO-250), and 0.50 ± 0.07 V dec⁻¹ (InO-400/AlO-400) (Figure 4h). SS in JL TFTs reflects the combined influence of interface/bulk traps and the depletion capacitance (C_dep). Although InO-250/AlO-250 exhibits a small SS, thin film analysis does not necessarily indicate a low trap density. Instead, the lower apparent SS likely arises from reduced electron density, which allows for efficient depletion (smaller C_dep). By contrast, InO-400/AlO-250 shows the largest SS, consistent with the combined effects of higher channel electron density (larger C_dep) and residual –OH–related traps in AlO-250. The InO-400/AlO-400 device achieves a low SS by combining a crystalline, adequately doped InO_x channel with a trap-suppressed AlO_x CL. The SS of conventional solution-processed oxide TFTs was at the values of 0.36 to 4.87, and the SS of the junctionless device proposed in this study was at a comparable value [29,30,31].

The μ_SAT values were 0.50 ± 0.14, 0.79 ± 0.14, and 1.57 ± 0.37 cm² V⁻¹ s⁻¹ for InO-250/AlO-250, InO-400/AlO-250, and InO-400/AlO-400 JL TFTs, respectively (Figure 4i). Crystallization and reduced structural disorder from densification of InO_x at 400 °C contributed to the improvement in μ_SAT.

In addition, the suppression of interface scattering and trapping through annealing of AlO_x at 400 °C further enhanced μ_SAT, as reflected in the trends across the three devices. Consequently, the InO-400/AlO-400 device exhibited the highest μ_SAT.

3.4. Contact and Channel Resistance of InO_x/AlO_x Heterostructure JL TFTs

The TLM was used to separate the contact and channel contributions. Figure 5a–c show the width-normalized total resistance (R_Total·W) as a function of L_ch, for InO-250/AlO-250, InO-400/AlO-250, and InO-400/AlO-400 JL TFTs, respectively. Transfer curves were measured in the linear region (V_D = 1 V) for devices with variable channel lengths on the same wafer. The R_Total·W–L_ch plots were highly linear under all conditions. The intercept yields the R_C·W, and the slope yields R_SH. As expected, both R_C·W and R_SH decrease with increasing gate overdrive voltage (V_OV) = V_G − V_T, reflecting the simultaneous mitigation of the metal/semiconductor injection barrier and carrier scattering as the accumulated charge increases.

Among the three types of devices, InO-250/AlO-250 exhibited the largest R_C·W and R_SH at V_OV (Figure 5d,e). This is attributed to the amorphous, low-density InO_x containing abundant –OH defects, which degrade the channel conduction and simultaneously increase the resistance of L_offset. These results are consistent with TEM, XPS, and XRR findings. In InO-400/AlO-250, both resistances decreased significantly at 400 °C because crystallization and densification of InO_x enhanced injection and bulk transport. However, R_SH remained higher than in InO-400/AlO-400, which suggests that residual –OH-related defects in AlO-250 still induced scattering and trapping near the channel. InO-400/AlO-400 devices exhibited the lowest R_SH across the entire bias range, and R_C·W were comparable to (or lower than) those of InO-400/AlO-250, indicating that both channel and contact were optimized simultaneously. These TLM results are consistent with the I-V characteristics in Figure 4. While the high R_C·W and R_SH in InO-250/AlO-250 led to low μ_SAT, InO-400/AlO-400 achieved the highest μ_SAT by reducing both R_C·W and R_SH and suppressing interface traps to maintain a low surface potential.

3.5. Positive Bias Stability of InO_x/AlO_x Heterostructure JL TFTs

Bias reliability is a critical performance metric for practical applications. We therefore performed PBS tests at a stress overdrive voltage (V_STR) of 20 V. Figure 6a–c show the transfer curve evolution with stress time for InO-250/AlO-250, InO-400/AlO-250, and InO-400/AlO-400, respectively, and Figure 6d–f summarize the corresponding time dependence of ΔV_T. The V_T of the InO-250/AlO-250 JL TFT gradually shifted in the positive direction, reaching a large ΔV_T = 6.22 V. This is attributed to the effective electron trapping caused by the high trap densities of the InO_x and AlO_x thin films. By contrast, the InO-400/AlO-250 and InO-400/AlO-400 JL TFTs exhibited much smaller final ΔV_T values of 1.78 V and 1.70 V, respectively, owing to defect reduction by thermal annealing.

A notable feature in Figure 6e is the non-monotonic ΔV_T observed for InO-400/AlO-250. The ΔV_T initially shifted negatively (t ≤ 100 s) and then reversed to a positive shift, ultimately converging to 1.78 V. This sign reversal points to the role of low-temperature AlO_x. Consistent with the XPS results, AlO-250 retained a higher M–OH fraction than AlO-400, which can supply hydrogen-related species. Under positive gate bias, H⁺ can drift toward the interface/channel or be injected into InO_x, transiently increasing interfacial positive charge or forming shallow hydrogen-related donors. This process produces the initial negative ΔV_T. As stress continues, electron trapping at deeper states becomes dominant, which drives ΔV_T back to positive values. In InO-400/AlO-400 JL TFTs, –OH species were effectively removed, so the H⁺ contribution was minimal. The initial negative component was therefore absent, and the overall ΔV_T remained small. Thus, the non-monotonic behavior in Figure 6e serves as a sensitive indicator of hydrogen-related defects in low-temperature AlO_x and quantitatively underscores the importance of high-temperature AlO_x annealing to ensure PBS stability.

4. Conclusions

A systematic study of InO_x/AlO_x JL TFTs fabricated via a solution process was performed to clarify the relationship between processing conditions, film properties, and device performance, which enables device optimization. Independently varying the annealing temperature in the InO_x/AlO_x heterostructure revealed that high-temperature treatment at 400 °C crystallized and densified InO_x, while suppressing –OH-related interface traps in AlO-400 without altering its amorphous nature. This temperature-dependent understanding of film properties enabled simultaneous optimization of channel transport and contact characteristics. Consequently, InO-400/AlO-400 devices were realized with an optimal configuration. This device demonstrated the following performance parameters: V_T = 1.82 ± 0.40 V, SS = 0.50 ± 0.07 V dec⁻¹, μ_SAT = 1.57 ± 0.37 cm² V⁻¹ s⁻¹, including the smallest PBS mobility (ΔV_T = 1.70 V), and the lowest R_C·W and R_SH under TLM. By contrast, InO-400/AlO-250 exhibited large SS, relatively low μ_SAT, and non-monotonic ΔV_T under PBS due to –OH-related defects in low-temperature AlO_x, an instability that was resolved by annealing AlO_x at 400 °C. These results demonstrate that capping-induced carrier modulation and interface trap control are the key determinants of device performance and stability.