Monolayer TiAlTe3: A Perfect Room-Temperature Valleytronic Semiconductor
Abstract
:1. Introduction
2. Computational Details
3. Results
4. Conclusions
Supplementary Materials
Author Contributions
Funding
Institutional Review Board Statement
Informed Consent Statement
Data Availability Statement
Conflicts of Interest
References
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Jia, K.; Zhang, C.-W.; Wang, Z.-R.; Wang, P.-J. Monolayer TiAlTe3: A Perfect Room-Temperature Valleytronic Semiconductor. Materials 2025, 18, 2396. https://doi.org/10.3390/ma18102396
Jia K, Zhang C-W, Wang Z-R, Wang P-J. Monolayer TiAlTe3: A Perfect Room-Temperature Valleytronic Semiconductor. Materials. 2025; 18(10):2396. https://doi.org/10.3390/ma18102396
Chicago/Turabian StyleJia, Kang, Chang-Wen Zhang, Zi-Ran Wang, and Pei-Ji Wang. 2025. "Monolayer TiAlTe3: A Perfect Room-Temperature Valleytronic Semiconductor" Materials 18, no. 10: 2396. https://doi.org/10.3390/ma18102396
APA StyleJia, K., Zhang, C.-W., Wang, Z.-R., & Wang, P.-J. (2025). Monolayer TiAlTe3: A Perfect Room-Temperature Valleytronic Semiconductor. Materials, 18(10), 2396. https://doi.org/10.3390/ma18102396