# Development of a Novel Bidirectional DC/DC Converter Topology with High Voltage Conversion Ratio for Electric Vehicles and DC-Microgrids

## Abstract

**:**

## 1. Introduction

## 2. Proposed BDC Topology and Operation Principles

_{H}and V

_{L}denote the high-side voltage and low-side voltage, respectively. L

_{1}and L

_{2}represent two-phase inductors of IBCPC. C

_{B}denotes the charge-pump capacitor. C

_{H}and C

_{L}are the high-side and low-side capacitors, respectively. The symbols, Q

_{1}~Q

_{4}, and S

_{1}~S

_{4}, respectively, are the power switches of the IBCPC and ULC.

_{a}, L

_{b}) is required, it can substantially boost the power density of the low-side stage. Furthermore, by leaving the voltage regulation to another high-side stage, the studied BDC for the low-side stage with fixed 2:1 under charge state operation or 1:2 conversion ratio under discharge state operation, can achieve high efficiency with a relatively low-side voltage in whole load range. As to the high-side stage, the structure of two-phase IBCPC is similar to a conventional buck-boost converter except two active switches in series and a charge-pump capacitor (C

_{B}) employed in the power path. The circuit structure is simple and it can reach the high voltage conversion ratio with a reasonable duty cycle. Therefore, it can reduce the conduction loss of the switch, to further upgrade the efficiency of the whole bidirectional converter.

_{H}to V

_{L}, it operates in charge state (i.e., buck operation); Q

_{1}and Q

_{2}are controlled to regulate the output. Thus, Q

_{1}and Q

_{2}are defined as the active switches, while Q

_{3}and Q

_{4}are the passive switches. The passive switches work as synchronous rectification (SR). When the energy flows from V

_{L}to V

_{H}, it operates in discharge state (i.e., boost operation); Q

_{3}and Q

_{4}are controlled to regulate the output. Thus, Q

_{3}and Q

_{4}are defined as the active switches, while Q

_{1}and Q

_{2}are the passive switches.

_{H}and C

_{L}is large enough to be considered as a voltage source; (3) the middle-link voltage V

_{M}= V

_{M}

_{1}+ V

_{M}

_{2}is treated as a pure dc and considered as constant; (4) the two inductor L

_{1}and L

_{2}have the same inductor L

_{s}; (5) all power semiconductors are ideal; (6) the charge-pump voltage V

_{CB}is treated as a pure dc and considered as constant.

#### 2.1. Charge State Operation

_{1}and Q

_{2}are driven with the phase shift angle of 180°; Q

_{3}and Q

_{4}work as synchronous rectification. In charge state, when S

_{1}, S

_{3}are turned on and S

_{2}, S

_{4}are turned off; or else S

_{2}, S

_{4}are turned on and S

_{1}, S

_{3}are turned off. The low-side voltage V

_{L}is half the middle-link voltage V

_{M}, i.e., V

_{L}= 0.5V

_{M}. In this state, one can see that, when duty ratio of Q

_{1}and Q

_{2}are smaller than 50%, there are four operating modes according to the on/off status of the active switches.

#### 2.1.1. Mode 1 [t_{0} < t ≤ t_{1}]

_{d}T

_{sw}, in this mode, switches Q

_{1}, Q

_{3}turned on and switches Q

_{2}, Q

_{4}are all off. The voltage across L

_{1}is the negative middle-link voltage, and hence i

_{L}

_{1}decreases linearly from the initial value. Also, the voltage across L

_{2}is the difference of the high-side voltage V

_{H}, the charge-pump voltage V

_{CB}, and the middle-link voltage V

_{M}, and its level is positive. The voltages across inductances L

_{1}and L

_{2}can be represented as:

#### 2.1.2. Mode 2 [t_{1} < t ≤ t_{2}]

_{d})T

_{sw}, switches Q

_{3}, Q

_{4}are turned on and switches Q

_{1}, Q

_{2}are all off. Both voltages across inductors L

_{1}and L

_{2}are the negative middle-link voltage V

_{M}, hence i

_{L}

_{1}and i

_{L}

_{2}decrease linearly. The voltages across inductances L

_{1}and L

_{2}can be represented as:

#### 2.1.3. Mode 3 [t_{2} < t ≤ t_{3}]

_{d}T

_{sw}, switches Q

_{2}, Q

_{4}are turned on and switches Q

_{1}and Q

_{3}are all off. The voltage across L

_{1}is the difference between the charge-pump voltage V

_{CB}with the middle-link voltage V

_{M}, and L

_{2}is keeping the negative middle-link voltage, the voltages across inductances L

_{1}and L

_{2}can be represented as follows:

#### 2.1.4. Mode 4 [t_{3} < t ≤ t_{4}]

_{d})T

_{sw}. Switches Q

_{3}, Q

_{4}are turned on and switches Q

_{1}, Q

_{2}are all off, and its operation is the same with that of Mode 2.

#### 2.2. Discharge State Operation

_{3}, Q

_{4}are driven with the phase shift angle of 180°; Q

_{1}, Q

_{2}are used for the synchronous rectifier. In discharge state, when S

_{1}, S

_{3}are turned on and S

_{2}, S

_{4}are turned off; or else S

_{2}, S

_{4}are turned on and S

_{1}, S

_{3}are turned off. The low voltage V

_{L}will charge the C

_{M}

_{1}and C

_{M}

_{2}to make V

_{M}

_{1}and V

_{M}

_{2}equal to V

_{L}, the middle-link voltage V

_{M}is then twice the low-side voltage V

_{L}, i.e., V

_{M}= 2V

_{L}.

#### 2.2.1. Mode 1 [t_{0} < t ≤ t_{1}]

_{b}− 0.5)T

_{sw}, switches Q

_{3}and Q

_{4}are turned on; switches Q

_{1}and Q

_{2}are all off. For the high-side stage, the middle-link voltage V

_{M}stays between inductance L

_{1}and L

_{2}, making the inductance current increase linearly, and begins to deposit energy. The voltages across inductances L

_{1}and L

_{2}can be represented as:

#### 2.2.2. Mode 2 [t_{1} < t ≤ t_{2}]

_{b})T

_{sw}. Switch Q

_{1}, Q

_{3}remains conducting and Q

_{2}, Q

_{4}are turned off. The voltages across inductances L

_{1}and L

_{2}can be represented as:

#### 2.2.3. Mode 3 [t_{2} < t ≤ t_{3}]

#### 2.2.4. Mode 4 [t_{3} < t ≤ t_{4}]

_{b})T

_{sw}. For the low-side stage, switches Q

_{1}, Q

_{3}are turned off and Q

_{2}, Q

_{4}are turned on. The energy stored in inductor L

_{1}is now released energy to charge-pump capacitor C

_{B}for compensating the lost charges in previous modes. The output power is supplied from the capacitor C

_{H}. The voltages across inductances L

_{1}and L

_{2}can be represented as:

## 3. Steady-State Analysis

#### 3.1. Voltage Conversion Ratio

_{H}is the input and V

_{L}is the output. According to Equations (1)–(5) and based on the voltage-second balance principle in L

_{1}and L

_{2}, the voltage conversion ratio M

_{d}in charge state can be derived as:

_{d}is the duty cycle of the active switches Q

_{1}and Q

_{2}. As can be seen, the voltage conversion ratio in charge state is one-fourth of that of the conventional buck converter. Similarly, in discharge state, V

_{L}is the input and V

_{H}is the output. According to Equations (6)–(10) and based on the voltage-second balance principle in L

_{1}and L

_{2}, the voltage conversion ratio M

_{b}in discharge state can be derived as:

_{b}is the duty cycle of the active switches Q

_{3}and Q

_{4}. As can be seen, the voltage conversion ratio in discharge state is four times of that of the conventional boost converter.

#### 3.2. Voltage Stress of the Switches

_{1}~S

_{4}of ULC is equal to the low-side input voltage V

_{L}, as follows:

_{1}~Q

_{4}can be obtained directly as:

#### 3.3. Inductor Current Ripple

#### 3.4. Boundary Conduction Mode

_{L,B}can be defined as:

_{Ld,B}and τ

_{Lb,B}in charge and discharge states. The BDC in charge state operates in CCM when τ

_{Ld}is designed to be higher than the boundary curve of τ

_{Ld,B}. The studied BDC in discharge state operates in discontinuous conduction mode (DCM) when τ

_{Lb}is selected to be lower than the boundary curve of τ

_{Lb,B}.

_{out}is the output power.

#### 3.5. Selection Considerations of Charge-Pump Capacitor

_{B}can be obtained as follows:

_{B}, the voltage ripple can be reduced by increasing the switching frequency. The root mean square (RMS) value of the current through the charge-pump capacitor is

#### 3.6. Summaries of Component Stress and Loss

_{d}< 0.5 and D

_{b}> 0.5 for charge and discharge modes, respectively. The results of component stress can be summarized as in Table 1. Furthermore, equations for loss analysis can be summarized as in Table 2, where Q

_{g}represents the MOSFET total gate charge; t

_{r}is rise time, it’s the period after the v

_{GS}reaches threshold voltage v

_{GS}

_{(th)}to complete the transient MOSFET gate charge; t

_{f}is fall time, it’s the time where the gate voltage reaches the threshold voltage v

_{GS}

_{(th)}after MOSFET turn-off delay time [26].

## 4. Simulation and Experimental Results

- (1)
- high-side voltage V
_{H}: 385 V; - (2)
- low-side voltage V
_{L}: 48 V; - (3)
- rated power P
_{o}: 500 W; - (4)
- switching frequency f
_{sw}: 20 kHz; - (5)
- capacitors C
_{H}= C_{L}= 33 μF, C_{M}_{1}= C_{M}_{2}= 33 μF, C_{B}= 10 μF; (ESR of C_{H}, R_{CH}= 0.064 Ω; ESR of C_{L}, R_{CL}= 0.062 Ω, ESR of C_{M}_{1}, R_{CM}_{1}= 0.16 Ω; ESR of C_{M}_{2}, R_{CM}_{2}= 0.16 Ω; ESR of C_{B}, R_{CB}= 0.062 Ω); - (6)
- inductors L
_{1}= L_{2}= L_{s}= 800 μH; L_{a}= L_{b}= 1.5 μH (IHLP-6767GZ-A1); (ESR of L_{1}, R_{L}_{1}= 0.18 Ω, ESR of L_{2}, R_{L}_{2}= 0.18 Ω, ESR of L_{a}, R_{La}= 13.6 mΩ; ESR of L_{b}, R_{Lb}= 13.6 mΩ); - (7)
- power switches S
_{1}~S_{4}: IXFH160N15T2, 150 V/160 A/R_{DS}_{(on)}= 9 mΩ, TO-247AC; Q_{1}, Q_{3}, Q_{4}: FDA59N30, 300 V/59 A/R_{DS}_{(on)}= 56 mΩ, TO-247AC; Q_{2}: W25NM60, 650 V/21 A/R_{DS}_{(on)}= 160 mΩ, TO-247AC.

_{La}, i

_{Lb}), gate signals of active switches (Q

_{1}, Q

_{2}) and two-phase inductor currents (i

_{L}

_{1}, i

_{L}

_{2}) in charge state at full load condition. Also the corresponding experimental results are shown in Figure 16. One can observe that both results are in very close agreement as well. From Figure 15a and Figure 16a, as can be seen, the low-side filter (L

_{a}, L

_{b}) can effectively limit the switching current spike and shape the current to a nearly rectified sinusoidal waveform. Also, from the figures it is observed that by interleaved controlling the duty cycles of 0.48 for the switches (Q

_{1}, Q

_{2}), the two-phase currents (i

_{L}

_{1}, i

_{L}

_{2}) are in complementary relation and in CCM.

_{CB}), middle-link voltage (V

_{M}), middle-link capacitor voltages (V

_{M}

_{1}, V

_{M}

_{2}), low-side voltage (V

_{L}), and low-side switch voltages (V

_{S}

_{1}, V

_{S}

_{2}, V

_{S}

_{3}, V

_{S}

_{4}). From Figure 17 and Figure 18, with the ULC of studied BDC, the low-voltage side (V

_{L}) is well regulated at 48 V. The middle-link voltage is 96 V, it does quite reach twice of the regulated low-side voltage (V

_{L}) of 48 V. The charge-pump capacitor voltage (V

_{CB}) of 192 V can be achieved easily and indeed can share one-half of the high-side voltage to reduce the voltage stress of active switches. It is observed that the steady-state voltage stresses of low-side active switches (V

_{S}

_{1}, V

_{S}

_{2}, V

_{S}

_{3}, V

_{S}

_{4}) are only about 48 V, which means that lower on-resistance MOSFETs can be used to achieve the improved conversion efficiency. Also, both the simulated results are in close agreement with the corresponding experimental results.

_{3}, Q

_{4}, the two-phase inductor currents (i

_{L}

_{1}, i

_{L}

_{2}) and the switch voltages of (V

_{Q}

_{3}, V

_{Q}

_{4}) in charge state at full load condition. The corresponding experimental results are also shown in Figure 20. One can observe that both results are in very close agreement as well. From the figures it is observed that by interleaved controlling the duty cycles of 0.52 for the switches (Q

_{3}, Q

_{4}), the two-phase currents (i

_{L}

_{1}, i

_{L}

_{2}) are in complementary relation and in CCM. Also, from Figure 19b and Figure 20b, the charge-pump capacitor voltage (V

_{CB}) is about 192.5 V, it can clamp the switch voltages of active switches (Q

_{3}, Q

_{4}) to be nearly one-half of the regulated high-side voltage V

_{H}of 385 V.

## 5. Conclusions

## Acknowledgments

## Conflicts of Interest

## References

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**Figure 1.**A typical dc-microgrid structure [4].

**Figure 2.**Circuit structure of the bidirectional double-boost cascaded topology [17].

**Figure 7.**Equivalent circuits of the modes during different intervals in charge state: (

**a**) Mode 1; (

**b**) Mode 2, Mode 4; (

**c**) Mode 3.

**Figure 10.**Equivalent circuits of the modes during different intervals in discharge state: (

**a**) Mode 1, Mode 3; (

**b**) Mode 2; (

**c**) Mode 4.

**Figure 15.**Simulated waveforms of the studied BDC in charge state at full load: (

**a**) low-side filter currents i

_{La}, i

_{Lb}; (

**b**) gate signals of Q

_{1}, Q

_{2}and two-phase inductor currents i

_{L}

_{1}, i

_{L}

_{2}.

**Figure 16.**Measured waveforms of the studied BDC in charge state at full load: (

**a**) low-side filter currents i

_{La}, i

_{Lb}; (

**b**) gate signals of Q

_{1}, Q

_{2}and two-phase inductor currents i

_{L}

_{1}, i

_{L}

_{2}.

**Figure 17.**Simulated waveforms of the studied BDC in charge state at full load: (

**a**) charge-pump capacitor voltage V

_{CB}, middle-link voltage V

_{M}; (

**b**) middle-link capacitor voltages V

_{M}

_{1}, V

_{M}

_{2}, and low-side voltage V

_{L}; (

**c**) switch voltages of S

_{1}, S

_{2}, S

_{3}, S

_{4}.

**Figure 18.**Measured waveforms of the studied BDC in charge state at full load: (

**a**) charge-pump capacitor voltage V

_{CB}and middle-link voltage V

_{M}; (

**b**) middle-link capacitor voltages V

_{M}

_{1}, V

_{M}

_{2}, and low-side voltage V

_{L}; (

**c**) switch voltages of S

_{1}, S

_{2}, S

_{3}, S

_{4}.

**Figure 19.**Simulated waveforms of the studied BDC in discharge state at full load: (

**a**) gate signals of Q

_{3}, Q

_{4}, two-phase inductor currents i

_{L}

_{1}, i

_{L}

_{2}; (

**b**) switch voltages of Q

_{3}, Q

_{4}; (

**c**) charge-pump capacitor voltage V

_{CB}and high-side voltage V

_{H}.

**Figure 20.**Measured waveforms of the studied BDC in discharge state at full load: (

**a**) gate signals of Q

_{3}, Q

_{4}, two-phase inductor currents i

_{L}

_{1}, i

_{L}

_{2}; (

**b**) switches voltages of Q

_{3}, Q

_{4}; (

**c**) charge-pump capacitor voltage V

_{CB}and high-side voltage V

_{H}.

**Figure 21.**Measured conversion efficiency of the studied BDC for low-side voltage V

_{L}= 48 V and high-side voltage V

_{H}= 385 V under different loads.

**Figure 22.**Calculated losses breakdown diagrams at rated load condition: (

**a**) in charge state; (

**b**) in discharge state.

Items | Charge State | Discharge State |
---|---|---|

Voltage Stress of Q_{1}, Q_{3,} Q_{4} (v_{Q}_{1}, v_{Q}_{3}, v_{Q}_{4}) | $0.5{V}_{H}$ | $0.5{V}_{H}$ |

Voltage Stress of Q_{2} (v_{Q}_{2}) | ${V}_{H}$ | ${V}_{H}$ |

Voltage Stress of S_{1}~S_{4} (v_{S}_{1}~v_{S}_{4}) | ${V}_{L}$ | ${V}_{L}$ |

RMS Current Stress of Q_{1} (i_{Q}_{1}) | ${I}_{L2\left(\text{RMS}\right)}\sqrt{{D}_{d}}$ | ${I}_{L2\left(\text{RMS}\right)}\sqrt{1-{D}_{b}}$ |

RMS Current Stress of Q_{2} (i_{Q}_{2}) | ${I}_{L1\left(\text{RMS}\right)}\sqrt{{D}_{d}}$ | ${I}_{L1\left(\text{RMS}\right)}\sqrt{1-{D}_{b}}$ |

RMS Current Stress of Q_{3} (i_{Q}_{3}) | ${I}_{L1\left(\text{RMS}\right)}\sqrt{1-{D}_{d}}$ | ${I}_{L1\left(\text{RMS}\right)}\sqrt{{D}_{b}}$ |

RMS Current Stress of Q_{4} (i_{Q}_{4}) | $\sqrt{\begin{array}{l}{({I}_{Lt\left(\text{RMS}\right)})}^{2}({D}_{d})+\\ {({I}_{L2\left(\text{RMS}\right)})}^{2}(0.5-{D}_{d})\end{array}}$ | $\sqrt{\begin{array}{l}{({I}_{Lt\left(\text{RMS}\right)})}^{2}(1-{D}_{b})+\\ {({I}_{L2\left(\text{RMS}\right)})}^{2}({D}_{b}-0.5)\end{array}}$ |

RMS Current Stress of S_{1}~S_{4} (i_{S}_{1}~i_{S}_{4}) | ${I}_{Lt(RMS)}/\sqrt{2}$ | ${I}_{Lt(RMS)}/\sqrt{2}$ |

RMS Current Stress of L_{1} (i_{L}_{1}) | $\sqrt{{I}_{L1}{}^{2}+(\frac{\Delta {i}_{L1}}{2\sqrt{3}})}$ | $\sqrt{{I}_{L1}{}^{2}+(\frac{\Delta {i}_{L1}}{2\sqrt{3}})}$ |

RMS Current Stress of L_{2} (i_{L}_{2}) | $\sqrt{{I}_{L2}{}^{2}+(\frac{\Delta {i}_{L2}}{2\sqrt{3}})}$ | $\sqrt{{I}_{L2}{}^{2}+(\frac{\Delta {i}_{L2}}{2\sqrt{3}})}$ |

RMS Current Stress of L_{a} (i_{L}_{a}) | $\sqrt{{I}_{La}{}^{2}+(\frac{\Delta {i}_{La}}{2\sqrt{3}})}$ | $\sqrt{{I}_{La}{}^{2}+(\frac{\Delta {i}_{La}}{2\sqrt{3}})}$ |

RMS Current Stress of L_{b} (i_{L}_{b}) | $\sqrt{{I}_{Lb}{}^{2}+(\frac{\Delta {i}_{Lb}}{2\sqrt{3}})}$ | $\sqrt{{I}_{Lb}{}^{2}+(\frac{\Delta {i}_{Lb}}{2\sqrt{3}})}$ |

RMS Current Stress of C_{B} (i_{CB}) | $\left({I}_{L}\sqrt{2{D}_{d}}\right)/4$ | $\left({I}_{L}\sqrt{2(1-{D}_{b})}\right)/4$ |

RMS Current Stress of C_{H} (i_{CH}) | $\sqrt{{({I}_{Q1(RMS)})}^{2}-{I}_{H}}$ | $\sqrt{{({I}_{Q1(RMS)})}^{2}-{I}_{H}}$ |

RMS Current Stress of C_{L} (i_{CL}) | $\sqrt{{I}_{L}{}^{2}-\frac{4\Delta {i}_{La}{I}_{L}}{\pi}+\frac{4\Delta {i}_{La}{}^{2}}{{\pi}^{2}}+\frac{\Delta {i}_{La}{}^{2}}{2}}$ | $\sqrt{{I}_{L}{}^{2}-\frac{4\Delta {i}_{La}{I}_{L}}{\pi}+\frac{4\Delta {i}_{La}{}^{2}}{{\pi}^{2}}+\frac{\Delta {i}_{La}{}^{2}}{2}}$ |

RMS Current Stress of C_{M}_{1}, C_{M}_{2} (i_{CM}_{1}, i_{CM}_{2}) | $\sqrt{{I}_{Lt(RMS)}{}^{2}-{I}_{S1(RMS)}{}^{2}}$ | $\sqrt{{I}_{Lt(RMS)}{}^{2}-{I}_{S2(RMS)}{}^{2}}$ |

Items | Equations |
---|---|

Conduction loss of Q_{1}~Q_{4} | ${R}_{DS\left(\mathrm{Q}1\right)}\times {[{i}_{Q1(RMS)}]}^{2}$; ${R}_{DS\left(\mathrm{Q}2\right)}\times {[{i}_{Q2(RMS)}]}^{2}$; ${R}_{DS(Q3)}\times {[{i}_{Q3(RMS)}]}^{2}$; ${R}_{DS(Q4)}\times {[{i}_{Q4(RMS)}]}^{2}$ |

Conduction loss of S_{1}~S_{4} | ${R}_{DS(S1)}\times {[{i}_{S1(RMS)}]}^{2}$; ${R}_{DS\left(\mathrm{S}2\right)}\times {[{i}_{S2(RMS)}]}^{2}$; ${R}_{DS\left(\mathrm{S}3\right)}\times {[{i}_{S3(RMS)}]}^{2}$; ${R}_{DS\left(\mathrm{S}4\right)}\times {[{i}_{S4(RMS)}]}^{2}$ |

Switching loss of Q_{1} | $({V}_{DS(Q1)}\times {i}_{Q1(ON)}\times {T}_{r})/6{T}_{sw}$; $({V}_{DS(Q1)}\times {i}_{Q1(OFF)}\times {T}_{f})/6{T}_{sw}$ |

Switching loss of Q_{2} | $({V}_{DS(Q2)}\times {i}_{Q2(ON)}\times {T}_{r})/6{T}_{sw}$; $({V}_{DS(Q2)}\times {i}_{Q2(OFF)}\times {T}_{f})/6{T}_{sw}$ |

Switching loss of Q_{3} | $({V}_{DS(Q3)}\times {i}_{Q3(ON)}\times {T}_{r})/6{T}_{sw}$; $({V}_{DS(Q3)}\times {i}_{Q3(OFF)}\times {T}_{f})/6{T}_{sw}$ |

Switching loss of Q_{4} | $({V}_{DS(Q4)}\times {i}_{Q4(ON)}\times {T}_{r})/6{T}_{sw}$; $({V}_{DS(Q4)}\times {i}_{Q4(OFF)}\times {T}_{f})/6{T}_{sw}$ |

Switching loss of S_{1} | $({V}_{DS(S1)}\times {i}_{S1(ON)}\times {T}_{r})/6{T}_{sw}$; $({V}_{DS(S1)}\times {i}_{S1(OFF)}\times {T}_{f})/6{T}_{sw}$ |

Switching loss of S_{2} | $({V}_{DS(S2)}\times {i}_{S2(ON)}\times {T}_{r})/6T$; $({V}_{DS(S2)}\times {i}_{S2(OFF)}\times {T}_{f})/6T$ |

Switching loss of S_{3} | $({V}_{DS(S3)}\times {i}_{S3(ON)}\times {T}_{r})/6{T}_{sw}$; $({V}_{DS(S3)}\times {i}_{S3(OFF)}\times {T}_{f})/6{T}_{sw}$ |

Switching loss of S_{4} | $({V}_{DS(S4)}\times {i}_{S4(ON)}\times {T}_{r})/6{T}_{sw}$; $({V}_{DS(S4)}\times {i}_{S4(OFF)}\times {T}_{f})/6{T}_{sw}$ |

Conduction loss of L_{1}~L_{2} | ${R}_{L1}\times {[{i}_{L1(RMS)}]}^{2}$; ${R}_{L2}\times {[{i}_{L2(RMS)}]}^{2}$ |

Conduction loss of L_{a}~L_{b} | ${R}_{La}\times {[{i}_{La(RMS)}]}^{2}$; ${R}_{Lb}\times {[{i}_{Lb(RMS)}]}^{2}$ |

Conduction loss of C_{B}, C_{H,} C_{L} | ${R}_{CB}\times {[{i}_{CB(RMS)}]}^{2}$; ${R}_{CH}\times {[{i}_{CH(RMS)}]}^{2}$; ${R}_{CL}\times {[{i}_{CL(RMS)}]}^{2}$ |

Conduction loss of C_{M}_{1}~ C_{M}_{2} | ${R}_{CM1}\times {[{i}_{CM1(RMS)}]}^{2}$; ${R}_{CM2}\times {[{i}_{CM2(RMS)}]}^{2}$ |

Gate driving loss of Q_{1}~Q_{4} | ${Q}_{g(Q1~Q4)}\times {V}_{GS(Q1~Q4)}\times {f}_{sw}$ |

Gate driving loss of S_{1}~S_{4} | ${Q}_{g(S1~S4)}\times {V}_{GS(S1~S4)}\times {f}_{sw}$ |

Items | Charge State | Discharge State |
---|---|---|

Calculated Results | Calculated Results | |

Conduction loss of Q_{1} | 0.62 W | 0.62 W |

Conduction loss of Q_{2} | 1.58 W | 1.58 W |

Conduction loss of Q_{3} | 0.67 W | 0.67 W |

Conduction loss of Q_{4} | 1.29 W | 1.29 W |

Conduction loss of S_{1} | 0.58 W | 0.58 W |

Conduction loss of S_{2} | 0.58 W | 0.58 W |

Conduction loss of S_{3} | 0.58 W | 0.58 W |

Conduction loss of S_{4} | 0.58 W | 0.58 W |

Switching loss of Q_{1} (turn on/off transition) | on: 0.09 W; off: 0.52 W | on: 0.10 W; off: 0.72 W |

Switching loss of Q_{2} (turn on/off transition) | on: 0.19 W; off: 1.01 W | on: 0.17 W; off: 0.87 W |

Switching loss of Q_{3} (turn on/off transition) | on: 0.09 W; off: 0.62 W | on: 0.09 W; off: 0.52 W |

Switching loss of Q_{4} (turn on/off transition) | on: 0.10 W; off: 0.69 W | on: 0.09 W; off: 0.54 W |

Switching loss of S_{1} (turn on/off transition) | on: 0.07 W; off: 0.44 W | on: 0.05 W; off: 0.55 W |

Switching loss of S_{2} (turn on/off transition) | on: 0.05 W; off: 0.60 W | on: 0.06 W; off: 0.35 W |

Switching loss of S_{3} (turn on/off transition) | on: 0.05 W; off: 0.47 W | on: 0.05 W; off: 0.29 W |

Switching loss of S_{4} (turn on/off transition) | on: 0.06 W; off: 0.34 W | on: 0.05 W; off: 0.46 W |

Conduction loss of L_{1} | 4.94 W | 4.94 W |

Conduction loss of L_{2} | 4.94 W | 4.94 W |

Conduction loss of L_{a} | 1.80 W | 1.80 W |

Conduction loss of L_{b} | 1.80 W | 1.80 W |

Conduction loss of C_{B} | 1.61 W | 1.61 W |

Conduction loss of C_{H} | 1.67 W | 1.67 W |

Conduction loss of C_{L} | 0.02 W | 0.02 W |

Conduction loss of C_{M}_{1} | 0.01 W | 0.01 W |

Conduction loss of C_{M}_{2} | 0.01 W | 0.01 W |

Gate driving loss of Q_{1}~Q_{4} | 0.02 W | 0.02 W |

Gate driving loss of S_{1}~S_{4} | 0.08 W | 0.08 W |

Total losses | 28.5 W | 28.64 W |

% in rated load condition | 5.70% | 5.73% |

Calculated Efficiency | 94.30% | 94.27% |

Measured Efficiency | 94.29% | 94.25% |

Items | Topology | |||
---|---|---|---|---|

This Work | [17] | [22] | [23] | |

Switching control structure | two-phase | single-phase | single-phase | single-phase |

Output ripple | Low | High | Medium | Medium |

Step-up conversion ratio | 4/(1 − D_{b}) | n/(1 − D_{b}) | 2/(1 − D_{b}) | 1/(1 − D_{b})^{2} |

Step-down conversion ratio | D_{d}/4 | D_{d}/(1 + n − nD_{d}) | D_{d}/2 | (D_{d})^{2} |

High-side voltage | 385 V | 400 V | 200 V | 62.5 V |

Low-side voltage | 48 V | 48 V | 24 V | 10 V |

Realized prototype power rating | 500 W | 200 W | 200 W | 100 W |

Number of main switches | 8 | 4 | 4 | 4 |

Number of storage components | 7 | 5 | 5 | 5 |

Maximum efficiency (charge state) | 96% | 91.6% | 94.8% | 91.5% |

Maximum efficiency (discharge state) | 95% | 94.3% | 94.1% | 92.5% |

© 2016 by the author; licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC-BY) license (http://creativecommons.org/licenses/by/4.0/).

## Share and Cite

**MDPI and ACS Style**

Lai, C.-M.
Development of a Novel Bidirectional DC/DC Converter Topology with High Voltage Conversion Ratio for Electric Vehicles and DC-Microgrids. *Energies* **2016**, *9*, 410.
https://doi.org/10.3390/en9060410

**AMA Style**

Lai C-M.
Development of a Novel Bidirectional DC/DC Converter Topology with High Voltage Conversion Ratio for Electric Vehicles and DC-Microgrids. *Energies*. 2016; 9(6):410.
https://doi.org/10.3390/en9060410

**Chicago/Turabian Style**

Lai, Ching-Ming.
2016. "Development of a Novel Bidirectional DC/DC Converter Topology with High Voltage Conversion Ratio for Electric Vehicles and DC-Microgrids" *Energies* 9, no. 6: 410.
https://doi.org/10.3390/en9060410