Open Access
This article is

- freely available
- re-usable

*Energies*
**2016**,
*9*(11),
871;
doi:10.3390/en9110871

Article

Novel Interleaved Converter with Extra-High Voltage Gain to Process Low-Voltage Renewable-Energy Generation

Department of Electronic Engineering, National Kaohsiung First University of Science and Technology, Kaohsiung 82445, Taiwan

^{*}

Author to whom correspondence should be addressed.

Academic Editor:
Paul Stewart

Received: 28 July 2016 / Accepted: 17 October 2016 / Published: 25 October 2016

## Abstract

**:**

This paper presents a novel interleaved converter (NIC) with extra-high voltage gain to process the power of low-voltage renewable-energy generators such as photovoltaic (PV) panel, wind turbine, and fuel cells. The NIC can boost a low input voltage to a much higher voltage level to inject renewable energy to DC bus for grid applications. Since the NIC has two circuit branches in parallel at frond end to share input current, it is suitable for high power applications. In addition, the NIC is controlled in an interleaving pattern, which has the advantages that the NIC has lower input current ripple, and the frequency of the ripple is twice the switching frequency. Two coupled inductors and two switched capacitors are incorporated to achieve a much higher voltage gain than conventional high step-up converters. The proposed NIC has intrinsic features such as leakage energy totally recycling and low voltage stress on power semiconductor. Thorough theoretical analysis and key parameter design are presented in this paper. A prototype is built for practical measurements to validate the proposed NIC.

Keywords:

photovoltaic (PV) panel; fuel cells; high step-up converter; interleaved converter; low voltage stress## 1. Introduction

Since fossil fuels will be depleted in the next decades, development of green energy power generation systems becomes urgent. Among renewable energy generation systems, photovoltaic (PV), wind turbine, energy storage systems, and fuel cells attract a lot of attention [1,2,3,4]. Nevertheless, low output voltage is their common shortcoming, especially in grid connection or electric vehicle (EV) applications. Therefore, a step-up converter to achieve high voltage gain is required. Conventional boost-type converters, like boost, buck-boost, and flyback, are able to step-up input voltage. However, in order to meet high-voltage gain requirements, they have to operate in heavy-duty ratio or adopt a high turns ratio transformer, which will decrease the conversion efficiency dramatically. Cascading more boost-type converters can avoid the above problem but issues of volume, cost, and efficiency emerge. Therefore, the high step-up DC/DC converter is the current design trend.

High step-up converters can be mainly classified into two categories: single-stage and interleaved structure. Single-stage topology incorporates coupled inductors and/or switched capacitors to complete high voltage gain. Even though its input voltage is boosted, a large magnitude of input current ripple occurs, limiting the converter power rating significantly [5,6,7,8]. The interleaved converter has the ability of suppressing input current ripple by means of adding a parallel current path, which is a better choice for high power applications [9,10,11]. However, the conventional interleaved converters have voltage gain limitation, which confines their applications in grid-tied systems. To overcome the aforementioned disadvantages, various high step-up interleaved converters were proposed in [12,13,14,15,16]; nevertheless, the shortcomings of lower voltage gain, higher voltage stress, and large component count still exist. An interleaved Boost converter combining voltage doubler is introduced in [12], while a coupled inductor is examined in [13]. In order to achieve high voltage gain, the converters in [12,13] have to be operated at heavy-duty ratio or adopt a magnetic transform with high turns ratio, which results in low conversion efficiency or high voltage stress. Even though Lai et al. [14] proposed another high step-up converter, incorporating coupled inductor and switched capacitor, into an interleaved Boost configuration, the converter intrinsically has the demerits of higher voltage stress and sophisticated structure. An interleaved step-up converter with winding-cross-coupled inductors and voltage multiplier cells is presented in [15]. This converter is composed of eight semiconductor devices and two three-winding coupled inductors. That is, a large number of power devices must be used. Tseng et al. [16] utilized the characteristics of forward, flyback, and interleaved converters to boost input voltage, but voltage gain still is limited.

This paper proposes a novel interleaved converter (NIC), which can accomplish a high voltage conversion ratio and is capable of processing low voltage, high power distributed resources. Its power stage is depicted in Figure 1. The proposed NIC mainly includes three parts: one interleaved-boost converter cell and two voltage multipliers. The interleaved-Boost converter cell is in charge of lowering input current ripple, increasing current rating, and primarily stepping input voltage. The two voltage multipliers can further stack up voltage level. The series voltage of the three parts determines the magnitude of output voltage. Since the proposed converter only uses two coupled inductors, three capacitors, four diodes, and two active power switches, it has a lower component count and a simple circuit structure. The advantages of the proposed NIC are summarized as follows:

- (1)
- The NIC can suppress input current ripple.
- (2)
- The energy stored in leakage inductance can be recycled.
- (3)
- The voltage stress of the semiconductor device is low enough so that a power switch with lower on-state resistance and smaller parasitic capacitance can be chosen.
- (4)
- As compared with a conventional interleaved high step-up converter, the proposed NIC can achieve a much higher voltage gain under the same power component count.

## 2. Operation Principle of the Proposed Converter

In Figure 1, L

_{m1}and L_{m2}denote the magnetizing inductances of the coupled inductors T_{1}and T_{2}, respectively. The L_{k1}and L_{k2}represent the primary leakage inductances of T_{1}and T_{2}, in turn, while L_{k3}stands for the total leakage inductance at the secondary windings of both coupled inductors. Turns ratios of primary to secondary of T_{1}and T_{2}are denoted as n_{1}and n_{2}, respectively. C_{1}, C_{2}, and C_{3}are the main capacitors employed in the circuit. It is supposed that the NIC operates in continuous conduction mode (CCM) and the two active switches S_{1}and S_{2}are controlled in interleaved manner. Accordingly, the operation of the NIC can be divided into ten operation modes over one switching cycle. The corresponding equivalents are illustrated in Figure 2, while Figure 3 depicts key waveforms. Analysis of the proposed NIC begins by making these assumptions:- (1)
- All parasitic capacitances and internal resistances are neglected. Moreover, all diodes are ideal.
- (2)
- The voltages across capacitors C
_{1}, C_{2}, C_{3}, and C_{o}are time-invariant. - (3)
- Magnetizing inductances, L
_{m1}and L_{m2}, are much larger than the leakage inductances L_{lk}_{1}, L_{lk2}and L_{lk3}. - (4)
- The switching period is T
_{s}. Both switches are closed for time DT_{s}and open for (1 − D)T_{s}.

**Mode 1 (t**: This mode is the initial mode of the all operation procedures. During this time interval, both active switches S

_{0}–t_{1}) (Figure 2a)_{1}and S

_{2}are closed. Diodes D

_{1}, D

_{3}and D

_{o}are in reverse-bias, but D

_{2}is forward-biased. Input voltage V

_{in}is across the primaries of T

_{1}and T

_{2}directly. Then, the current flowing through S

_{2}starts increasing linearly from zero, while the switch current i

_{S1}, having an initial value determined by the end of Mode 10, also increases linearly. In addition, the energy remained in L

_{k3}will be recycled to C

_{2}via D

_{2}. At the time that the diode current i

_{D}

_{2}drops to zero, and this mode ends.

**Mode 2 (t**: During this time interval, active switches S

_{1}–t_{2}) (Figure 2b)_{1}and S

_{2}are still closed, and V

_{in}remains across the two coupled inductors

_{.}Thus, the current i

_{Lm1}and i

_{Lm2}are continuously increasing. In this mode, the current flowing through leakage inductances i

_{lk1}and i

_{lk2}are equal to magnetizing-inductance currents i

_{Lm1}and i

_{Lm2}, respectively. This mode ends when the switch S

_{1}is turned off.

**Mode 3 (t**: In this mode, S

_{2}–t_{3}) (Figure 2c)_{2}remains in on state but S

_{1}becomes off. Diodes D

_{2}, D

_{3}and D

_{o}are reversely-biased but D

_{1}is in forward-bias. The V

_{in}, L

_{m1}, L

_{k1}and C

_{2}dump energy to L

_{k3}and C

_{1}via D

_{1}and S

_{2}, so the current flowing through D

_{1}and S

_{2}increases. This mode finishes when D

_{3}becomes forward-biased and L

_{k}

_{3}starts to release energy.

**Mode 4 (t**: Over the whole interval of Mode 4, S

_{3}–t_{4}) (Figure 2d)_{2}is still kept in on state while S

_{1}in off state. The D

_{1}remains forward-biased and D

_{3}becomes closed. Meanwhile, both diodes D

_{2}and D

_{o}continue the off status. Magnetizing-inductance L

_{m1}pumps energy to C

_{3}via the coupled inductor. Capacitor C

_{1}is charged continuously, the circuit behavior of which is the same as in the previous mode. When the leakage-inductance L

_{k1}releases over its stored energy, i

_{D}

_{1}will drop to zero. That is, diode D

_{1}becomes reversely-biased and this mode ends.

**Mode 5 (t**: During this time interval, S

_{4}–t_{5}) (Figure 2e)_{2}is still closed and S

_{1}is open. Diodes D

_{1}, D

_{2}and D

_{o}are reversely-biased but D

_{3}is in forward-bias. V

_{in}and L

_{m1}supply energy to C

_{3}simultaneously by the T

_{1}and T

_{2}in turn. This mode finishes as S

_{1}is turned on.

**Mode 6 (t**: During this mode, S

_{5}–t_{6}) (Figure 2f)_{1}and S

_{2}are both in on state. Diodes D

_{1}, D

_{2}and D

_{o}are off, but D

_{3}is on. L

_{m1}starts to draw energy from V

_{in}. The stored energy in L

_{k3}will releases to C

_{3}through D

_{3}. This mode sustains until i

_{D}

_{3}decreases to zero.

**Mode 7 (t**: During this time interval, S

_{6}–t_{7}) (Figure 2g)_{1}and S

_{2}are both in on state, but D

_{1}, D

_{2}, D

_{3}and D

_{o}are all reversely-biased. Since the primaries of the two coupled inductors are in parallel, V

_{in}will supply energy to L

_{m1}, L

_{m2}, L

_{k1}and L

_{k2}. Therefore, i

_{Lm1}and i

_{Lm2}will increase linearly, which are identical to i

_{S}

_{1}and i

_{S}

_{2}, respectively. This mode is ended when S

_{2}is turned off.

**Mode 8 (t**: During this time interval, S

_{7}–t_{8}) (Figure 2h)_{1}remains in on state, but S

_{2}in off state. D

_{1}, D

_{2}and D

_{3}are off, but D

_{o}is on. The L

_{m2}starts to release its stored energy so that the current flowing through L

_{m2}decays. Meanwhile, the current i

_{lk3}increases. The input V

_{in}and the voltages across L

_{m2}, L

_{k2}, C

_{1}, and C

_{3}will be stacked up to supply C

_{o}. This mode terminates when L

_{k3}starts to charge C

_{2}.

**Mode 9 (t**: In this mode, S

_{8}–t_{9}) (Figure 2i)_{1}is still closed and S

_{2}is open. The V

_{in}will charge C

_{2}via coupled inductor T

_{1}; meanwhile, the energy stored in L

_{m2}will also be transferred to the secondary of T

_{2}for powering C

_{2}. Therefore, i

_{Lm2}drops and C

_{o}keeps on charging. In Mode 9, the energy in L

_{k2}is recycled to the output. This mode ends as i

_{lk2}falls to zero.

**Mode 10 (t**: The diode D

_{9}–t_{10}) (Figure 2j)_{o}will become reversely biased when i

_{lk2}drops to zero. In Mode 10, S

_{1}proceeds with on-state conducting and S

_{2}remains in off state. With respect to diode status, the diodes D

_{1}, D

_{3}and D

_{o}are in reverse-bias and D

_{2}is still in on state. The V

_{in}and L

_{m2}will forward energy to C

_{2}through the coupled inductors T

_{1}and T

_{2}, respectively. This mode ends when S

_{2}is turned on again, and then the operation returns to Mode 1.

## 3. Voltage Gain Derivation

Voltage gain is the most important characteristic of a high step-up converter. As the analysis in Section 2 shows, the switched capacitors C

_{1}and C_{3}have the benefit of voltage stacking for achieving extra-high voltage gain. This section focuses on the voltage gain derivation of the proposed NIC. For high power applications, the converter is designed in CCM. Assumptions made in Section 2 are also adopted for simplifying the derivation. Furthermore, the coupling coefficients of the coupled inductors are both supposed at unity; that is, there is no leakage inductance.According to the description for Mode 4 in Section 2, C

_{1}is charged by V_{in}, C_{2}, T_{1}, and T_{2}, whereas C_{3}is charged by the two coupled inductors. Referring to Mode 9 in Section 2, if the leakage inductances are ignored, the output port is supplied by V_{in}, T_{1}, T_{2}, C_{1}, and C_{3}. Hence, to determine the voltage gain, V_{o}/V_{in}, the relationships of V_{C}_{1}, V_{C}_{2}and V_{C}_{3}in terms of V_{in}have to be found in advance.#### 3.1. The Ratio of V_{C3} to V_{in}

As S

_{1}is closed, V_{in}will supply energy to L_{m}_{1}. After an on-time interval DT_{s}, the change in i_{Lm1}can be estimated as:
$${\left(\Delta {i}_{\mathrm{Lm}1}\right)}_{\mathrm{on}}=\frac{{V}_{\mathrm{in}}D{T}_{\mathrm{s}}}{{L}_{\mathrm{m}1}}$$

In the opposite switch statuses, that is, S

_{1}off and S_{2}on, the energy stored in L_{m}_{1}will be transferred to the secondary of the coupled inductor T_{1}and then be forwarded to C_{3}by the loop of N_{2}-N_{12}-D_{3}-C_{2}. In addition, the source voltage V_{in}also supplies energy to C_{3}via T_{2}. By Kirchhoff's voltage law (KVL) and from the closed loop N_{2}-N_{12}-D_{3}-C_{2}, it can be found that:
$${n}_{2}{V}_{\mathrm{Lm}2}-{n}_{1}{V}_{\mathrm{Lm}1}-{V}_{C3}=0$$

Since voltage across L

_{m2}is V_{in}, rewriting Equation (2) becomes:
$${V}_{\mathrm{Lm}1}=\frac{n{V}_{\mathrm{in}}-{V}_{\mathrm{C}3}}{n}={L}_{\mathrm{m}1}\frac{\mathrm{d}{i}_{\mathrm{Lm}1}}{\mathrm{d}t}$$

From Equation (3), the current change in L

_{m1}after a switch-off interval (1 − D)T_{s}, is found by:
$${\left(\Delta {i}_{\mathrm{Lm}1}\right)}_{\mathrm{off}}=\frac{\left(n{V}_{\mathrm{in}}-{V}_{C3}\right)\left(1-D\right){T}_{\mathrm{s}}}{n{L}_{\mathrm{m}1}}$$

In steady state, over one switching cycle the net change of inductor current i

_{Lm1}is zero. That is:
$$n{V}_{\mathrm{in}}D{T}_{\mathrm{s}}+\left(n{V}_{\mathrm{in}}-{V}_{\mathrm{C}3}\right)\left(1-D\right){T}_{\mathrm{s}}=0$$

Rearranging the above equation can obtain the voltage of V

_{C3}in terms of V_{in}as follows:
$${V}_{\mathrm{C}3}=\frac{n{V}_{\mathrm{in}}}{(1-D)}$$

#### 3.2. The Ratio of V_{C2} to V_{in}

With respect to the ratio of V
when switch S

_{C2}to V_{in}, the current change in L_{m2}has to be dealt with first. The current flowing through L_{m2}increases when S_{2}is closed. After DT_{s}, the change (Δi_{Lm2})_{on}can be expressed as:
$${\left(\Delta {i}_{\mathrm{Lm}2}\right)}_{\mathrm{on}}=\frac{{V}_{\mathrm{in}}D{T}_{\mathrm{s}}}{{L}_{\mathrm{m}2}}$$

_{2}is open for (1 − D)T_{s}and S_{1}is in on state. The energy stored in L_{m2}will be released to C_{2}by coupled inductor T_{2}as well as the loop of N_{12}-N_{2}-C_{3}-D_{2}. Therefore:
$$n{V}_{\mathrm{Lm}1}-n{V}_{\mathrm{Lm}2}-{V}_{\mathrm{C}2}=0$$

In Equation (8), the voltage across L

_{m1}equals V_{in}, thus:
$${V}_{\mathrm{Lm}2}=\frac{n{V}_{in}-{V}_{\mathrm{C}2}}{n}={L}_{m2}\frac{\mathrm{d}{i}_{\mathrm{Lm}2}}{\mathrm{d}t}$$

The total current drop in L

_{m2}can be found by:
$${\left(\Delta {i}_{\mathrm{Lm}2}\right)}_{\mathrm{off}}=\frac{\left(n{V}_{\mathrm{in}}-{V}_{\mathrm{C}2}\right)\left(1-D\right){T}_{\mathrm{s}}}{n{L}_{\mathrm{m}2}}$$

In steady state, over one switching cycle the net change of the inductor current i

_{Lm2}is zero. That is:
$$n{V}_{\mathrm{in}}D{T}_{\mathrm{s}}+\left(n{V}_{\mathrm{in}}-{V}_{\mathrm{C}2}\right)\left(1-D\right){T}_{\mathrm{s}}=0$$

Thus, the voltage of V

_{C2}in terms of V_{in}is as follows:
$${V}_{\mathrm{C}2}=\frac{n{V}_{\mathrm{in}}}{(1-D)}$$

#### 3.3. The Ratio of V_{C1} to V_{in}

While S

_{1}is open and S_{2}is closed, from the current flow path of V_{in}-L_{m}_{1}-D_{1}-C_{2}-N_{2}-N_{12}-C_{1}-S_{2}, the following relationship can be found:
$${V}_{\mathrm{Lm}1}=\frac{{V}_{\mathrm{in}}+{V}_{\mathrm{C}2}+n{V}_{\mathrm{Lm}2}-{V}_{\mathrm{C}1}}{\left(1+n\right)}={L}_{\mathrm{m}1}\frac{\mathrm{d}{i}_{\mathrm{Lm}1}}{\mathrm{d}t}$$

Since the voltage across L

_{m2}in Equation (13) is V_{in}, the current decrease on L_{m1}is derived as:
$${\left(\Delta {i}_{\mathrm{Lm}1}\right)}_{\mathrm{off}}=\frac{({V}_{\mathrm{in}}+{V}_{\mathrm{C}2}+n{V}_{\mathrm{in}}-{V}_{\mathrm{C}1})(1-D){T}_{\mathrm{s}}}{\left(1+n\right){L}_{\mathrm{m}1}}$$

In addition, the total amount of current increase on L

_{m1}over the S_{1}-closed interval has been depicted as Equation (1). This increment is equal to the decrease amount in i_{Lm1}over one switching cycle, which yields:
$$\frac{{V}_{\mathrm{in}}D{T}_{\mathrm{s}}}{{L}_{\mathrm{m}1}}+\frac{({V}_{\mathrm{in}}+{V}_{\mathrm{C}2}+n{V}_{\mathrm{in}}-{V}_{\mathrm{C}1})(1-D){T}_{\mathrm{s}}}{(1+n){L}_{\mathrm{m}1}}=0$$

Rearranging Equation (15) results in:

$${V}_{\mathrm{C}1}=\frac{(1+2n)}{(1-D)}{V}_{\mathrm{in}}$$

#### 3.4. The Ratio of V_{o} to V_{in}

Under the condition that S

_{1}is closed and S_{2}is in off state, the voltage V_{Lm2}can be determined by applying KVL to the loop enclosed by V_{in}, L_{m2}, C_{1}, N_{12}, N_{2}, C_{3}, D_{o}, and C_{o}. Therefore:
$${V}_{\mathrm{Lm}2}=\frac{{V}_{\mathrm{in}}+{V}_{\mathrm{C}1}+n{V}_{\mathrm{in}}+{V}_{\mathrm{C}3}-{V}_{\mathrm{o}}}{\left(1+n\right)}={L}_{\mathrm{m}2}\frac{{\mathrm{di}}_{\mathrm{Lm}2}}{\mathrm{dt}}$$

Thus, the decreased quantity of i

_{Lm2}is expressed as:
$${\left(\Delta {i}_{\mathrm{Lm}2}\right)}_{\mathrm{off}}=\frac{\left({V}_{\mathrm{in}}+{V}_{\mathrm{C}1}+n{V}_{\mathrm{in}}+{V}_{\mathrm{C}3}-{V}_{\mathrm{o}}\right)\left(1-D\right){T}_{\mathrm{s}}}{\left(1+n\right){L}_{\mathrm{m}2}}$$

From the increment (Δi

_{Lm2})_{on}in Equation (7) and the condition (Δi_{Lm2})_{off}= (Δi_{Lm2})_{on}, the following relationship holds:
$$\frac{{V}_{\mathrm{in}}D{T}_{\mathrm{s}}}{{L}_{\mathrm{m}2}}+\frac{\left({V}_{\mathrm{in}}+{V}_{\mathrm{C}1}+n{V}_{\mathrm{in}}+{V}_{\mathrm{C}3}-{V}_{\mathrm{o}}\right)\left(1-D\right){T}_{\mathrm{s}}}{\left(1+n\right){L}_{\mathrm{m}2}}=0$$

After simplifying, the following equation can be obtained:

$${V}_{\mathrm{in}}\frac{\left(1+n\right)D}{\left(1-D\right)}+{V}_{\mathrm{in}}+{V}_{\mathrm{C}1}+n{V}_{\mathrm{in}}+{V}_{\mathrm{C}3}-{V}_{\mathrm{o}}=0$$

Substituting Equations (6) and (16) into Equation (20) can obtain the voltage gain of the proposed converter, V

_{o}/V_{in}, and yields:
$$\frac{{V}_{\mathrm{o}}}{{V}_{\mathrm{in}}}=\frac{2\left(2n+1\right)}{(1-D)}$$

## 4. Voltage Stress of Power Component

This section begins with the determination of voltage stresses across S

_{1}and S_{2}. Supposing that all leakage inductances are neglected, Modes 4 and 9 in Section 2 will therefore dominate the estimation of voltage stress. When S_{1}is open, from Figure 2d it can be found that the blocking voltage of S_{1}, V_{DS1,stress}, can be expressed as
$${V}_{\mathrm{DS}1,\text{stress}}={V}_{\mathrm{C}1}-{V}_{\mathrm{C}2}-{V}_{\mathrm{C}3}=\frac{1}{1-D}{V}_{\mathrm{in}}$$

With respect to active switch S

_{2}, its blocking voltage, V_{DS2,stress}, can be determined from Figure 2i and the following relationship can be found:
$${V}_{\mathrm{DS}2,\text{stress}}={V}_{\mathrm{o}}-{V}_{\mathrm{C}3}-{V}_{\mathrm{C}2}-{V}_{\mathrm{C}1}=\frac{1}{1-D}{V}_{\mathrm{in}}$$

Equations (22) and (23) reveal that the voltage stresses of S

_{1}and S_{2}are identical and irrelative to turns ratio of coupled inductor. Voltage stresses across active switches only depend on duty ratio and input voltage. Rewriting Equations (22) and (23) in terms of V_{o}results in:
$${V}_{\mathrm{DS}1,\mathrm{stress}}={V}_{\mathrm{DS}2,\mathrm{stress}}=\frac{{V}_{\mathrm{o}}}{2(1+n)}$$

Equation (24) implies that the voltage stresses of S
and:

_{1}and S_{2}are much lower than output voltage. Considering the statues of S_{1}on and S_{2}off, the voltage across D_{1}and D_{3}can be determined as follows:
$${V}_{\mathrm{D}1,\text{stress}}={V}_{\mathrm{o}}-{V}_{\mathrm{C}3}-{V}_{\mathrm{C}2}=\frac{2(1+n)}{1-D}{V}_{\mathrm{in}}$$

$${V}_{\mathrm{D}3,\mathrm{stress}}={V}_{\mathrm{C}3}+{V}_{\mathrm{C}2}=\frac{2n}{1-D}{V}_{\mathrm{in}}$$

With respect to D
and:

_{2}and D_{o}, their voltage stresses are calculated during the time interval of S_{1}off and S_{2}on. The corresponding voltage stress calculations can be:
$${V}_{\mathrm{D}2,\mathrm{stress}}={V}_{\mathrm{C}2}+{V}_{\mathrm{C}3}=\frac{2n}{1-D}{V}_{\mathrm{in}}$$

$${V}_{\mathrm{D}\mathrm{o},\text{stress}}={V}_{\mathrm{o}}-{V}_{\mathrm{C}1}=\frac{1+2n}{1-D}{V}_{\mathrm{in}}$$

According to Equations (25)–(28), it can be observed that D

_{1}endures the highest voltage stress among the four diodes. Table 1 summaries the comparison between NIC and other high step-up converters proposed in [13,14,15,16]. If the duty cycle D is 0.6, and the transformer turns ratio n is 1, the proposed converter can boost 15-times input voltage. However, the voltage gains of the converters in [13,14,15,16] are 5, 5.6, 10, and 10, respectively. It is obvious that the proposed NIC can exceed these high step-up converters in voltage gain. With respect to voltage stress across semiconductor device, if under the same condition that D = 0.6, n = 1, and V_{o}= 380 V, the maximum voltage stress of the active switches in [15,16] and the proposed NIC are all 95 V, but the converters in [13,14] are up to 190 V and 170 V, respectively. That is, the proposed converter features an advantage over other high step-up converters.## 5. Experimental Results

To validate the proposed NIC, a prototype based on the specifications summarized in Table 2 is designed, built, and tested. The types of semiconductor devices used in the prototype are given in Table 3. The power MOSFET, IRFSL4615PbF (International Rectifier, El Segundo, CA, USA), is selected to serve as active switches for controlling the current flow, of which maximum on-state resistance R

_{DS(on)}is 42 mΩ. The FEP16GT (Fairchild, Sunnyvale, CA, USA) is employed as diodes D_{1}and D_{o}, of which forward voltage is 1.3 V and reverse recovery time is 50 ns. With regard to diodes D_{2}and D_{3}, the hyper-fast rectifier VS-8ETH03-1PbF (Nichicon, Kyoto, Japan) is considered, which has 1.25 V forward voltage and 35 ns reverse recovery time. The voltage waveforms of active power switches and control signals are shown in Figure 4a,b, which indicate that the voltage across S_{1}and S_{2}are both near 65 V. This value also demonstrates a relatively low voltage stress across the active power semiconductor, as compared with other high step-up converters.Figure 5a,d is the practical measurements of voltage waveforms of diodes D

_{o}, D_{1}, D_{2}and D_{3}, in turn, at the condition D = 0.62 and in CCM operation. Figure 5a illustrates that the maximum blocking voltage of D_{o}is nearly 200 V. With respect to D_{1}, its voltage stress approaches to 280 V, as shown in Figure 5b. Diodes D_{2}and D_{3}endure the same voltage of 130 V. In Figure 5, all the diode voltage stresses are in compliance with Equations (25)–(28).Figure 6 shows the waveforms of input current and the corresponding control signals. It indicates that the magnitude of input ripple current is limited to less than 2 A. Figure 7 depicts the measured and simulated efficiencies from light load to full load. In the simulations, the considered conditions include forward voltage of diode, R

_{DS(on)}of MOSFET, copper loss of the coupled inductor, switching loss of MOSFET, and the equivalent resistance of diode. The maximum value of the measured efficiency is 93.7% at P_{o}= 140 W. Figure 8 is the photo of test bench, in which PV simulator Chroma 62050H-600S (Taoyuan, Taiwan) serves as input source, electronic load Chroma 6320 draws power from the converter, and all waveforms are measured by oscilloscope KEYSIGHT DSOX4024A (Santa Rosa, CA, USA).## 6. Conclusions

This paper proposes a NIC, which is applicable to PV systems or fuel cells for grid-connected high-power applications. The proposed converter utilizes the interleaved technique for current sharing to decrease input current ripples. Furthermore, the proposed converter can achieve a much higher voltage gain than a conventional interleaved converter. The operation principle and steady-state analysis of the proposed converter are described in detail. A 24 V/380 V 200 W prototype has been examined to demonstrate the feasibility of the proposed NIC. The maximum measured efficiency of the proposed converter is 93.7%. This value is a little lower than some of other high step-up converters. However, if the soft-switching technique is employed to make the switches operate at zero-voltage-switching or zero-current-switching condition, the efficiency of the proposed NIC can be improved significantly.

## Acknowledgments

The authors would like to convey their appreciation for grant support from the Ministry of Science and Technology (MOST) of Taiwan under its grant with Reference Number MOST 105-3113-E-006-007.

## Author Contributions

Chih-Lung Shen, Yan-Chi Lee and Po-Chieh Chiu conceived and designed the circuit. Yan-Chi Lee and Po-Chieh Chiu performed simulations, carried out the prototype, and analyzed data with guidance from Chih-Lung Shen. Chih-Lung Shen revised the manuscript for submission.

## Conflicts of Interest

The authors declare that there is no conflict of interests regarding the publication of this paper.

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**Figure 1.**The main power circuit of the proposed novel interleaved converter (NIC). PV: photovoltaic.

**Figure 2.**Mode equivalents of the proposed NIC over one switching period. (

**a**) Mode 1 (t

_{0}–t

_{1}); (

**b**) Mode 2 (t

_{1}–t

_{2}); (

**c**) Mode 3 (t

_{2}–t

_{3}); (

**d**) Mode 4 (t

_{3}–t

_{4}); (

**e**) Mode 5 (t

_{4}–t

_{5}); (

**f**) Mode 6 (t

_{5}–t

_{6}); (

**g**) Mode 7 (t

_{6}–t

_{7}); (

**h**) Mode 8 (t

_{7}–t

_{8}); (

**i**) Mode 9 (t

_{8}–t

_{9}); and (

**j**) Mode 10 (t

_{9}–t

_{10}).

**Figure 4.**Experimental waveforms of active power switches in CCM operation and at D = 0.62. (

**a**) v

_{DS1}and the corresponding control signals (v

_{DS1}: 50 V/div, v

_{gs1}and v

_{gs2}: 10 V/div, time: 10 μs/div). (

**b**) v

_{DS2}and the corresponding control signals (v

_{DS2}: 50 V/div, v

_{gs1}and v

_{gs2}: 10 V/div, time: 10 μs/div).

**Figure 5.**Experimental waveforms of diodes: (

**a**) v

_{D}

_{o}(v

_{D}

_{o}: 100 V/div, v

_{gs}

_{1}and v

_{gs2}: 20 V/div, time: 5 μs/div); (

**b**) v

_{D}

_{1}(v

_{D}

_{1}: 200 V/div, v

_{gs1}and v

_{gs2}: 20 V/div, time: 5 μs/div); (

**c**) v

_{D}

_{2}(v

_{D}

_{2}: 100 V/div, v

_{gs1}and v

_{gs2}: 20 V/div, time: 5 μs/div); (

**d**) v

_{D}

_{3}(v

_{D}

_{3}: 100 V/div, v

_{gs1}and v

_{gs2}: 20 V/div, time: 5 μs/div).

**Figure 6.**Experimental waveforms of input current and corresponding control signals (i

_{in}: 5 A/div, v

_{gs1}and v

_{gs2}: 20 V/div, time: 10 μs/div).

Items | Converter Introduced in [13] | Converter Introduced in [14] | Converter Introduced in [15] | Converter Introduced in [16] | Proposed Converter |
---|---|---|---|---|---|

Voltage gain | $\frac{1+n}{1-D}$ | $\frac{2+nD-n{D}^{2}}{1-D}$ | $\frac{2(1+n)}{1-D}$ | $\frac{2(1+n)}{1-D}$ | $\frac{2(1+2n)}{1-D}$ |

Number of active switches | 4 | 2 | 2 | 2 | 2 |

Number of diodes | 4 | 4 | 6 | 4 | 4 |

Number of capacitors | 3 | 3 | 5 | 4 | 4 |

Number of transformers | 1 | 1 | 2 | 2 | 2 |

Number of inductors | 2 | 2 | 0 | 0 | 0 |

Maximum voltage stress of active switch | $\frac{{V}_{\mathrm{o}}}{1+n}$ | $\frac{{V}_{\mathrm{o}}}{2+nD-n{D}^{2}}$ | $\frac{{V}_{\mathrm{o}}}{2(1+n)}$ | $\frac{{V}_{\mathrm{o}}}{2(1+n)}$ | $\frac{{V}_{o}}{2(1+n)}$ |

Maximum voltage stress of diode | V_{o} | $\frac{2{V}_{\mathrm{o}}}{2+nD-n{D}^{2}}$ | $\frac{(1+2n){V}_{\mathrm{o}}}{2(1+n)}$ | $\frac{n{V}_{\mathrm{o}}}{1+n}$ | $\frac{(1+n){V}_{\mathrm{o}}}{1+2n}$ |

Symbols | Items | Values |
---|---|---|

V_{in} | Input voltage | 24 V |

V_{o} | Output voltage | 380 V |

P_{o} | Output power | 200 W |

D | Duty cycle | 0.62 |

f_{s} | Switching frequency | 50 kHz |

n | Transformer turns ratio | 1 |

L_{m} | Magnetizing inductance | 93 μH |

L_{lk} | Leakage inductance | 1.9 μH |

C_{1}, C_{2}, and C_{3} | Capacitances | 68 μF |

C_{o} | Output capacitance | 330 μF |

Components | Types | Absolute Maximum Ratings |
---|---|---|

D_{1} and D_{o} | FEP16GT | 400 V/16 A |

D_{2} and D_{3} | VS-8ETH03-1PbF | 300 V/8 A |

S_{1} and S_{2} | IRFSL4615PbF | 150 V/33 A |

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