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Energies 2016, 9(11), 871; doi:10.3390/en9110871

Article
Novel Interleaved Converter with Extra-High Voltage Gain to Process Low-Voltage Renewable-Energy Generation
Department of Electronic Engineering, National Kaohsiung First University of Science and Technology, Kaohsiung 82445, Taiwan
*
Author to whom correspondence should be addressed.
Academic Editor: Paul Stewart
Received: 28 July 2016 / Accepted: 17 October 2016 / Published: 25 October 2016

Abstract

:
This paper presents a novel interleaved converter (NIC) with extra-high voltage gain to process the power of low-voltage renewable-energy generators such as photovoltaic (PV) panel, wind turbine, and fuel cells. The NIC can boost a low input voltage to a much higher voltage level to inject renewable energy to DC bus for grid applications. Since the NIC has two circuit branches in parallel at frond end to share input current, it is suitable for high power applications. In addition, the NIC is controlled in an interleaving pattern, which has the advantages that the NIC has lower input current ripple, and the frequency of the ripple is twice the switching frequency. Two coupled inductors and two switched capacitors are incorporated to achieve a much higher voltage gain than conventional high step-up converters. The proposed NIC has intrinsic features such as leakage energy totally recycling and low voltage stress on power semiconductor. Thorough theoretical analysis and key parameter design are presented in this paper. A prototype is built for practical measurements to validate the proposed NIC.
Keywords:
photovoltaic (PV) panel; fuel cells; high step-up converter; interleaved converter; low voltage stress

1. Introduction

Since fossil fuels will be depleted in the next decades, development of green energy power generation systems becomes urgent. Among renewable energy generation systems, photovoltaic (PV), wind turbine, energy storage systems, and fuel cells attract a lot of attention [1,2,3,4]. Nevertheless, low output voltage is their common shortcoming, especially in grid connection or electric vehicle (EV) applications. Therefore, a step-up converter to achieve high voltage gain is required. Conventional boost-type converters, like boost, buck-boost, and flyback, are able to step-up input voltage. However, in order to meet high-voltage gain requirements, they have to operate in heavy-duty ratio or adopt a high turns ratio transformer, which will decrease the conversion efficiency dramatically. Cascading more boost-type converters can avoid the above problem but issues of volume, cost, and efficiency emerge. Therefore, the high step-up DC/DC converter is the current design trend.
High step-up converters can be mainly classified into two categories: single-stage and interleaved structure. Single-stage topology incorporates coupled inductors and/or switched capacitors to complete high voltage gain. Even though its input voltage is boosted, a large magnitude of input current ripple occurs, limiting the converter power rating significantly [5,6,7,8]. The interleaved converter has the ability of suppressing input current ripple by means of adding a parallel current path, which is a better choice for high power applications [9,10,11]. However, the conventional interleaved converters have voltage gain limitation, which confines their applications in grid-tied systems. To overcome the aforementioned disadvantages, various high step-up interleaved converters were proposed in [12,13,14,15,16]; nevertheless, the shortcomings of lower voltage gain, higher voltage stress, and large component count still exist. An interleaved Boost converter combining voltage doubler is introduced in [12], while a coupled inductor is examined in [13]. In order to achieve high voltage gain, the converters in [12,13] have to be operated at heavy-duty ratio or adopt a magnetic transform with high turns ratio, which results in low conversion efficiency or high voltage stress. Even though Lai et al. [14] proposed another high step-up converter, incorporating coupled inductor and switched capacitor, into an interleaved Boost configuration, the converter intrinsically has the demerits of higher voltage stress and sophisticated structure. An interleaved step-up converter with winding-cross-coupled inductors and voltage multiplier cells is presented in [15]. This converter is composed of eight semiconductor devices and two three-winding coupled inductors. That is, a large number of power devices must be used. Tseng et al. [16] utilized the characteristics of forward, flyback, and interleaved converters to boost input voltage, but voltage gain still is limited.
This paper proposes a novel interleaved converter (NIC), which can accomplish a high voltage conversion ratio and is capable of processing low voltage, high power distributed resources. Its power stage is depicted in Figure 1. The proposed NIC mainly includes three parts: one interleaved-boost converter cell and two voltage multipliers. The interleaved-Boost converter cell is in charge of lowering input current ripple, increasing current rating, and primarily stepping input voltage. The two voltage multipliers can further stack up voltage level. The series voltage of the three parts determines the magnitude of output voltage. Since the proposed converter only uses two coupled inductors, three capacitors, four diodes, and two active power switches, it has a lower component count and a simple circuit structure. The advantages of the proposed NIC are summarized as follows:
(1)
The NIC can suppress input current ripple.
(2)
The energy stored in leakage inductance can be recycled.
(3)
The voltage stress of the semiconductor device is low enough so that a power switch with lower on-state resistance and smaller parasitic capacitance can be chosen.
(4)
As compared with a conventional interleaved high step-up converter, the proposed NIC can achieve a much higher voltage gain under the same power component count.

2. Operation Principle of the Proposed Converter

In Figure 1, Lm1 and Lm2 denote the magnetizing inductances of the coupled inductors T1 and T2, respectively. The Lk1 and Lk2 represent the primary leakage inductances of T1 and T2, in turn, while Lk3 stands for the total leakage inductance at the secondary windings of both coupled inductors. Turns ratios of primary to secondary of T1 and T2 are denoted as n1 and n2, respectively. C1, C2, and C3 are the main capacitors employed in the circuit. It is supposed that the NIC operates in continuous conduction mode (CCM) and the two active switches S1 and S2 are controlled in interleaved manner. Accordingly, the operation of the NIC can be divided into ten operation modes over one switching cycle. The corresponding equivalents are illustrated in Figure 2, while Figure 3 depicts key waveforms. Analysis of the proposed NIC begins by making these assumptions:
(1)
All parasitic capacitances and internal resistances are neglected. Moreover, all diodes are ideal.
(2)
The voltages across capacitors C1, C2, C3, and Co are time-invariant.
(3)
Magnetizing inductances, Lm1 and Lm2, are much larger than the leakage inductances Llk1, Llk2 and Llk3.
(4)
The switching period is Ts. Both switches are closed for time DTs and open for (1 − D)Ts.
Mode 1 (t0t1) (Figure 2a): This mode is the initial mode of the all operation procedures. During this time interval, both active switches S1 and S2 are closed. Diodes D1, D3 and Do are in reverse-bias, but D2 is forward-biased. Input voltage Vin is across the primaries of T1 and T2 directly. Then, the current flowing through S2 starts increasing linearly from zero, while the switch current iS1, having an initial value determined by the end of Mode 10, also increases linearly. In addition, the energy remained in Lk3 will be recycled to C2 via D2. At the time that the diode current iD2 drops to zero, and this mode ends.
Mode 2 (t1t2) (Figure 2b): During this time interval, active switches S1 and S2 are still closed, and Vin remains across the two coupled inductors. Thus, the current iLm1 and iLm2 are continuously increasing. In this mode, the current flowing through leakage inductances ilk1 and ilk2 are equal to magnetizing-inductance currents iLm1 and iLm2, respectively. This mode ends when the switch S1 is turned off.
Mode 3 (t2t3) (Figure 2c): In this mode, S2 remains in on state but S1 becomes off. Diodes D2, D3 and Do are reversely-biased but D1 is in forward-bias. The Vin, Lm1, Lk1 and C2 dump energy to Lk3 and C1 via D1 and S2, so the current flowing through D1 and S2 increases. This mode finishes when D3 becomes forward-biased and Lk3 starts to release energy.
Mode 4 (t3t4) (Figure 2d): Over the whole interval of Mode 4, S2 is still kept in on state while S1 in off state. The D1 remains forward-biased and D3 becomes closed. Meanwhile, both diodes D2 and Do continue the off status. Magnetizing-inductance Lm1 pumps energy to C3 via the coupled inductor. Capacitor C1 is charged continuously, the circuit behavior of which is the same as in the previous mode. When the leakage-inductance Lk1 releases over its stored energy, iD1 will drop to zero. That is, diode D1 becomes reversely-biased and this mode ends.
Mode 5 (t4t5) (Figure 2e): During this time interval, S2 is still closed and S1 is open. Diodes D1, D2 and Do are reversely-biased but D3 is in forward-bias. Vin and Lm1 supply energy to C3 simultaneously by the T1 and T2 in turn. This mode finishes as S1 is turned on.
Mode 6 (t5t6) (Figure 2f): During this mode, S1 and S2 are both in on state. Diodes D1, D2 and Do are off, but D3 is on. Lm1 starts to draw energy from Vin. The stored energy in Lk3 will releases to C3 through D3. This mode sustains until iD3 decreases to zero.
Mode 7 (t6t7) (Figure 2g): During this time interval, S1 and S2 are both in on state, but D1, D2, D3 and Do are all reversely-biased. Since the primaries of the two coupled inductors are in parallel, Vin will supply energy to Lm1, Lm2, Lk1 and Lk2. Therefore, iLm1 and iLm2 will increase linearly, which are identical to iS1 and iS2, respectively. This mode is ended when S2 is turned off.
Mode 8 (t7t8) (Figure 2h): During this time interval, S1 remains in on state, but S2 in off state. D1, D2 and D3 are off, but Do is on. The Lm2 starts to release its stored energy so that the current flowing through Lm2 decays. Meanwhile, the current ilk3 increases. The input Vin and the voltages across Lm2, Lk2, C1, and C3 will be stacked up to supply Co. This mode terminates when Lk3 starts to charge C2.
Mode 9 (t8t9) (Figure 2i): In this mode, S1 is still closed and S2 is open. The Vin will charge C2 via coupled inductor T1; meanwhile, the energy stored in Lm2 will also be transferred to the secondary of T2 for powering C2. Therefore, iLm2 drops and Co keeps on charging. In Mode 9, the energy in Lk2 is recycled to the output. This mode ends as ilk2 falls to zero.
Mode 10 (t9t10) (Figure 2j): The diode Do will become reversely biased when ilk2 drops to zero. In Mode 10, S1 proceeds with on-state conducting and S2 remains in off state. With respect to diode status, the diodes D1, D3 and Do are in reverse-bias and D2 is still in on state. The Vin and Lm2 will forward energy to C2 through the coupled inductors T1 and T2, respectively. This mode ends when S2 is turned on again, and then the operation returns to Mode 1.

3. Voltage Gain Derivation

Voltage gain is the most important characteristic of a high step-up converter. As the analysis in Section 2 shows, the switched capacitors C1 and C3 have the benefit of voltage stacking for achieving extra-high voltage gain. This section focuses on the voltage gain derivation of the proposed NIC. For high power applications, the converter is designed in CCM. Assumptions made in Section 2 are also adopted for simplifying the derivation. Furthermore, the coupling coefficients of the coupled inductors are both supposed at unity; that is, there is no leakage inductance.
According to the description for Mode 4 in Section 2, C1 is charged by Vin, C2, T1, and T2, whereas C3 is charged by the two coupled inductors. Referring to Mode 9 in Section 2, if the leakage inductances are ignored, the output port is supplied by Vin, T1, T2, C1, and C3. Hence, to determine the voltage gain, Vo/Vin, the relationships of VC1, VC2 and VC3 in terms of Vin have to be found in advance.

3.1. The Ratio of VC3 to Vin

As S1 is closed, Vin will supply energy to Lm1. After an on-time interval DTs, the change in iLm1 can be estimated as:
( Δ i Lm 1 ) on = V in D T s L m 1
In the opposite switch statuses, that is, S1 off and S2 on, the energy stored in Lm1 will be transferred to the secondary of the coupled inductor T1 and then be forwarded to C3 by the loop of N2-N12-D3-C2. In addition, the source voltage Vin also supplies energy to C3 via T2. By Kirchhoff's voltage law (KVL) and from the closed loop N2-N12-D3-C2, it can be found that:
n 2 V Lm 2 n 1 V Lm 1 V C 3 = 0
Since voltage across Lm2 is Vin, rewriting Equation (2) becomes:
V Lm 1 = n V in V C 3 n = L m 1 d i Lm 1 d t
From Equation (3), the current change in Lm1 after a switch-off interval (1 − D)Ts, is found by:
( Δ i Lm 1 ) off = ( n V in V C 3 ) ( 1 D ) T s n L m 1
In steady state, over one switching cycle the net change of inductor current iLm1 is zero. That is:
n V in D T s + ( n V in V C 3 ) ( 1 D ) T s = 0
Rearranging the above equation can obtain the voltage of VC3 in terms of Vin as follows:
V C 3 = n V in ( 1 D )

3.2. The Ratio of VC2 to Vin

With respect to the ratio of VC2 to Vin, the current change in Lm2 has to be dealt with first. The current flowing through Lm2 increases when S2 is closed. After DTs, the change (ΔiLm2)on can be expressed as:
( Δ i Lm 2 ) on = V in D T s L m 2
when switch S2 is open for (1 − D)Ts and S1 is in on state. The energy stored in Lm2 will be released to C2 by coupled inductor T2 as well as the loop of N12-N2-C3-D2. Therefore:
n V Lm 1 n V Lm 2 V C 2 = 0
In Equation (8), the voltage across Lm1 equals Vin, thus:
V Lm 2 = n V i n V C 2 n = L m 2 d i Lm 2 d t
The total current drop in Lm2 can be found by:
( Δ i Lm 2 ) off = ( n V in V C 2 ) ( 1 D ) T s n L m 2
In steady state, over one switching cycle the net change of the inductor current iLm2 is zero. That is:
n V in D T s + ( n V in V C 2 ) ( 1 D ) T s = 0
Thus, the voltage of VC2 in terms of Vin is as follows:
V C 2 = n V in ( 1 D )

3.3. The Ratio of VC1 to Vin

While S1 is open and S2 is closed, from the current flow path of Vin-Lm1-D1-C2-N2-N12-C1-S2, the following relationship can be found:
V Lm 1 = V in + V C 2 + n V Lm 2 V C 1 ( 1 + n ) = L m 1 d i Lm 1 d t
Since the voltage across Lm2 in Equation (13) is Vin, the current decrease on Lm1 is derived as:
( Δ i Lm 1 ) off = ( V in + V C 2 + n V in V C 1 ) ( 1 D ) T s ( 1 + n ) L m 1
In addition, the total amount of current increase on Lm1 over the S1-closed interval has been depicted as Equation (1). This increment is equal to the decrease amount in iLm1 over one switching cycle, which yields:
V in D T s L m 1 + ( V in + V C 2 + n V in V C 1 ) ( 1 D ) T s ( 1 + n ) L m 1 = 0
Rearranging Equation (15) results in:
V C 1 = ( 1 + 2 n ) ( 1 D ) V in

3.4. The Ratio of Vo to Vin

Under the condition that S1 is closed and S2 is in off state, the voltage VLm2 can be determined by applying KVL to the loop enclosed by Vin, Lm2, C1, N12, N2, C3, Do, and Co. Therefore:
V Lm 2 = V in + V C 1 + n V in + V C 3 V o ( 1 + n ) = L m 2 di Lm 2 dt
Thus, the decreased quantity of iLm2 is expressed as:
( Δ i Lm 2 ) off = ( V in + V C 1 + n V in + V C 3 V o ) ( 1 D ) T s ( 1 + n ) L m 2
From the increment (ΔiLm2)on in Equation (7) and the condition (ΔiLm2)off = (ΔiLm2)on, the following relationship holds:
V in D T s L m 2 + ( V in + V C 1 + n V in + V C 3 V o ) ( 1 D ) T s ( 1 + n ) L m 2 = 0
After simplifying, the following equation can be obtained:
V in ( 1 + n ) D ( 1 D ) + V in + V C 1 + n V in + V C 3 V o = 0
Substituting Equations (6) and (16) into Equation (20) can obtain the voltage gain of the proposed converter, Vo/Vin, and yields:
V o V in = 2 ( 2 n + 1 ) ( 1 D )

4. Voltage Stress of Power Component

This section begins with the determination of voltage stresses across S1 and S2. Supposing that all leakage inductances are neglected, Modes 4 and 9 in Section 2 will therefore dominate the estimation of voltage stress. When S1 is open, from Figure 2d it can be found that the blocking voltage of S1, VDS1,stress, can be expressed as
V DS 1 , stress = V C 1 V C 2 V C 3 = 1 1 D V in
With respect to active switch S2, its blocking voltage, VDS2,stress, can be determined from Figure 2i and the following relationship can be found:
V DS 2 , stress = V o V C 3 V C 2 V C 1 = 1 1 D V in
Equations (22) and (23) reveal that the voltage stresses of S1 and S2 are identical and irrelative to turns ratio of coupled inductor. Voltage stresses across active switches only depend on duty ratio and input voltage. Rewriting Equations (22) and (23) in terms of Vo results in:
V DS 1 , stress = V DS 2 , stress = V o 2 ( 1 + n )
Equation (24) implies that the voltage stresses of S1 and S2 are much lower than output voltage. Considering the statues of S1 on and S2 off, the voltage across D1 and D3 can be determined as follows:
V D 1 , stress = V o V C 3 V C 2 = 2 ( 1 + n ) 1 D V in
and:
V D 3 , stress = V C 3 + V C 2 = 2 n 1 D V in
With respect to D2 and Do, their voltage stresses are calculated during the time interval of S1 off and S2 on. The corresponding voltage stress calculations can be:
V D 2 , stress = V C 2 + V C 3 = 2 n 1 D V in
and:
V D o , stress = V o V C 1 = 1 + 2 n 1 D V in
According to Equations (25)–(28), it can be observed that D1 endures the highest voltage stress among the four diodes. Table 1 summaries the comparison between NIC and other high step-up converters proposed in [13,14,15,16]. If the duty cycle D is 0.6, and the transformer turns ratio n is 1, the proposed converter can boost 15-times input voltage. However, the voltage gains of the converters in [13,14,15,16] are 5, 5.6, 10, and 10, respectively. It is obvious that the proposed NIC can exceed these high step-up converters in voltage gain. With respect to voltage stress across semiconductor device, if under the same condition that D = 0.6, n = 1, and Vo = 380 V, the maximum voltage stress of the active switches in [15,16] and the proposed NIC are all 95 V, but the converters in [13,14] are up to 190 V and 170 V, respectively. That is, the proposed converter features an advantage over other high step-up converters.

5. Experimental Results

To validate the proposed NIC, a prototype based on the specifications summarized in Table 2 is designed, built, and tested. The types of semiconductor devices used in the prototype are given in Table 3. The power MOSFET, IRFSL4615PbF (International Rectifier, El Segundo, CA, USA), is selected to serve as active switches for controlling the current flow, of which maximum on-state resistance RDS(on) is 42 mΩ. The FEP16GT (Fairchild, Sunnyvale, CA, USA) is employed as diodes D1 and Do, of which forward voltage is 1.3 V and reverse recovery time is 50 ns. With regard to diodes D2 and D3, the hyper-fast rectifier VS-8ETH03-1PbF (Nichicon, Kyoto, Japan) is considered, which has 1.25 V forward voltage and 35 ns reverse recovery time. The voltage waveforms of active power switches and control signals are shown in Figure 4a,b, which indicate that the voltage across S1 and S2 are both near 65 V. This value also demonstrates a relatively low voltage stress across the active power semiconductor, as compared with other high step-up converters.
Figure 5a,d is the practical measurements of voltage waveforms of diodes Do, D1, D2 and D3, in turn, at the condition D = 0.62 and in CCM operation. Figure 5a illustrates that the maximum blocking voltage of Do is nearly 200 V. With respect to D1, its voltage stress approaches to 280 V, as shown in Figure 5b. Diodes D2 and D3 endure the same voltage of 130 V. In Figure 5, all the diode voltage stresses are in compliance with Equations (25)–(28).
Figure 6 shows the waveforms of input current and the corresponding control signals. It indicates that the magnitude of input ripple current is limited to less than 2 A. Figure 7 depicts the measured and simulated efficiencies from light load to full load. In the simulations, the considered conditions include forward voltage of diode, RDS(on) of MOSFET, copper loss of the coupled inductor, switching loss of MOSFET, and the equivalent resistance of diode. The maximum value of the measured efficiency is 93.7% at Po = 140 W. Figure 8 is the photo of test bench, in which PV simulator Chroma 62050H-600S (Taoyuan, Taiwan) serves as input source, electronic load Chroma 6320 draws power from the converter, and all waveforms are measured by oscilloscope KEYSIGHT DSOX4024A (Santa Rosa, CA, USA).

6. Conclusions

This paper proposes a NIC, which is applicable to PV systems or fuel cells for grid-connected high-power applications. The proposed converter utilizes the interleaved technique for current sharing to decrease input current ripples. Furthermore, the proposed converter can achieve a much higher voltage gain than a conventional interleaved converter. The operation principle and steady-state analysis of the proposed converter are described in detail. A 24 V/380 V 200 W prototype has been examined to demonstrate the feasibility of the proposed NIC. The maximum measured efficiency of the proposed converter is 93.7%. This value is a little lower than some of other high step-up converters. However, if the soft-switching technique is employed to make the switches operate at zero-voltage-switching or zero-current-switching condition, the efficiency of the proposed NIC can be improved significantly.

Acknowledgments

The authors would like to convey their appreciation for grant support from the Ministry of Science and Technology (MOST) of Taiwan under its grant with Reference Number MOST 105-3113-E-006-007.

Author Contributions

Chih-Lung Shen, Yan-Chi Lee and Po-Chieh Chiu conceived and designed the circuit. Yan-Chi Lee and Po-Chieh Chiu performed simulations, carried out the prototype, and analyzed data with guidance from Chih-Lung Shen. Chih-Lung Shen revised the manuscript for submission.

Conflicts of Interest

The authors declare that there is no conflict of interests regarding the publication of this paper.

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Figure 1. The main power circuit of the proposed novel interleaved converter (NIC). PV: photovoltaic.
Figure 1. The main power circuit of the proposed novel interleaved converter (NIC). PV: photovoltaic.
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Figure 2. Mode equivalents of the proposed NIC over one switching period. (a) Mode 1 (t0t1); (b) Mode 2 (t1t2); (c) Mode 3 (t2t3); (d) Mode 4 (t3t4); (e) Mode 5 (t4t5); (f) Mode 6 (t5t6); (g) Mode 7 (t6t7); (h) Mode 8 (t7t8); (i) Mode 9 (t8t9); and (j) Mode 10 (t9t10).
Figure 2. Mode equivalents of the proposed NIC over one switching period. (a) Mode 1 (t0t1); (b) Mode 2 (t1t2); (c) Mode 3 (t2t3); (d) Mode 4 (t3t4); (e) Mode 5 (t4t5); (f) Mode 6 (t5t6); (g) Mode 7 (t6t7); (h) Mode 8 (t7t8); (i) Mode 9 (t8t9); and (j) Mode 10 (t9t10).
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Figure 3. Conceptual key waveforms of the proposed NIC.
Figure 3. Conceptual key waveforms of the proposed NIC.
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Figure 4. Experimental waveforms of active power switches in CCM operation and at D = 0.62. (a) vDS1 and the corresponding control signals (vDS1: 50 V/div, vgs1 and vgs2: 10 V/div, time: 10 μs/div). (b) vDS2 and the corresponding control signals (vDS2: 50 V/div, vgs1 and vgs2: 10 V/div, time: 10 μs/div).
Figure 4. Experimental waveforms of active power switches in CCM operation and at D = 0.62. (a) vDS1 and the corresponding control signals (vDS1: 50 V/div, vgs1 and vgs2: 10 V/div, time: 10 μs/div). (b) vDS2 and the corresponding control signals (vDS2: 50 V/div, vgs1 and vgs2: 10 V/div, time: 10 μs/div).
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Figure 5. Experimental waveforms of diodes: (a) vDo (vDo: 100 V/div, vgs1 and vgs2: 20 V/div, time: 5 μs/div); (b) vD1 (vD1: 200 V/div, vgs1 and vgs2: 20 V/div, time: 5 μs/div); (c) vD2 (vD2: 100 V/div, vgs1 and vgs2: 20 V/div, time: 5 μs/div); (d) vD3 (vD3: 100 V/div, vgs1 and vgs2: 20 V/div, time: 5 μs/div).
Figure 5. Experimental waveforms of diodes: (a) vDo (vDo: 100 V/div, vgs1 and vgs2: 20 V/div, time: 5 μs/div); (b) vD1 (vD1: 200 V/div, vgs1 and vgs2: 20 V/div, time: 5 μs/div); (c) vD2 (vD2: 100 V/div, vgs1 and vgs2: 20 V/div, time: 5 μs/div); (d) vD3 (vD3: 100 V/div, vgs1 and vgs2: 20 V/div, time: 5 μs/div).
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Figure 6. Experimental waveforms of input current and corresponding control signals (iin: 5 A/div, vgs1 and vgs2: 20 V/div, time: 10 μs/div).
Figure 6. Experimental waveforms of input current and corresponding control signals (iin: 5 A/div, vgs1 and vgs2: 20 V/div, time: 10 μs/div).
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Figure 7. The measured and simulated efficiencies of the proposed NIC.
Figure 7. The measured and simulated efficiencies of the proposed NIC.
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Figure 8. Photo of the experimental setup.
Figure 8. Photo of the experimental setup.
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Table 1. Comparison among the proposed and other high step-up converters.
Table 1. Comparison among the proposed and other high step-up converters.
ItemsConverter Introduced in [13]Converter Introduced in [14]Converter Introduced in [15]Converter Introduced in [16]Proposed Converter
Voltage gain 1 + n 1 D 2 + n D n D 2 1 D 2 ( 1 + n ) 1 D 2 ( 1 + n ) 1 D 2 ( 1 + 2 n ) 1 D
Number of active switches42222
Number of diodes44644
Number of capacitors33544
Number of transformers11222
Number of inductors22000
Maximum voltage stress of active switch V o 1 + n V o 2 + n D n D 2 V o 2 ( 1 + n ) V o 2 ( 1 + n ) V o 2 ( 1 + n )
Maximum voltage stress of diodeVo 2 V o 2 + n D n D 2 ( 1 + 2 n ) V o 2 ( 1 + n ) n V o 1 + n ( 1 + n ) V o 1 + 2 n
Table 2. Specifications of the proposed converter.
Table 2. Specifications of the proposed converter.
SymbolsItemsValues
VinInput voltage24 V
VoOutput voltage380 V
PoOutput power200 W
DDuty cycle0.62
fsSwitching frequency50 kHz
nTransformer turns ratio1
LmMagnetizing inductance93 μH
LlkLeakage inductance1.9 μH
C1, C2, and C3Capacitances68 μF
CoOutput capacitance330 μF
Table 3. Semiconductor devices used in the prototype.
Table 3. Semiconductor devices used in the prototype.
ComponentsTypesAbsolute Maximum Ratings
D1 and DoFEP16GT400 V/16 A
D2 and D3VS-8ETH03-1PbF300 V/8 A
S1 and S2IRFSL4615PbF150 V/33 A
Energies EISSN 1996-1073 Published by MDPI AG, Basel, Switzerland RSS E-Mail Table of Contents Alert
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