Novel Interleaved Converter with Extra-High Voltage Gain to Process Low-Voltage Renewable-Energy Generation

This paper presents a novel interleaved converter (NIC) with extra-high voltage gain to process the power of low-voltage renewable-energy generators such as photovoltaic (PV) panel, wind turbine, and fuel cells. The NIC can boost a low input voltage to a much higher voltage level to inject renewable energy to DC bus for grid applications. Since the NIC has two circuit branches in parallel at frond end to share input current, it is suitable for high power applications. In addition, the NIC is controlled in an interleaving pattern, which has the advantages that the NIC has lower input current ripple, and the frequency of the ripple is twice the switching frequency. Two coupled inductors and two switched capacitors are incorporated to achieve a much higher voltage gain than conventional high step-up converters. The proposed NIC has intrinsic features such as leakage energy totally recycling and low voltage stress on power semiconductor. Thorough theoretical analysis and key parameter design are presented in this paper. A prototype is built for practical measurements to validate the proposed NIC.


Introduction
Since fossil fuels will be depleted in the next decades, development of green energy power generation systems becomes urgent.Among renewable energy generation systems, photovoltaic (PV), wind turbine, energy storage systems, and fuel cells attract a lot of attention [1][2][3][4].Nevertheless, low output voltage is their common shortcoming, especially in grid connection or electric vehicle (EV) applications.Therefore, a step-up converter to achieve high voltage gain is required.Conventional boost-type converters, like boost, buck-boost, and flyback, are able to step-up input voltage.However, in order to meet high-voltage gain requirements, they have to operate in heavy-duty ratio or adopt a high turns ratio transformer, which will decrease the conversion efficiency dramatically.Cascading more boost-type converters can avoid the above problem but issues of volume, cost, and efficiency emerge.Therefore, the high step-up DC/DC converter is the current design trend.
High step-up converters can be mainly classified into two categories: single-stage and interleaved structure.Single-stage topology incorporates coupled inductors and/or switched capacitors to complete high voltage gain.Even though its input voltage is boosted, a large magnitude of input current ripple occurs, limiting the converter power rating significantly [5][6][7][8].The interleaved converter has the ability of suppressing input current ripple by means of adding a parallel current path, which is a better choice for high power applications [9][10][11].However, the conventional interleaved converters have voltage gain limitation, which confines their applications in grid-tied systems.To overcome the aforementioned disadvantages, various high step-up interleaved converters were proposed in [12][13][14][15][16]; nevertheless, the shortcomings of lower voltage gain, higher voltage stress, and large component count still exist.An interleaved Boost converter combining voltage doubler is introduced in [12], while a coupled inductor is examined in [13].In order to achieve high voltage gain, the converters in [12,13] have to be operated at heavy-duty ratio or adopt a magnetic transform with high turns ratio, which results in low conversion efficiency or high voltage stress.Even though Lai et al. [14] proposed another high step-up converter, incorporating coupled inductor and switched capacitor, into an interleaved Boost configuration, the converter intrinsically has the demerits of higher voltage stress and sophisticated structure.An interleaved step-up converter with winding-cross-coupled inductors and voltage multiplier cells is presented in [15].This converter is composed of eight semiconductor devices and two three-winding coupled inductors.That is, a large number of power devices must be used.Tseng et al. [16] utilized the characteristics of forward, flyback, and interleaved converters to boost input voltage, but voltage gain still is limited.
This paper proposes a novel interleaved converter (NIC), which can accomplish a high voltage conversion ratio and is capable of processing low voltage, high power distributed resources.Its power stage is depicted in Figure 1.The proposed NIC mainly includes three parts: one interleaved-boost converter cell and two voltage multipliers.The interleaved-Boost converter cell is in charge of lowering input current ripple, increasing current rating, and primarily stepping input voltage.The two voltage multipliers can further stack up voltage level.The series voltage of the three parts determines the magnitude of output voltage.Since the proposed converter only uses two coupled inductors, three capacitors, four diodes, and two active power switches, it has a lower component count and a simple circuit structure.The advantages of the proposed NIC are summarized as follows: (1) The NIC can suppress input current ripple.(2) The energy stored in leakage inductance can be recycled.(3) The voltage stress of the semiconductor device is low enough so that a power switch with lower on-state resistance and smaller parasitic capacitance can be chosen.( 4) As compared with a conventional interleaved high step-up converter, the proposed NIC can achieve a much higher voltage gain under the same power component count.
in grid-tied systems.To overcome the aforementioned disadvantages, various high step-up interleaved converters were proposed in [12][13][14][15][16]; nevertheless, the shortcomings of lower voltage gain, higher voltage stress, and large component count still exist.An interleaved Boost converter combining voltage doubler is introduced in [12], while a coupled inductor is examined in [13].In order to achieve high voltage gain, the converters in [12,13] have to be operated at heavy-duty ratio or adopt a magnetic transform with high turns ratio, which results in low conversion efficiency or high voltage stress.Even though Lai et al. [14] proposed another high step-up converter, incorporating coupled inductor and switched capacitor, into an interleaved Boost configuration, the converter intrinsically has the demerits of higher voltage stress and sophisticated structure.An interleaved step-up converter with winding-cross-coupled inductors and voltage multiplier cells is presented in [15].This converter is composed of eight semiconductor devices and two three-winding coupled inductors.That is, a large number of power devices must be used.Tseng et al. [16] utilized the characteristics of forward, flyback, and interleaved converters to boost input voltage, but voltage gain still is limited.This paper proposes a novel interleaved converter (NIC), which can accomplish a high voltage conversion ratio and is capable of processing low voltage, high power distributed resources.Its power stage is depicted in Figure 1.The proposed NIC mainly includes three parts: one interleaved-boost converter cell and two voltage multipliers.The interleaved-Boost converter cell is in charge of lowering input current ripple, increasing current rating, and primarily stepping input voltage.The two voltage multipliers can further stack up voltage level.The series voltage of the three parts determines the magnitude of output voltage.Since the proposed converter only uses two coupled inductors, three capacitors, four diodes, and two active power switches, it has a lower component count and a simple circuit structure.The advantages of the proposed NIC are summarized as follows: (1) The NIC can suppress input current ripple.
(2) The energy stored in leakage inductance can be recycled.
(3) The voltage stress of the semiconductor device is low enough so that a power switch with lower on-state resistance and smaller parasitic capacitance can be chosen.(4) As compared with a conventional interleaved high step-up converter, the proposed NIC can achieve a much higher voltage gain under the same power component count.

Operation Principle of the Proposed Converter
In Figure 1, Lm1 and Lm2 denote the magnetizing inductances of the coupled inductors T1 and T2, respectively.The Lk1 and Lk2 represent the primary leakage inductances of T1 and T2, in turn, while Lk3 stands for the total leakage inductance at the secondary windings of both coupled inductors.Turns ratios of primary to secondary of T1 and T2 are denoted as n1 and n2, respectively.C1, C2, and C3 are the main capacitors employed in the circuit.It is supposed that the NIC operates in continuous conduction mode (CCM) and the two active switches S1 and S2 are controlled in

Operation Principle of the Proposed Converter
In Figure 1, L m1 and L m2 denote the magnetizing inductances of the coupled inductors T 1 and T 2 , respectively.The L k1 and L k2 represent the primary leakage inductances of T 1 and T 2 , in turn, while L k3 stands for the total leakage inductance at the secondary windings of both coupled inductors.Turns ratios of primary to secondary of T 1 and T 2 are denoted as n 1 and n 2 , respectively.C 1 , C 2 , and C 3 are the main capacitors employed in the circuit.It is supposed that the NIC operates in continuous conduction mode (CCM) and the two active switches S 1 and S 2 are controlled in interleaved manner.Accordingly, the operation of the NIC can be divided into ten operation modes over one switching cycle.The corresponding equivalents are illustrated in Figure 2, while Figure 3 depicts key waveforms.Analysis of the proposed NIC begins by making these assumptions: Energies 2016, 9, 871 3 of 12 (1) All parasitic capacitances and internal resistances are neglected.Moreover, all diodes are ideal.(2) The voltages across capacitors C 1 , C 2 , C 3 , and C o are time-invariant.(3) Magnetizing inductances, L m1 and L m2 , are much larger than the leakage inductances L lk1 , L lk2 and L lk3 .(4) The switching period is T s .Both switches are closed for time DT s and open for (1 − D)T s .
Mode 1 (t 0 -t 1 ) (Figure 2a): This mode is the initial mode of the all operation procedures.During this time interval, both active switches S 1 and S 2 are closed.Diodes D 1 , D 3 and D o are in reverse-bias, but D 2 is forward-biased.Input voltage V in is across the primaries of T 1 and T 2 directly.Then, the current flowing through S 2 starts increasing linearly from zero, while the switch current i S1 , having an initial value determined by the end of Mode 10, also increases linearly.In addition, the energy remained in L k3 will be recycled to C 2 via D 2 .At the time that the diode current i D2 drops to zero, and this mode ends.
Mode 2 (t 1 -t 2 ) (Figure 2b): During this time interval, active switches S 1 and S 2 are still closed, and V in remains across the two coupled inductors .Thus, the current i Lm1 and i Lm2 are continuously increasing.In this mode, the current flowing through leakage inductances i lk1 and i lk2 are equal to magnetizing-inductance currents i Lm1 and i Lm2 , respectively.This mode ends when the switch S 1 is turned off.
Mode 3 (t 2 -t 3 ) (Figure 2c): In this mode, S 2 remains in on state but S 1 becomes off.Diodes D 2 , D 3 and D o are reversely-biased but D 1 is in forward-bias.The V in , L m1 , L k1 and C 2 dump energy to L k3 and C 1 via D 1 and S 2 , so the current flowing through D 1 and S 2 increases.This mode finishes when D 3 becomes forward-biased and L k3 starts to release energy.
Mode 4 (t 3 -t 4 ) (Figure 2d): Over the whole interval of Mode 4, S 2 is still kept in on state while S 1 in off state.The D 1 remains forward-biased and D 3 becomes closed.Meanwhile, both diodes D 2 and D o continue the off status.Magnetizing-inductance L m1 pumps energy to C 3 via the coupled inductor.Capacitor C 1 is charged continuously, the circuit behavior of which is the same as in the previous mode.When the leakage-inductance L k1 releases over its stored energy, i D1 will drop to zero.That is, diode D 1 becomes reversely-biased and this mode ends.
Mode 5 (t 4 -t 5 ) (Figure 2e): During this time interval, S 2 is still closed and S 1 is open.Diodes D 1 , D 2 and D o are reversely-biased but D 3 is in forward-bias.V in and L m1 supply energy to C 3 simultaneously by the T 1 and T 2 in turn.This mode finishes as S 1 is turned on.
Mode 6 (t 5 -t 6 ) (Figure 2f): During this mode, S 1 and S 2 are both in on state.Diodes D 1 , D 2 and D o are off, but D 3 is on.L m1 starts to draw energy from V in .The stored energy in L k3 will releases to C 3 through D 3 .This mode sustains until i D3 decreases to zero.
Mode 7 (t 6 -t 7 ) (Figure 2g): During this time interval, S 1 and S 2 are both in on state, but D 1 , D 2 , D 3 and D o are all reversely-biased.Since the primaries of the two coupled inductors are in parallel, V in will supply energy to L m1 , L m2 , L k1 and L k2 .Therefore, i Lm1 and i Lm2 will increase linearly, which are identical to i S1 and i S2 , respectively.This mode is ended when S 2 is turned off.
Mode 8 (t 7 -t 8 ) (Figure 2h): During this time interval, S 1 remains in on state, but S 2 in off state.D 1 , D 2 and D 3 are off, but D o is on.The L m2 starts to release its stored energy so that the current flowing through L m2 decays.Meanwhile, the current i lk3 increases.The input V in and the voltages across L m2 , L k2 , C 1 , and C 3 will be stacked up to supply C o .This mode terminates when L k3 starts to charge C 2 .
Mode 9 (t 8 -t 9 ) (Figure 2i): In this mode, S 1 is still closed and S 2 is open.The V in will charge C 2 via coupled inductor T 1 ; meanwhile, the energy stored in L m2 will also be transferred to the secondary of T 2 for powering C 2 .Therefore, i Lm2 drops and C o keeps on charging.In Mode 9, the energy in L k2 is recycled to the output.This mode ends as i lk2 falls to zero.
Mode 10 (t 9 -t 10 ) (Figure 2j): The diode D o will become reversely biased when i lk2 drops to zero.In Mode 10, S 1 proceeds with on-state conducting and S 2 remains in off state.With respect to diode status, the diodes D 1 , D 3 and D o are in reverse-bias and D 2 is still in on state.The V in and L m2 will forward energy to C 2 through the coupled inductors T 1 and T 2 , respectively.This mode ends when S 2 is turned on again, and then the operation returns to Mode 1.
forward energy to C2 through the coupled inductors T1 and T2, respectively.This mode ends when S2 is turned on again, and then the operation returns to Mode 1.

Voltage Gain Derivation
Voltage gain is the most important characteristic of a high step-up converter.As the analysis in Section 2 shows, the switched capacitors C1 and C3 have the benefit of voltage stacking for achieving extra-high voltage gain.This section focuses on the voltage gain derivation of the proposed NIC.For high power applications, the converter is designed in CCM.Assumptions made in Section 2 are also adopted for simplifying the derivation.Furthermore, the coupling coefficients of the coupled inductors are both supposed at unity; that is, there is no leakage inductance.
According to the description for Mode 4 in Section 2, C1 is charged by Vin, C2, T1, and T2, whereas C3 is charged by the two coupled inductors.Referring to Mode 9 in Section 2, if the leakage inductances are ignored, the output port is supplied by Vin, T1, T2, C1, and C3.Hence, to determine the voltage gain, Vo/Vin, the relationships of VC1, VC2 and VC3 in terms of Vin have to be found in advance.

The Ratio of VC3 to Vin
As S1 is closed, Vin will supply energy to Lm1.After an on-time interval DTs, the change in iLm1 can be estimated as: In the opposite switch statuses, that is, S1 off and S2 on, the energy stored in Lm1 will be transferred to the secondary of the coupled inductor T1 and then be forwarded to C3 by the loop of N2-N12-D3-C2.In addition, the source voltage Vin also supplies energy to C3 via T2.By Kirchhoffʹs voltage law (KVL) and from the closed loop N2-N12-D3-C2, it can be found that:

Voltage Gain Derivation
Voltage gain is the most important characteristic of a high step-up converter.As the analysis in Section 2 shows, the switched capacitors C 1 and C 3 have the benefit of voltage stacking for achieving extra-high voltage gain.This section focuses on the voltage gain derivation of the proposed NIC.For high power applications, the converter is designed in CCM.Assumptions made in Section 2 are also adopted for simplifying the derivation.Furthermore, the coupling coefficients of the coupled inductors are both supposed at unity; that is, there is no leakage inductance.
According to the description for Mode 4 in Section 2, C 1 is charged by V in , C 2 , T 1 , and T 2 , whereas C 3 is charged by the two coupled inductors.Referring to Mode 9 in Section 2, if the leakage inductances are ignored, the output port is supplied by V in , T 1 , T 2 , C 1 , and C 3 .Hence, to determine the voltage gain, V o /V in , the relationships of V C1 , V C2 and V C3 in terms of V in have to be found in advance.

The Ratio of V C3 to V in
As S 1 is closed, V in will supply energy to L m1 .After an on-time interval DT s , the change in i Lm1 can be estimated as: In the opposite switch statuses, that is, S 1 off and S 2 on, the energy stored in L m1 will be transferred to the secondary of the coupled inductor T 1 and then be forwarded to C 3 by the loop of N 2 -N 12 -D 3 -C 2 .In addition, the source voltage V in also supplies energy to C 3 via T 2 .By Kirchhoff's voltage law (KVL) and from the closed loop N 2 -N 12 -D 3 -C 2 , it can be found that: Since voltage across L m2 is V in , rewriting Equation (2) becomes: From Equation (3), the current change in L m1 after a switch-off interval (1 − D)T s , is found by: In steady state, over one switching cycle the net change of inductor current i Lm1 is zero.That is: Rearranging the above equation can obtain the voltage of V C3 in terms of V in as follows:

The Ratio of V C2 to V in
With respect to the ratio of V C2 to V in , the current change in L m2 has to be dealt with first.The current flowing through L m2 increases when S 2 is closed.After DT s , the change (∆i Lm2 ) on can be expressed as: when switch S 2 is open for (1 − D)T s and S 1 is in on state.The energy stored in L m2 will be released to C 2 by coupled inductor T 2 as well as the loop of N 12 -N 2 -C 3 -D 2 .Therefore: In Equation ( 8), the voltage across L m1 equals V in , thus: The total current drop in L m2 can be found by: In steady state, over one switching cycle the net change of the inductor current i Lm2 is zero.That is: Thus, the voltage of V C2 in terms of V in is as follows:

The Ratio of V C1 to V in
While S 1 is open and S 2 is closed, from the current flow path of V in -L m1 -D 1 -C 2 -N 2 -N 12 -C 1 -S 2 , the following relationship can be found: Since the voltage across L m2 in Equation ( 13) is V in , the current decrease on L m1 is derived as: Energies 2016, 9, 871 7 of 12 In addition, the total amount of current increase on L m1 over the S 1 -closed interval has been depicted as Equation ( 1).This increment is equal to the decrease amount in i Lm1 over one switching cycle, which yields: Rearranging Equation ( 15) results in:

The Ratio of V o to V in
Under the condition that S 1 is closed and S 2 is in off state, the voltage V Lm2 can be determined by applying KVL to the loop enclosed by V in , L m2 , C 1 , N 12 , N 2 , C 3 , D o , and C o .Therefore: Thus, the decreased quantity of i Lm2 is expressed as: From the increment (∆i Lm2 ) on in Equation ( 7) and the condition (∆i Lm2 ) off = (∆i Lm2 ) on , the following relationship holds: After simplifying, the following equation can be obtained: Substituting Equations ( 6) and ( 16) into Equation (20) can obtain the voltage gain of the proposed converter, V o /V in , and yields:

Voltage Stress of Power Component
This section begins with the determination of voltage stresses across S 1 and S 2 .Supposing that all leakage inductances are neglected, Modes 4 and 9 in Section 2 will therefore dominate the estimation of voltage stress.When S 1 is open, from Figure 2d it can be found that the blocking voltage of S 1 , V DS1,stress , can be expressed as With respect to active switch S 2 , its blocking voltage, V DS2,stress , can be determined from Figure 2i and the following relationship can be found: Energies 2016, 9, 871 8 of 12 Equations ( 22) and ( 23) reveal that the voltage stresses of S 1 and S 2 are identical and irrelative to turns ratio of coupled inductor.Voltage stresses across active switches only depend on duty ratio and input voltage.Rewriting Equations ( 22) and ( 23) in terms of V o results in: Equation ( 24) implies that the voltage stresses of S 1 and S 2 are much lower than output voltage.Considering the statues of S 1 on and S 2 off, the voltage across D 1 and D 3 can be determined as follows: and: With respect to D 2 and D o , their voltage stresses are calculated during the time interval of S 1 off and S 2 on.The corresponding voltage stress calculations can be: and: According to Equations ( 25)-( 28), it can be observed that D 1 endures the highest voltage stress among the four diodes.Table 1 summaries the comparison between NIC and other high step-up converters proposed in [13][14][15][16].If the duty cycle D is 0.6, and the transformer turns ratio n is 1, the proposed converter can boost 15-times input voltage.However, the voltage gains of the converters in [13][14][15][16] are 5, 5.6, 10, and 10, respectively.It is obvious that the proposed NIC can exceed these high step-up converters in voltage gain.With respect to voltage stress across semiconductor device, if under the same condition that D = 0.6, n = 1, and V o = 380 V, the maximum voltage stress of the active switches in [15,16] and the proposed NIC are all 95 V, but the converters in [13,14] are up to 190 V and 170 V, respectively.That is, the proposed converter features an advantage over other high step-up converters.

Experimental Results
To validate the proposed NIC, a prototype based on the specifications summarized in Table 2 is designed, built, and tested.The types of semiconductor devices used in the prototype are given in Table 3.The power MOSFET, IRFSL4615PbF (International Rectifier, El Segundo, CA, USA), is selected to serve as active switches for controlling the current flow, of which maximum on-state resistance Energies 2016, 9, 871 9 of 12 R DS(on) is 42 mΩ.The FEP16GT (Fairchild, Sunnyvale, CA, USA) is employed as diodes D 1 and D o , of which forward voltage is 1.3 V and reverse recovery time is 50 ns.With regard to diodes D 2 and D 3 , the hyper-fast rectifier VS-8ETH03-1PbF (Nichicon, Kyoto, Japan) is considered, which has 1.25 V forward voltage and 35 ns reverse recovery time.The voltage waveforms of active power switches and control signals are shown in Figure 4a,b, which indicate that the voltage across S 1 and S 2 are both near 65 V.This value also demonstrates a relatively low voltage stress across the active power semiconductor, as compared with other high step-up converters.

Experimental Results
To validate the proposed NIC, a prototype based on the specifications summarized in Table 2 is designed, built, and tested.The types of semiconductor devices used in the prototype are given in Table 3.The power MOSFET, IRFSL4615PbF (International Rectifier, El Segundo, CA, USA), is selected to serve as active switches for controlling the current flow, of which maximum on-state resistance RDS(on) is 42 mΩ.The FEP16GT (Fairchild, Sunnyvale, CA, USA) is employed as diodes D1 and Do, of which forward voltage is 1.3 V and reverse recovery time is 50 ns.With regard to diodes D2 and D3, the hyper-fast rectifier VS-8ETH03-1PbF (Nichicon, Kyoto, Japan) is considered, which has 1.25 V forward voltage and 35 ns reverse recovery time.The voltage waveforms of active power switches and control signals are shown in Figure 4a,b, which indicate that the voltage across S1 and S2 are both near 65 V.This value also demonstrates a relatively low voltage stress across the active power semiconductor, as compared with other high step-up converters.Figure 6 shows the waveforms of input current and the corresponding control signals.It indicates that the magnitude of input ripple current is limited to less than 2 A. Figure 7 depicts the measured and simulated efficiencies from light load to full load.In the simulations, the considered conditions include forward voltage of diode, RDS(on) of MOSFET, copper loss of the coupled inductor, switching loss of MOSFET, and the equivalent resistance of diode.The maximum value of the measured efficiency is 93.7% at Po = 140 W. Figure 8 is the photo of test bench, in which PV simulator Chroma 62050H-600S (Taoyuan, Taiwan) serves as input source, electronic load Chroma 6320 draws power from the converter, and all waveforms are measured by oscilloscope KEYSIGHT DSOX4024A (Santa Rosa, CA, USA).  Figure 6 shows the waveforms of input current and the corresponding control signals.It indicates that the magnitude of input ripple current is limited to less than 2 A. Figure 7 depicts the measured and simulated efficiencies from light load to full load.In the simulations, the considered conditions include forward voltage of diode, R DS(on) of MOSFET, copper loss of the coupled inductor, switching loss of MOSFET, and the equivalent resistance of diode.The maximum value of the measured efficiency is 93.7% at P o = 140 W. Figure 8 is the photo of test bench, in which PV simulator Chroma 62050H-600S (Taoyuan, Taiwan) serves as input source, electronic load Chroma 6320 draws power from the converter, and all waveforms are measured by oscilloscope KEYSIGHT DSOX4024A (Santa Rosa, CA, USA). Figure 6 shows the waveforms of input current and the corresponding control signals.It indicates that the magnitude of input ripple current is limited to less than 2 A. Figure 7 depicts the measured and simulated efficiencies from light load to full load.In the simulations, the considered conditions include forward voltage of diode, RDS(on) of MOSFET, copper loss of the coupled inductor, switching loss of MOSFET, and the equivalent resistance of diode.The maximum value of the measured efficiency is 93.7% at Po = 140 W. Figure 8 is the photo of test bench, in which PV simulator Chroma 62050H-600S (Taoyuan, Taiwan) serves as input source, electronic load Chroma 6320 draws power from the converter, and all waveforms are measured by oscilloscope KEYSIGHT DSOX4024A (Santa Rosa, CA, USA).

Conclusions
This paper proposes a NIC, which is applicable to PV systems or fuel cells for grid-connected high-power applications.The proposed converter utilizes the interleaved technique for current sharing to decrease input current ripples.Furthermore, the proposed converter can achieve a much higher voltage gain than a conventional interleaved converter.The operation principle and steady-state analysis of the proposed converter are described in detail.A 24 V/380 V 200 W prototype has been examined to demonstrate the feasibility of the proposed NIC.The maximum measured efficiency of the proposed converter is 93.7%.This value is a little lower than some of other high step-up converters.However, if the soft-switching technique is employed to make the switches operate at zero-voltage-switching or zero-current-switching condition, the efficiency of the proposed NIC can be improved significantly.

Conclusions
This paper proposes a NIC, which is applicable to PV systems or fuel cells for grid-connected high-power applications.The proposed converter utilizes the interleaved technique for current sharing to decrease input current ripples.Furthermore, the proposed converter can achieve a much higher voltage gain than a conventional interleaved converter.The operation principle and steady-state analysis of the proposed converter are described in detail.A 24 V/380 V 200 W prototype has been examined to demonstrate the feasibility of the proposed NIC.The maximum measured efficiency of the proposed converter is 93.7%.This value is a little lower than some of other high step-up converters.However, if the soft-switching technique is employed to make the switches operate at zero-voltage-switching or zero-current-switching condition, the efficiency of the proposed NIC can be improved significantly.

Conclusions
This paper proposes a NIC, which is applicable to PV systems or fuel cells for grid-connected high-power applications.The proposed converter utilizes the interleaved technique for current sharing to decrease input current ripples.Furthermore, the proposed converter can achieve a much higher voltage gain than a conventional interleaved converter.The operation principle and steady-state analysis of the proposed converter are described in detail.A 24 V/380 V 200 W prototype has been examined to demonstrate the feasibility of the proposed NIC.The maximum measured efficiency of the proposed converter is 93.7%.This value is a little lower than some of other high step-up converters.However, if the soft-switching technique is employed to make the switches operate at zero-voltage-switching or zero-current-switching condition, the efficiency of the proposed NIC can be improved significantly.

Figure 1 .
Figure 1.The main power circuit of the proposed novel interleaved converter (NIC).PV: photovoltaic.

Figure 1 .
Figure 1.The main power circuit of the proposed novel interleaved converter (NIC).PV: photovoltaic.

Figure 3 .
Figure 3. Conceptual key waveforms of the proposed NIC.

Figure 3 .
Figure 3. Conceptual key waveforms of the proposed NIC.

Figure 5a ,
Figure 5a,d is the practical measurements of voltage waveforms of diodes Do, D1, D2 and D3, in turn, at the condition D = 0.62 and in CCM operation.Figure 5a illustrates that the maximum blocking voltage of Do is nearly 200 V.With respect to D1, its voltage stress approaches to 280 V, as shown in Figure 5b.Diodes D2 and D3 endure the same voltage of 130 V.In Figure 5, all the diode voltage stresses are in compliance with Equations (25)-(28).

Figure
Figure 5a,d is the practical measurements of voltage waveforms of diodes D o , D 1 , D 2 and D 3 , in turn, at the condition D = 0.62 and in CCM operation.Figure 5a illustrates that the maximum blocking voltage of D o is nearly 200 V.With respect to D 1 , its voltage stress approaches to 280 V, as shown in Figure 5b.Diodes D 2 and D 3 endure the same voltage of 130 V.In Figure 5, all the diode voltage stresses are in compliance with Equations (25)-(28).

Figure 7 .Figure 8 .
Figure 7.The measured and simulated efficiencies of the proposed NIC.

Figure 7 .
Figure 7.The measured and simulated efficiencies of the proposed NIC.

Figure 8 .
Figure 8. Photo of the experimental setup.

Table 1 .
Comparison among the proposed and other high step-up converters.

Table 2 .
Specifications of the proposed converter.

Table 3 .
Semiconductor devices used in the prototype.

Table 2 .
Specifications of the proposed converter.

Table 3 .
Semiconductor devices used in the prototype.