High-Level Synthesis (HLS)-Enabled Field-Programmable Gate Array (FPGA) Algorithms for Latency-Critical Plasma Diagnostics and Neural Trigger Prototyping in Next-Generation Energy Projects

Abstract

Large-scale advanced energy systems, including fusion devices, high-power plasma sources, and accelerator-driven energy platforms, increasingly depend on real-time, hardware-level data processing for diagnostics, control, and protection. In such installations, ultra-low latency, deterministic throughput, and multi-decade operational lifetimes are not optional design goals but strict system-level requirements. While similar timing constraints exist in high-energy physics infrastructures, energy applications place a stronger emphasis on long-term stability, maintainability, and reproducibility of digital signal processing pipelines. This work investigates whether high-level synthesis (HLS) provides a practical and sustainable design methodology for implementing both classical pattern-based and compact neural network (NN) trigger logic on Field-Programmable Gate Arrays (FPGAs) under realistic energy-system constraints. Using representative commercial toolchains (Intel HLS and hls4ml) as reference workflows, we demonstrate the capabilities of fixed-point, fully pipelined streaming architectures, while also identifying critical shortcomings of pragma-driven HLS approaches in terms of architecture transparency, long-term portability, and systematic multi-objective design-space exploration, all of which are crucial for long-lived energy projects and plasma diagnostic systems. These limitations directly motivate the development of a custom, vendor-agnostic, extensible HLS framework (PyHLS), specifically oriented toward deterministic latency, reproducibility, and physics-grade verification demands of advanced energy infrastructures. Gas Electron Multipliers (GEMs) are modern gaseous detectors increasingly employed in plasma diagnostics, radiation monitoring, and high-power energy experiments, where high rate capability, fine spatial resolution, and radiation tolerance are required. Their massively parallel signal structure and continuous data streams make GEMs a representative and demanding benchmark for FPGA-based real-time trigger and preprocessing systems in energy-related environments. The primary objective of this study is to establish a pragmatic technological baseline, demonstrating that contemporary HLS workflows can reliably support both template-based and neural inference-based trigger architectures within strict timing, resource, and power constraints typical for advanced energy installations. Furthermore, we outline a scalable development path toward multi-channel and two-dimensional (pixelated) GEM readout architectures, directly applicable to fusion diagnostics, plasma accelerators, beam–plasma interaction studies, and radiation-hard energy monitoring platforms. Although the proposed methodology remains fully transferable to large-scale physics trigger systems, its principal relevance is directed toward real-time diagnostics and protection layers in next-generation energy systems.

1. Introduction

The global energy landscape is undergoing a profound transformation driven by the growing demand for clean, sustainable, and high-density energy sources. Renewable energy technologies such as wind and solar power are playing an increasingly important role in reducing greenhouse gas emissions and diversifying the energy mix. Nevertheless, their inherently intermittent nature, dependence on meteorological conditions, and comparatively low areal power density impose system-level challenges that must be addressed through grid reinforcement, large-scale energy storage, and complementary firm generation. These characteristics do not diminish the value of renewables. Instead, they highlight the need for a balanced and integrated energy strategy in which different technologies operate synergistically.

Conventional power generation based on fossil fuels has historically provided stability and dispatchability, yet it is constrained by finite resource availability and environmental considerations. As many regions pursue deep decarbonization, attention is increasingly directed toward energy sources capable of delivering low emissions, high capacity factors, and long-term scalability. In this context, identifying reliable pathways for large-scale, carbon-neutral electricity production remains one of the central scientific and engineering challenges of the 21st century.

Among emerging technologies, controlled thermonuclear fusion represents a particularly promising complement to established low-carbon solutions. Fusion offers a virtually inexhaustible fuel supply derived from isotopes present in seawater and lithium reserves, while producing no CO₂ and minimal long lived radioactive waste and operating with inherent safety characteristics. Rather than competing with renewable energy resources, fusion is widely viewed as a potential firm, high-density energy source that could provide the continuous power needed to stabilize a highly renewable grid.

Tokamak-based fusion devices, such as ITER and its satellite experiments, represent the forefront of global efforts to realize practical fusion energy. These facilities confine high-temperature plasma using strong magnetic fields to sustain fusion reactions under extreme thermodynamic conditions. However, the same conditions that make fusion feasible also give rise to complex plasma phenomena, including instabilities, impurity transport, and edge-localized modes, which can degrade performance or damage internal components. Continuous, high-speed diagnostics and real-time feedback control are therefore essential to maintain plasma stability and optimize energy output.

Plasma contamination, transient events, and fast-growing instabilities must be detected and mitigated within microseconds to prevent disruptions and preserve stable operation. This necessitates diagnostic systems capable of processing large volumes of data with deterministic latency directly within the data acquisition electronics. Among the detectors used for such high-speed diagnostics, the Gas Electron Multiplier (GEM) plays a particularly significant role. It is a gaseous particle detector in which signals are generated by amplifying primary electrons inside microscopic holes of thin, metal-coated polymer foils placed in an electric field. A typical configuration consists of a drift region where the passage of a charged particle ionizes the gas followed by one or more GEM foils (often arranged as a triple-GEM stack for stable high gain), and an induction gap above a segmented readout anode. The primary electrons drift toward the GEM holes, where strong local electric fields initiate avalanche multiplication. The resulting charge is then transferred and collected on the readout electrodes strips, pads, or pixels, allowing precise reconstruction of position and timing.

GEM detectors combine robustness, high spatial and temporal resolution, and the ability to operate in harsh radiation environments. They are therefore well suited for monitoring impurity transport, plasma–wall interactions, and energetic particle losses in fusion devices, providing the detailed temporal and spatial insights required for real-time plasma control and energy optimization [1,2,3,4,5,6,7,8].

To contextualize the diagnostic role of GEM systems within a future fusion plant, Figure 1 shows a simplified schematic of a tokamak-based fusion power station. The fusion core is surrounded by a tritium breeding blanket and a divertor system responsible for heat exhaust and impurity control. Helium coolant extracts the fusion heat and transfers it to a secondary water loop powering a steam turbine, closely mirroring conventional nuclear power plant architecture.

The adoption of large-area, multi-channel GEM systems introduces substantial challenges in data volume and throughput. Each detector produces thousands of high-frequency signals that must be analyzed in real time to extract relevant physical information. Efficient triggering and classification mechanisms are therefore indispensable. Real-time signal classification and triggering are integral to modern plasma diagnostics and large-scale physics experiments, where microsecond-level latency determines whether critical events are captured or missed.

These requirements impose the need for hardware-based accelerators, with field-programmable gate arrays (FPGAs) being particularly attractive due to their ability to implement highly parallelized pipelines, deterministic execution, and reconfigurable architectures [10,11,12,13,14,15,16]. In such FPGA-based systems, trigger logic plays a key role in identifying and selecting relevant events in real time while rejecting the vast majority of uninteresting background data. The efficiency and responsiveness of the entire data acquisition chain strongly depend on the trigger design and its implementation.

Traditionally, many trigger systems have relied on pattern-based methods [3], in which a normalized reference template of a detector signal tail is compared against incoming waveforms. For detectors such as GEMs, whose pulses exhibit characteristic exponential or semi-exponential decays, this approach offers low complexity, deterministic timing, and direct mapping to FPGA logic. By exploiting metrics such as correlation or least-square error, pattern matching enables robust real-time identification of signals that correspond to known physics signatures. However, while efficient, these template-driven strategies are limited: they assume a fixed or slowly varying pulse shape and cannot generalize well to the diverse or noisy morphologies observed in real experimental conditions.

To address these limitations, machine learning approaches, particularly neural networks (NNs), have emerged as powerful tools for generalized signal classification [8,11]. NNs can extract invariant features and learn directly from raw or partially processed waveforms, offering adaptability to non-standard or overlapping signals at the expense of higher computational cost and design complexity.

Bridging these algorithmic and hardware domains, high-level synthesis (HLS) provides a practical framework for describing and optimizing FPGA-based implementations [17,18,19,20,21]. In this study, two complementary trigger architectures are developed. The first, a pattern-based trigger, is specified, optimized, and deployed using the PyHLSframework, which employs a metamodel to explore pipelining, loop unrolling, and memory banking while reducing manual HDL effort during design-space exploration [22,23,24]. The second, a neural-network trigger, is implemented using the Intel HLS Compiler [25,26] and hls4ml [27] toolchains to demonstrate inference-based FPGA flows. This dual-track approach enables direct comparison of deterministic and data-driven methods under realistic latency and resource constraints.

The remainder of the paper is organized as follows. Section 2 summarizes detector signal characteristics and preprocessing. Section 3 details the pattern-based classifier and its FPGA implementation using PyHLS v0.1.3. Section 4 presents the CNN-based classifier and its FPGA realization using Intel HLS Compiler v24.2.0 and hls4ml v1.1.0. Section 5 discusses mapping strategies, design-space exploration, and optimization knobs across both flows. Section 6 presents the main contributions of this work. Finally, Section 7 concludes with directions for extending PyHLS toward fully integrated NN support.

2. Detector Signals and Data Characteristics

The design of real-time classification and trigger algorithms must begin with a careful analysis of the detector signal and its front-end conditioning. In this work, we focus on Gas Electron Multiplier (GEM) detectors, widely used in plasma diagnostics and high-energy physics for their fine spatial resolution, fast response, and robustness in harsh conditions. The primary GEM output is a short charge impulse at the readout electrode. This impulse is integrated and converted to voltage by a charge-sensitive preamplifier, then shaped by a cascade that can be viewed as consecutively applied low-pass sections, optionally including baseline restoration and an explicit anti-alias stage. The shaping broadens the narrow impulse into a pulse with a well-defined peaking time and decay constant while effectively suppressing high-frequency disturbances and reducing the measured noise prior to digitization. The conditioned signal is finally sampled by an analog-to-digital converter (ADC) typically operating in the 50–100 MHz range (for the WEST experiment, 80 MHz was used). Consequently, the analog chain from preamplifier through low-pass shaping and anti-alias filtering defines the rise time, tail characteristics, and signal-to-noise ratio perceived by digital algorithms.

The typical GEM waveform is characterized by a sharp rising edge followed by a decaying tail that can often be approximated by an exponential or semi-exponential function. The duration and amplitude of these tails depend on detector geometry, operating voltage, and gas mixture, but the overall structure remains recognizable. This characteristic shape allows pattern-based classification methods to detect valid events, i.e., signals corresponding to real physical interactions in the detector, such as the passage of charged particles, while ignoring spurious signals caused by electronic noise, cross-talk between channels, or overlapping pulses (pile-up). By comparing the incoming waveform to a normalized reference template of the expected decay, these methods can efficiently discriminate true physical events from background fluctuations, achieving high detection reliability with minimal computational overhead.

However, real experimental data introduces significant variability. Noise from front-end electronics, cross-talk between neighboring channels, baseline fluctuations, and overlapping events (pile-up) can all distort the idealized pulse shape. In high-rate operation, pile-up becomes a recurrent problem when multiple charge clusters arrive within the shaping time of the front-end electronics. Their temporal overlap causes partial signal superposition, resulting in apparent amplitude variations, distorted rising edges, and elongated decay tails. Such effects complicate event discrimination and can obscure the temporal separation of consecutive interactions. Accurate timing and amplitude reconstruction therefore require dedicated correction or pulse separation techniques that increase processing complexity and latency.

In addition, different operational regimes of the detector may yield pulses with non-standard morphologies that deviate from the expected exponential decay. In such cases, fixed-shape templates become less effective, leading to higher rates of false positives or missed detections. To mitigate these distortions, a preprocessing stage is applied before classification. Typical steps include baseline subtraction, amplitude normalization, and temporal windowing to focus on the region of interest. For multi-channel GEM systems, cross-channel alignment is also necessary to ensure synchronous analysis of correlated signals.

After preprocessing, the signals can be analyzed by either deterministic, template-based matching methods or adaptive, data-driven approaches. While normalization improves the robustness of pattern-based detection, it cannot fully account for nonlinear distortions, pile-up effects, or waveform anomalies. Machine-learning models such as convolutional neural networks (CNNs), on the other hand, can learn directly from raw or partially processed waveforms, enabling recognition of a broader variety of signal shapes and distortions. The methods discussed in the following sections are designed to address these challenges by combining deterministic and adaptive strategies under strict real-time constraints.

In summary, the morphology of GEM signals, particularly their consistent decay tails, supports the use of deterministic, pattern-based classification. However, variability introduced by noise, pile-up, and non-ideal operating conditions motivates complementary adaptive techniques. A precise understanding of these properties is crucial for FPGA implementations that must balance latency, accuracy, and resource usage in real-time trigger systems.

The diagnostic system is intended to operate within a real-time feedback loop, which imposes the following requirements:

• Low latency: End-to-end processing must meet tight control-loop budgets to support real-time actuation.
• High throughput: Higher spatial resolution and sampling rates increase channel counts and sample volumes, requiring sustained bandwidth across the acquisition and processing pipeline.
• Lossless transport: Streaming raw data to specialized FPGA compute nodes preserves information for maximal analysis quality.
• FPGA-efficient algorithms: Implementations should minimize resource usage and development time while maintaining numerical fidelity in complex digital pipelines.
• Portability: Designs should be easily adaptable across legacy and modern FPGA families from multiple vendors.

In view of next-generation fusion devices (e.g., ITER), existing diagnostic stacks are unlikely to satisfy all these constraints without substantial redesign. Future systems must be capable of recording and processing detector data with much higher efficiency, precision, and determinism. Achieving accurate, low-latency inference directly within the control loop is essential not only for maintaining plasma stability, but also for ensuring the reliable and continuous generation of fusion energy under operational reactor conditions. These challenges motivate the development of new real-time methods that combine advanced signal processing and hardware acceleration, forming the foundation for the architectures discussed in the following sections.

3. Pattern-Based Classification Method

The signal characteristics discussed in the previous section directly motivate the use of deterministic, pattern-based classification, which exploits the repeatable morphology of GEM pulses for real-time triggering. Modern diagnostic and trigger systems frequently require fast, deterministic signal processing performed directly within the data acquisition electronics. In such environments, FPGA-based implementations of digital signal processing (DSP) algorithms are increasingly adopted due to their ability to deliver low-latency, highly parallel, and resource-efficient computations [3].

This section presents a classification method based on a normalized reference pulse shape, enabling real-time identification of detector events and the separation of overlapping signals, an essential capability in multichannel measurement systems such as GEM-based plasma diagnostics.

The proposed approach is motivated by the observation that waveforms acquired from ADC channels exhibit nearly identical temporal shapes. Figure 2 shows representative GEM detector signals recorded across multiple channels. The rising edge and exponential-like decay remain consistent between channels, differing primarily in amplitude. This property makes it possible to define a normalized reference pulse, typically scaled by amplitude, that can be matched to the observed waveform in real time.

When multiple pulses overlap, the observed waveform can be expressed as a superposition of individual pulses scaled by their respective amplitudes. In typical conditions, a single pulse lasts about 20 clock cycles (see Figure 2), and the rate of overlapping pulses usually does not exceed 20% of events due to the use of appropriate beam collimation and helium buffer. The classification task then becomes equivalent to detecting local maxima, scaling the normalized tail, and subtracting the reconstructed component from the composite signal. An iterative procedure enables the recovery of multiple overlapping pulses.

The reconstruction algorithm relies on a predefined normalized tail $Z_k$ for channel k, scaled by an estimated charge $Q_k$. The procedure can be summarized in Listing 1:

Listing 1. Pattern-based reconstruction algorithm.

The nominal pulse duration is approximately 20 clock cycles. Assuming up to five potentially overlapping pulses, the processing window is extended to 100 clock cycles to ensure that the latest possible pile-up contribution is fully observed. Consequently, the worst-case reconstruction latency scales linearly with the maximum assumed pile-up depth and remains fully deterministic. If no additional pulses are detected within the window, the processing is terminated early and the observation window is restarted at the next detected pulse onset. Therefore, while the worst-case latency is determined by the configured maximum pile-up depth, the average latency is significantly lower under sparse pile-up conditions.

The algorithm itself does not impose a fundamental limit on the number of overlapping pulses; increasing the assumed pile-up depth directly increases the required observation window and thus the processing latency.

This iterative approach allows the decomposition of multiple overlapping events. Figure 3 illustrates the recovery of two partially overlapping GEM pulses using the normalized-tail method.

Implementation on FPGA Using PyHLS

The algorithm is well-suited for FPGA implementation due to its simplicity and use of basic arithmetic operations peak detection, amplitude scaling, and signal subtraction that map efficiently onto FPGA logic. In PyHLS, the method is represented as a parametrized function with metamodel entries specifying signal length, iteration depth, and real-time latency constraints. This formulation enables automatic design-space exploration across pipelining, loop unrolling, and memory banking strategies.

Table 1. Representative FPGA resource usage for pattern-based reconstruction on Altera Cyclone V SE 5CSEMA4U23C6N [24].

Parameter	Resource Usage
Core frequency [MHz]	146.5
ALMs	755
LABs	119
ALUTs	1171
Registers	486
DSP blocks	4
M10K blocks	22

presents representative synthesis results for a Cyclone V FPGA, including logic elements (ALMs), registers, DSP blocks, and on-chip memory, assuming up to five overlapping pulses (window length = 100 clock cycles). While the absolute values depend on configuration parameters, the results confirm the lightweight nature of the method, demonstrating its scalability for large multichannel systems.

The normalized-tail pattern-based method thus provides a simple, efficient, and deterministic solution for real-time pulse classification in GEM detectors. Its low-resource footprint and guaranteed latency make it particularly suitable for FPGA implementation and large-scale parallelization. Although it lacks adaptability to waveforms with substantially different morphologies, it forms a strong foundation for hybrid trigger systems, where a lightweight pattern-based stage can be combined with CNN-based classifiers for enhanced robustness under diverse operating conditions.

4. CNN-Based Model for Generalized Signal Shapes

While template-based methods offer low latency and efficient resource use, their applicability is restricted to waveforms with stable, predictable morphology. In real experimental conditions, detector signals (e.g., from GEMs) can exhibit distortions, pile-up, baseline wander, and non-linear effects that degrade template matching. Motivated by the growing success of NNs in large-scale physics experiments, both offline and increasingly in low-latency trigger applications [8,11], we adopt compact CNNs as a generalized, data-driven alternative. CNNs learn discriminative features directly from raw ADC windows, enabling robust classification across varying operating points and signal morphologies.

The key advantage of CNNs is their ability to generalize beyond a predefined template by extracting hierarchical features: early layers capture local structures (e.g., rising edges, noise spikes), while deeper layers integrate this information into complex shape descriptors. This makes CNNs particularly suitable for trigger applications where waveform variability is significant.

The proposed CNN-based method operates on two complementary sources of information, as illustrated in Figure 4. A large signal window is continuously acquired from the detector, from which a smaller context window is extracted. Unlike conventional CNN approaches that rely on long temporal segments, here the context window can be extremely short, as its primary purpose is to capture the signal front (local maximum). By focusing on the front, the network can determine the true amplitude of the pulse while minimizing latency. In addition to detecting the local maximum, the context window also provides enough temporal neighborhood to verify whether the observed front is contaminated by the tail of a previous signal. If necessary, the network can apply a correction by subtracting the residual contribution of the overlapping tail. This mechanism is essential in high-rate detectors where pulse pile-up is common, as it prevents the misclassification of merged or distorted signals.

In parallel, a context memory module inside the FPGA provides additional features: it stores previously observed signal fragments together with their “age” (time distance from the current window). This allows the CNN to incorporate both the instantaneous waveform and its temporal history into the inference process.

The FPGA-based context memory maintains a fixed-size buffer of the most recent K pulses, storing both amplitude and relative age (number of clock cycles since the pulse). At each clock cycle, the ages of all entries are incremented, and pulses exceeding the maximum age are discarded. New pulses are inserted into the youngest slot of the buffer. During CNN inference, the Dense (8) layer reads all $2K$ values (amplitudes and ages) simultaneously, providing an up-to-date temporal context for front-tail discrimination while preserving deterministic timing.

The preprocessing stage includes baseline subtraction and normalization. The resulting context window is streamed into a one-dimensional CNN. The signal branch begins with a Conv1D layer followed by global average pooling to produce a compact feature vector. In parallel, the context memory branch is processed through a dense layer that encodes the historical information. Both branches are then concatenated and passed to subsequent dense layers, resulting in a final amplitude prediction or classification score. The combination of a very short context window and hardware-supported context memory yields a network that is significantly less complex and computationally demanding than generic CNN architectures. By reducing the input dimensionality to only what is strictly necessary for front–tail discrimination and amplitude regression, the number of parameters, multiply–accumulate operations, and memory requirements are minimized. This makes the approach highly suitable for FPGA deployment, where both low latency and efficient resource usage are critical.

Training is performed on a conventional computer system using Python v3.8.10 and the Keras deep learning framework [28]. The dataset includes both valid detector events and background/noise samples. The explicit inclusion of noise in the training set is crucial: it forces the network not only to recognize true signal fronts, but also to learn how to ignore baseline fluctuations, electronic interference, and accidental overlaps of tails from previous pulses. In practice, additive white Gaussian noise was introduced to each training window, with the standard deviation $\sigma$ randomly drawn from a uniform range [NOISE_MIN, NOISE_MAX]. Formally, each sample was perturbed according to

$$n_i\sim \mathcal{N}(0,{\sigma }^2),x_i^{\mathrm{noisy}}=x_i+n_i,$$

where $x_i$ denotes the clean input sample and $n_i$ the Gaussian noise. This procedure emulates the effect of electronic noise, where the noise level is not constant but varies with operating conditions. As a result, the network learns to cope with signals ranging from nearly ideal to strongly distorted. Additionally, some training examples contain overlapping pulses (pile-up), so that the model can distinguish a true front from the residual tail of a preceding event. By confronting the CNN with such realistic distortions during training, the deployed model becomes robust to conditions encountered in actual experiments. This safeguards the trigger system against false activations that might otherwise be induced by random fluctuations or pile-up.

The training follows the standard supervised learning paradigm, where the CNN parameters are optimized to minimize a loss function using backpropagation and gradient descent. In our case, we employ the Huber loss function with $\delta =0.05$, which behaves like a mean squared error for small deviations but like a mean absolute error for large ones. This choice stabilizes the optimization, penalizing large outliers without overemphasizing small fluctuations.

In this work, the CNN serves a dual purpose. During training, the network is optimized to predict the amplitude of the signal front, i.e., a regression task measured via mean absolute error (MAE). However, for real-time trigger operation, a simple threshold is applied to the predicted amplitude to classify events as either “valid pulse” or “noise/background”, effectively performing a classification step at inference. This approach allows the same model to provide both precise amplitude estimation and reliable trigger decisions. Consequently, MAE is used as a regression metric for training, while the thresholded output can be evaluated with standard classification metrics (e.g., accuracy, precision, recall) if desired.

The CNN was trained and validated on fully synthetic datasets generated using the pulse model. Each sample consists of a signal window of L ADC samples with up to K preceding pulses stored in the context memory. The ground truth ($Y_{\mathrm{true}}$) corresponds to the amplitude of the newly generated pulse and serves as the reference for supervised training and evaluation. Amplitudes were sampled uniformly within $[A_{\mathrm{MIN}},A_{\mathrm{MAX}}]$, and synthetic noise was added per-sample, with standard deviation drawn from [NOISE_MIN, NOISE_MAX]. Pile-up events were introduced according to the probability $P_{\mathrm{NEW}}$ and up to K overlapping pulses, so that the network learns to reconstruct the target amplitude in the presence of residual tails from previous pulses. All units correspond to normalized ADC signal amplitudes, ensuring full reproducibility of the dataset and an unambiguous definition of the target.

The dataset was divided into training, validation, and test subsets with $N_{\mathrm{TRAIN}}=40,000$, $N_{\mathrm{VAL}}=5000$, and $N_{\mathrm{TEST}}=5000$ samples. Training was performed using the fit() function in Keras, iterating over mini-batches of input windows. Each epoch updated the network weights based on the error between predicted and true amplitudes, with the validation set providing an unbiased estimate of generalization performance. Early stopping was applied when the validation MAE ceased to improve, preventing overfitting and ensuring a balance between accuracy and robustness. The training was repeated five times with different random seeds, and the run-to-run variation of the mean absolute error (MAE) did not exceed approximately 20%.

Once convergence is reached, the optimized weights are exported, quantized, and prepared for hardware deployment. This ensures that the network used on FPGA has been trained not only to maximize accuracy on clean signals, but also to reliably distinguish them from realistic noise and distortions in real-time data streams.

Table 2. CNN architecture optimized for FPGA deployment.

Layer	Input Dim.	Output Dim.	Weights	Biases	MACs
Input (signal)	$(L,1)$	$(L,1)$	-	-	-
Conv1D (16, k = 3)	$(L,1)$	$(L,16)$	48	16	$48L$
GlobalAveragePooling1D	$(L,16)$	$(16,)$	0	0	0
Input (context)	$(2K,)$	$(2K,)$	-	-	-
Dense (8, ReLU)	$(2K,)$	$(8,)$	$16K$	8	$16K$
Concatenate	$(16,)+(8,)$	$(24,)$	0	0	0
Dense (16, ReLU)	$(24,)$	$(16,)$	384	16	384
Dense (1, ReLU)	$(16,)$	$(1,)$	16	1	16
Total	-	-	$16K+448$	41	$48L+16K+400$

summarizes the proposed CNN model. In addition to input/output dimensions, it lists the number of weights, biases, and multiply–accumulate operations (MACs) required per layer. This detailed view highlights the balance between functionality and hardware efficiency.

In this architecture, L denotes the length of the context window (number of ADC samples taken around the signal front), while K represents the number of previous pulses maintained in the FPGA context memory (together with their age). Thus, the signal branch operates on an input of dimension $(L,1)$, whereas the context branch receives $\left(2K\right)$ values encoding both past amplitudes and temporal distances. This parametrization is particularly convenient, since L and K can be adjusted to balance accuracy, latency, and hardware resources: increasing L improves local waveform resolution, while larger K provides deeper temporal context at the cost of additional logic and memory usage. Each layer serves a specific purpose: the convolution extracts fine-grained local features with modest resource use; global average pooling collapses temporal information into 16 robust descriptors; the dense encoder on context memory compresses historical data; and the final dense layers integrate both information streams into the trigger decision. The total parameter count is modest (hundreds rather than thousands), ensuring that the model can be fully mapped to mid-size FPGA devices.

Although the leading edge of the signal (local maximum) is in many cases sufficient for rapid pulse detection, there exist challenging scenarios where front-only detection may fail. In high-rate conditions, several overlapping high-amplitude tails may dominate the baseline, causing a low-amplitude following pulse and effectively masking its onset. As a result, relying solely on local maxima may lead to systematic amplitude bias or false triggers. To overcome these limitations, the proposed architecture integrates an FPGA-based context memory that explicitly encodes historical samples and their age. This information allows the CNN to distinguish between a true front and a distorted waveform influenced by preceding signals. The network can then subtract the contribution of overlapping tails, restoring an accurate estimate of the pulse amplitude. In this way, the combination of short context windows and temporal memory enables robust front–tail discrimination even under conditions of heavy pile-up.

Although the model is simpler than transformer-based architectures, it shares a conceptual similarity with attention. In attention, the model dynamically learns which parts of the input history should be weighted more strongly. Here, the FPGA provides a manual attention mechanism: the context memory explicitly delivers selected past samples and their age, while the Dense (8) layer encodes them into features. The concatenation of signal and context streams mimics the fusion of “query” and “memory” in attention, but in a deterministic, hardware-friendly manner. This design preserves the benefit of temporal awareness without the quadratic complexity of full attention, making it suitable for real-time FPGA triggers.

Once the model has been trained, the inference stage can be executed in real time directly on the FPGA. Inference corresponds to the forward pass of the CNN, where fixed weights are applied to new input data to produce predictions. The process consists of successive convolution, activation, pooling, and fully connected operations, as summarized in Listing 2:

Listing 2. CNN-based inference algorithm.

Implementation on FPGA Using hls4ml

The CNN-based approach was successfully implemented on Intel Arria 10 FPGA (device 10AX115U1F45I1SG) using the hls4ml toolchain [12,13,27]. The synthesis flow relied on the Intel HLS Compiler (version 24.2.0 Build 99.1) together with Quartus Prime Pro Edition (version 25.1.0 Build 129, 26 March 2025). The toolchain provided a direct path from trained Keras models to FPGA-ready C++ descriptions, which were then compiled to RTL and fully integrated using Quartus.

The synthesis flow exploited standard HLS optimization techniques:

• Loop unrolling: Parallel execution of convolution and dense layers across multiple hardware operators.
• Fixed-point quantization: Using fixed<16,6> for input/output and fixed<8,2> for weights, which eliminates floating-point units and reduces logic utilization.

Representative implementation results are summarized in

Table 3. Implementation results of CNN classifiers on Intel Arria 10 (10AX115U1F45I1SG) using hls4ml and Intel HLS Compiler 24.2.0. Precision: I/O = ap_fixed<16,6>, Dense weights = ap_fixed<8,2>.

Config (L,K)	Train MAE	Test MAE	ALMs	Registers	DSPs	Fmax [MHz]
L = 5, K = 4	0.0177	0.0197	17,182 (4%)	28,067	0	268.1
L = 6, K = 4	0.0196	0.0194	18,066 (4%)	30,242	0	252.4
L = 7, K = 4	0.0197	0.0199	19,842 (5%)	33,005	0	247.0
L = 8, K = 4	0.0199	0.0190	20,549 (5%)	35,307	0	228.9
L = 5, K = 2	0.0145	0.0140	16,089 (4%)	25,744	0	278.2
L = 6, K = 2	0.0132	0.0121	17,362 (4%)	28,380	0	245.5
L = 7, K = 2	0.0116	0.0119	18,888 (4%)	31,259	0	252.1
L = 8, K = 2	0.0123	0.0113	19,648 (5%)	33,219	0	225.4

. The metrics include training and test mean absolute error (MAE), FPGA resource utilization, and the maximum achievable operating frequency (Fmax).

The results demonstrate that all CNN models fit comfortably within the resource budget of the Arria 10 device. Logic utilization (ALMs) remains below 5%, and the maximum frequency consistently exceeds 225 MHz, which is sufficient for real-time data acquisition and triggering pipelines. The models achieve test MAE values between 0.011 and 0.020, with smaller context ($K=2$) generally yielding slightly higher accuracy, which is consistent with the fact that a longer observation window provides more informative temporal features of the pulse shape.

However, MAE alone is not fully representative of trigger performance, as it depends on dataset dataset sparsity, pile-up frequency, and the number of overlapping pulses within the observation window. Therefore, complementary metrics such as hit ratio and false positive rate are also reported.

For the CNN with a context window of $K=4$ previous impulses and signal window length $L=5$ (corresponding design parameters are summarized in the first row of Table 3), we obtained the following performance metrics over the first 4000 test samples:

• Total true events: 2389;
• Hits: 2388;
• Hit ratio: 99.96%;
• MAE of detected amplitudes: 0.032 (corresponding to ∼3.2% of the normalized amplitude range);
• False positives: 104 for the current detection threshold set to 0; these are primarily low-amplitude predictions likely caused by noise and can be reduced to 4 by applying a threshold.

The reported MAE quantifies the average deviation between predicted and true amplitudes for detected events and depends on factors such as the sparsity of events in the signal and the presence of overlapping pulses. Increasing the detection threshold for predicted amplitudes can reduce the number of false positives (i.e., low-amplitude noise detections) while slightly affecting the hit ratio. This makes the false positive count a tunable metric, depending on the desired trade-off between sensitivity and noise immunity.

A key factor influencing resource mapping is the chosen numeric format. In this work:

• Model inputs/outputs and intermediate results were quantized to ap_fixed<16,6>, i.e., 16-bit fixed-point with 6 fractional bits.
• Dense-layer weights were quantized to ap_fixed<8,2>, i.e., 8-bit fixed-point with 2 fractional bits.

This quantization allowed the Intel HLS Compiler to optimize arithmetic at synthesis time. Multiplications by constant weights (known at compile time) were translated into shift-and-add structures, mapped to ALMs instead of DSP blocks. Similarly, additions and bias operations were implemented using the logic fabric. As a result, no DSP resources were reported in any configuration, despite the model performing many multiply–accumulate operations. This behavior is expected and highlights the efficiency of logic-based implementations for compact fixed-point networks. It also leaves the entire DSP fabric available for other accelerator kernels if required.

Overall, the evaluation highlights the inherent trade-off between the simplicity and scalability of pattern-based methods and the superior accuracy and adaptability of CNN-based triggers. The results confirm that, through fixed-point quantization, NNs can be efficiently deployed on FPGAs. This demonstrates the practical feasibility of implementing real-time neural inference directly in reconfigurable hardware, paving the way toward low-latency and resource-efficient trigger systems for advanced energy research and large-scale physics experiments.

5. Discussion

The comparative evaluation of pattern-based and CNN-based approaches confirms that both methods provide complementary strengths for real-time classification in large-scale physics experiments. Pattern-matching pipelines guarantee deterministic latency with an extremely small hardware footprint, making them highly scalable for hundreds of channels. CNN-based classifiers, on the other hand, achieve superior robustness and accuracy across diverse waveform morphologies, though at the cost of higher complexity and greater resource consumption.

To provide a clear overview of the trade-offs,

Table 4. Comparison of pattern-based vs CNN-based trigger methods. Deterministic latency is estimated for fully parallel FPGA implementation.

Feature	Pattern-Based	CNN-Based
Deterministic latency	1.27 µs (127 clock cycles @ 100 MHz, window length 100 clocks, up to 5 overlapping pulses, determined by window length and HLS parameters)	310 ns (31 clock cycles @ 100 MHz, does not depend on context window length, determined by CNN structure and HLS parameters)
Hardware resources	Minimal (few subtractors, multipliers, comparators)	Moderate (Conv1D + Dense MAC units, pooling logic)
Robustness to waveform variations	Low–medium	High
Adaptability	Fixed templates	Can learn new signal morphologies via training
Throughput (events/s)	5 MHz (5 event per 100 clocks @ 100 MHz)	100 MHz (1 event per clock @ 100 MHz)
Capture efficiency	Very high (depends on pulse overlap, SNR and threshold)	High (depends on CNN training, context window and threshold)
Scalability (channels)	Very high	High, limited by FPGA resources

summarizes key features of both approaches, including deterministic latency, hardware resources, robustness, adaptability, and throughput.

However, implementing such diverse algorithms on FPGA platforms through existing commercial HLS tools (e.g., Intel HLS Compiler [25,26], AMD Xilinx Vitis HLS [29], Intel One API [30]) remains challenging. These environments are predominantly pragma-driven: algorithm code written in C/C++ or OpenCL is annotated with compiler directives to suggest unrolling, pipelining, or partitioning. While this can accelerate development, it places tight constraints on design exploration. Several key limitations emerge:

• Limited transparency: Critical scheduling and binding decisions are left to proprietary heuristics, making it difficult to guarantee deterministic timing behavior in latency-critical triggers.
• Restricted modularity: Vendor flows provide optimized primitives for convolution or matrix multiplication, but lack an explicit intermediate representation (IR) layer where algorithmic intent, constraints, and hardware contracts can be separated and reused.
• Poor portability: Designs are often tightly coupled to a specific vendor toolchain and device family, complicating reuse across FPGA generations or migration to heterogeneous platforms with AI-specific hardware blocks.
• Shallow exploration: Although pragmas allow some parameter sweeps (e.g., different unroll factors), comprehensive design space exploration under multiple constraints (timing, power, memory bandwidth) is not natively supported.

These limitations motivate the development of PyHLS, a metamodel-driven framework where an explicit IR mediates between high-level algorithm descriptions and hardware-specific implementations. Unlike pragma-based HLS, PyHLS encodes time, concurrency, and memory structures as first-class IR attributes. This provides transparency, portability, and reproducibility while enabling systematic exploration of trade-offs.

From a physics perspective, this shift is crucial. In ITER plasma diagnostics, pattern-based filters are ideal for detecting fast transients such as edge-localized modes (ELMs), while CNN classifiers can be trained to recognize turbulence or subtle instabilities. Commercial HLS tools struggle to express such hybrid, hierarchical architectures without extensive manual HDL intervention. PyHLS, by contrast, allows both paths to be described in a single metamodel, compiled, and co-optimized against shared latency and throughput constraints.

A broader implication of this study is that a metamodel-centric flow can unify both classical pipelines and AI-based classifiers in a single framework. Instead of being locked into vendor-specific pragmas, researchers can explore algorithm families, resource mappings, and latency contracts in a structured and auditable way. This promotes both innovation and reproducibility in next-generation trigger systems.

In summary, while commercial HLS tools provide a useful entry point, their pragma-driven design philosophy limits deep control, modularity, and portability. By contrast, PyHLS introduces a transparent, IR-centric methodology that enables deterministic pattern-based pipelines and expressive CNN triggers to coexist within one design flow. This direction opens the path to real-time trigger systems that combine the determinism required for physics-grade latency guarantees with the adaptability of neural and AI-accelerated hardware.

6. Contributions

This work makes the following contributions:

• Implementation and evaluation of a pattern-based real-time trigger classifier developed natively in PyHLS, serving as a deterministic and resource-efficient baseline.
• A proof-of-concept demonstration of NN-based trigger classification on FPGA using a commercial HLS flow (hls4ml and Intel HLS Compiler), motivated by the absence of native NN support in PyHLS at the time of this study.
• Design and demonstration of an original CNN architecture with short leading-edge windows and explicit context memory, showing that an efficient FPGA implementation of a neural trigger is feasible; without the context memory, such low-latency, resource-efficient implementation would be difficult to achieve.
• Experimental validation of FPGA feasibility on Intel Arria 10, showing high operating frequency and low resource utilization without DSP blocks through fixed-point arithmetic.
• Establishing a technical foundation for porting NN-based triggers to PyHLS, leveraging its open, fabric-aware compilation model for long-term maintainability and portability across FPGA generations.

7. Conclusions

This work compared two complementary strategies for real-time signal classification in physics experiments: a classical pattern-based method and a CNN approach tailored for FPGA deployment. The pattern-based method, relying on normalized template matching, served as a reference strategy due to its deterministic latency and extremely low-resource footprint. While attractive for large multichannel systems, its accuracy degrades in scenarios with signal variability, pile-up, or high noise.

The motivation for exploring neural-network-based triggers arises from the intrinsic variability of GEM signals and the increasing dimensionality of modern readouts. While pattern-based methods perform well under stable, stationary conditions, they assume a fixed reference shape and thus struggle when waveform morphology changes due to gain drifts, pile-up, or channel cross-talk. Neural approaches overcome this limitation by learning directly from measured data rather than relying on analytical templates. Their convolutional structure captures both spatial and temporal correlations, enabling robust feature extraction even under non-ideal detector conditions. Furthermore, the same one-dimensional convolutional layers used for strip signals can be extended seamlessly to two-dimensional kernels, making the transition toward pixelated GEM readouts straightforward while maintaining bounded latency through parallel, localized processing on FPGA hardware.

The CNN-based classifier was fully synthesized and tested on Intel Arria 10 (10AX115U1F45I1SG) using the Intel HLS Compiler (version 24.2.0 Build 99.1) together with the hls4ml toolchain. To improve efficiency, the network adopted a novel design with short context windows (L) and explicit context memory (K). Instead of analyzing entire long signals, the CNN processes only the leading-edge fragment and augments it with stored historical information, thereby avoiding redundant computations. This design yields several benefits: a much simpler network topology with fewer parameters and MACs, lower memory traffic and improved numerical stability, and reduced latency without sacrificing accuracy.

The implementation confirmed that such CNNs can be mapped efficiently to FPGA hardware: synthesis results showed modest ALM utilization (4–5%), with no DSP block usage due to fixed-point arithmetic (fixed<16,6> I/O and fixed<8,2> weights), and achieved operating frequencies above 225 MHz. The absence of DSP usage is explained by the fact that multiplications by constants are optimized into logic fabric, while additions do not require dedicated DSP units. This validates the feasibility of low-latency neural trigger pipelines within the resource budget of a single Arria 10 device.

7.1. Preliminary Scope and Scalability

It must be emphasized that the CNN was designed as a one-dimensional architecture and evaluated on a single strip of a GEM detector, serving as a preliminary proof of concept. There is a growing trend toward two-dimensional, including pixelated, readouts in practical GEM systems, which increases the computational challenge. The proposed approach offers a clear path to such systems:

• Convolutional layers extend naturally from 1D to 2D kernels, enabling spatial feature extraction;
• The short-window strategy avoids the excessive complexity of repeatedly analyzing long waveforms or large 2D frames;
• Context memory provides temporal correlation without requiring deep recurrent structures, ensuring bounded latency;
• FPGA resources can be managed effectively, since feature extraction remains localized and parallelizable.

7.2. Hybrid Architectures

These findings indicate that hybrid trigger systems are particularly promising. A pattern-based pre-filter can serve as a deterministic, low-cost stage to reject clear background events, while CNN classifiers provide robust discrimination for ambiguous cases. Such hierarchical strategies balance efficiency with robustness and are directly applicable to plasma diagnostics in energy-generating tokamaks (e.g., ITER).

7.3. Future Work

Further research will focus on:

• Adaptive trigger pipelines: Dynamic switching between pattern-based and CNN-based stages conditioned on detector operating point (rate, pile-up, SNR) and resource headroom.
• Fabric-Optimal PyHLS Mapping: Extending PyHLS with placement/routing heuristics that explicitly target hardware blocks (e.g., Agilex AI Slices, DSP packing, BRAM/M20K banking, URAM tiling) under strict latency/throughput constraints.
• Native NN library for PyHLS: Developing an embedded neural-network operator/library stack (convs, depthwise/separable, pooling, linear, activations, folded batch-norm, quantized kernels) with model import, graph lowering, and code generation, enabling native NN compilation in PyHLS without external toolchains.
• Distributed FPGA trigger farms: Scaling to multi-board deployments that process thousands of channels in real time with deterministic interconnect and failover.

7.4. Rationale for PyHLS

A survey of HLS usage in tokamak diagnostics revealed material gaps between the needs of long-horizon physics experiments and the capabilities or support models of mainstream vendor toolchains. While commercial HLS (e.g., Vivado HLS [29], Intel HLS Compiler [25,26], Intel OneAPI [30]) can substantially shorten time-to-prototype, their roadmaps and device support policies are optimized for the newest FPGA families. In multi-year programs with fixed instruments and constrained budgets, this creates a sustainability risk: mature, fielded systems may outlive the official tool support for the underlying devices, complicating maintenance, incremental upgrades, and reproducibility. Moreover, closed toolchains limit low-level extensibility (custom operators, timing models, or fabric-specific mappings) that is often required to guarantee bounded latency for real-time feedback control.

7.5. Final Takeaway

The experimental implementation shows that CNN-based classifiers, when paired with short context windows and compact state (context memory), offer a practical, scalable route to next-generation low-latency triggers. Pattern-based methods remain a strong baseline and diagnostic reference, but CNNs provide the adaptability required to operate under variable SNR, pile-up, and nonstationary conditions. While our one-dimensional GEM studies establish feasibility, the same design principles extend naturally to full 2D and pixelated readouts and, more broadly, to real-time trigger systems across hot-plasma diagnostics and other large-scale physics experiments (e.g., cosmic-ray, neutron/X-ray, and high-energy physics detectors), enabling robust FPGA-based deployments at scale.

Crucially, an open, fabric-aware HLS layer such as PyHLS complements these results by ensuring portability across device generations, transparent resource control for deterministic latency, and long-term maintainability beyond vendor tool lifecycles—properties that are essential for sustained operation of scientific trigger systems.

Current studies with frameworks such as hls4ml (ML4HLS) demonstrate that neural inference on FPGAs is technically feasible; however, they remain constrained by vendor-optimized flows and device-specific dependencies. Their workflows require indirect translation of ML4HLS Python models into C/C++ representations suitable for HLS compilation, which limits transparency, extensibility, and long-term reproducibility across heterogeneous FPGA generations.

7.6. Outlook and Prototype Scope

The presented system constitutes a mature prototype and a functional proof of feasibility, demonstrating that neural-network-based architectures can be effectively implemented in FPGA hardware under strict latency and resource constraints. While the current design validates this approach in practice, it also reveals inherent limitations of existing HLS and ML4HLS frameworks, particularly their dependence on vendor-specific flows and indirect Python-to-C/C++ translation. The results therefore represent a significant yet non-final stage in the ongoing development of open, portable, and fabric-aware methodologies. Future work will focus on extending this concept toward multidimensional readouts, hybrid trigger pipelines, and fully native PyHLS synthesis, ensuring sustainable and reproducible FPGA-based solutions for advanced energy and large-scale physics experiments.