Digital Control Scheme for Class-D Power Amplifier Driving ICP Load Without Matching Network

Abstract

Class-D power amplifiers driving variable loads, such as inductively coupled plasma (ICP), typically require an impedance matching network, which has a relatively slow matching speed, generally in the millisecond range. To address this issue, this paper proposes a solution that uses a fully digital control method for Class-D power amplifiers to directly drive ICP loads. This solution eliminates the need for an impedance matching network, reducing the overall output power regulation time to just tens of microseconds. Compared to traditional methods that use a VI probe to detect output power, the proposed method in this paper only requires measuring the resonant current in the loop to control the output power, thereby reducing costs and ensuring that the Class-D power amplifier achieves zero-voltage switching (ZVS) throughout the adjustment process. This paper provides a detailed introduction to the design method of the Class-D power amplifier and the overall digital control scheme and validates them via simulation and experimentation. The Class-D power amplifier prototype was designed using SiC MOSFETs, with a Xilinx ZYNQ-XC7Z100 FPGA as the control board. The output frequency varies around 4 MHz, successfully generating plasma.

1. Introduction

Inductively coupled plasma (ICP) is extensively used in industrial production due to its excellent characteristics, such as semiconductor manufacturing processes, surface treatment processes, high-power ultraviolet radiation sources, medical device disinfection, and carbon dioxide treatment [1,2]. However, the impedance of ICP changes rapidly during plasma generation and is related to many factors such as gas flow rate, pressure, and frequency, thus imposing high requirements on the power supply driving the ICP [3]. Currently, in industrial applications, the radio frequency power amplifiers used to drive ICP include linear amplifiers and switching amplifiers. Linear amplifiers mainly include Class A, AB, B, and C, but they have low efficiency, with overall efficiency generally less than 80%. In contrast, switching amplifiers mainly include Class D, E, and F, with overall efficiency generally reaching over 90%. It is evident that switching RF power amplifiers have significantly lower losses compared to linear RF power amplifiers, which gives them a greater advantage in high-power applications.

Currently, a mature solution in the industry is to use RF power amplifiers combined with impedance matching networks to drive inductively coupled plasma, with motors controlling the vacuum capacitors in the impedance matching networks to match the varying load, as shown in Figure 1 [4,5]. However, limited by the speed of motor adjustment, the adjustment speed of the impedance matching network is relatively slow, typically in the millisecond range. Moreover, as the overall power level of the amplifier increases, the number of passive components required for the impedance matching network also increases, adding to the system’s size and cost [4,6]. To address the above issues, scholars have proposed different solutions.

The first solution focuses on improving the tunable impedance matching network (TMN) or impedance matching algorithm. Under normal circumstances, the impedance matching time is 3–5 times the capacitor variation time. By researching the use of electronic capacitors composed of switching devices to replace vacuum capacitors driven by motors, the adjustment speed of the capacitors can be increased, thereby improving the adjustment speed of the impedance matching network [7,8,9]. However, the matching range and discreteness of electronic capacitors become issues that need to be resolved. Their tuning resolution depends on the number of switching elements. In some high-power applications that require precise impedance matching over a very wide impedance range, the number of switching elements required will increase sharply, leading to increased cost and size [9]. In addition, since there are switching losses during the operation of switching devices, a large number of switching devices will increase the losses of the matching network, thereby reducing system efficiency [7].

The second solution involves using impedance compression networks to achieve smaller impedance changes at the amplifier output when the load changes significantly [10,11,12,13]. This solution can regulate the output power by adjusting the input voltage and switching frequency. The values of the passive components used are fixed and do not require tunable capacitors. The speed of output power regulation depends on the adjustment speed of the input voltage and switching frequency [14]. In addition, due to the insensitivity of the impedance compression network to the load, it has also been applied to very high-frequency DC-DC converters, such as in applications with a switching frequency of 100 MHz [11].

The third solution improves from the perspective of the power amplifier, using an outphasing approach to control impedance through a parallel structure [15,16,17,18,19]. It uses two RF power amplifiers with independently controllable amplitude and phase, compressing the impedance seen by each inverter. When the load impedance changes, the impedance seen from the input side of the amplifier remains almost constant [20]. This solution is generally used in combination with an impedance compression network and requires the power amplifier’s phase and amplitude to change rapidly, resulting in higher design and control complexity [21].

The fourth solution improves from the perspective of the power amplifier, eliminating the need for an impedance matching network and directly using a Class-D power amplifier to drive the ICP load, with output power controlled by adjusting the switching frequency when the load changes [6,22,23,24,25]. The advantage of this solution is that it does not require a large number of passive components, and the adjustment speed is fast. For example, with a switching frequency of 4 MHz, one switching cycle is 250 ns, and power adjustment can be completed within a few cycles, achieving a speed in the microsecond range. This method requires a high frequency resolution for switching frequency adjustment to achieve precise control of output power. PLL-based control methods, which offer high frequency resolution, are widely used in frequency variation control [26]. However, their transient response is relatively slow owing to the limitations imposed by low-pass filters. Self-oscillating control methods, which lack integral circuits, are considered suitable solutions due to their high frequency resolution and fast frequency tracking speed [27,28,29]. However, the cumulative time delays of the closed-loop components can cause phase delay, resulting in hard switching issues [6]. Since the operating frequency of the MOSFETs is very high and the power is relatively large (typically in the kW range), to ensure the safe operation of the Class-D power amplifier, all MOSFETs must achieve ZVS [6]. Because the ICP load impedance changes very rapidly during plasma ignition, with the entire process typically completed within a few hundred microseconds, achieving ZVS is very challenging [22]. A comparison of the key characteristics of different types of RF power supplies for variable loads is presented in

Table 1. Key characteristics of different types of RF power supplies for variable loads.

Paper	Time	Frequency	Power	Topology	Efficiency	Features
[4]	2006	13.56 MHz	3 kW	Class E	NA	Impedance matching network, multiple power amplifiers.
[5]	2024	3.5 MHz, 4 MHz	200 W	Class D	>60%	In the impedance matching network, fixed-value passive components are used. With a fixed input voltage, the output power is controlled through duty cycle adjustment.
[30]	2025	NA	NA	NA	NA	Using the Neural Network Technique for the impedance matching network.
[7]	2020	13.56 MHz	1.5 kW	NA	>60%	Phase-switched impedance modulation; impedance matching is achieved within tens of microseconds.
[8]	2022	13.56 MHz	1 kW	NA	NA	By utilizing SiC MOSFETs and p-i-n diodes to construct electronic capacitors in place of vacuum capacitors, the impedance matching time is significantly reduced to the order of a few milliseconds.
[10]	2017	13.56 MHz	250 W	NA	NA	Using a Resistance Compression Network, an impedance transformation stage, and a specially configured set of plasma drive coils to achieve rapid adjustment to plasma load variations.
[19]	2019	13.56 MHz	1 kW	Class D	95.4%	Using two RF power amplifiers with independently controllable amplitude and phase, compressing the impedance seen by each inverter.
[6]	2019	4 MHz	10 kW	Class D	97%	Output power is adjusted by modifying the switching frequency, and high-resolution resonant frequency tracking control is implemented using analog techniques.
[22]	2022	3 MHz	25 kW	Class D	94%	Analyzing the characteristics of load variation in ICP during plasma generation.

.

Article [6] proposes a solution using a Class-D power amplifier to directly drive variable loads, such as ICP. The maximum power of this Class-D power amplifier prototype is 10 kW, with a normal operating frequency range of 3.4 MHz to 4 MHz. Its phase detection and control circuit (RLC phase lead circuit) is implemented by controlling a resistor matrix, which cannot continuously adjust the resistance value, thus resulting in low control precision of the output power. The paper does not provide a detailed analysis of this part.

Article [22] publishes theoretical designs related to driving xenon lamps at 10 Pa ICP and performs finite element method simulations of electromagnetic, thermal, mechanical, and plasma characteristics. It employs a half-bridge Class-D structure with a theoretical operating frequency around 3 MHz. The paper mainly analyzes and simulates the impedance variation during the ICP generation process and theoretically calculates the impedance variation range for achieving ZVS. Articles [23,24] introduce the control and hardware circuit design of its prototype.

The above studies explore the use of Class-D power amplifiers at MHz-level switching frequencies to directly drive variable loads, which has very high application value. This paper improves on the fourth solution mentioned above and proposes a full-digital control scheme for Class-D power amplifiers to directly drive variable loads such as ICP. The main contributions of this paper include:

(1)

Proposing a full-digital control scheme for Class-D power amplifiers to directly drive variable loads such as ICP, with a detailed analysis of the impact of PFM resolution on output power accuracy.

(2)

A method for high-resolution DPWM/DPFM generation with a simple structure is designed using an FPGA, thereby enhancing the temporal resolution of the drive signal generated.

(3)

Proposing a real-time phase measurement method that does not require a VI probe to calculate the phase of the output voltage and current in real-time, with a time accuracy of 53 ps. It can also calculate the output power in real-time, reducing hardware costs. This phase measurement scheme is not only applicable to Class-D power amplifiers but also to half-bridge or full-bridge resonant topologies, with a broad application prospect.

(4)

Proposing a dynamic dead-time calculation method to ensure ZVS in Class-D power amplifiers. It can also be used for real-time ZVS state judgment without the need for separate ZVS detection hardware circuits.

The phase measurement scheme, dynamic dead-time calculation method, and ZVS state judgment method proposed in this paper are not only applicable to Class-D power amplifiers but also to half-bridge or full-bridge resonant topologies, with a broad application prospect.

This paper primarily proposes a digital control scheme for driving an ICP. The structure of the paper is arranged as follows: Section 2 mainly introduces the overall structure of the digital control scheme. Section 3 discusses the high time-resolution DPFM generation method, as well as high-precision rapid phase detection and output power control methods. Section 4 presents a detailed validation and analysis of the proposed digital control scheme using simulation results. Section 5 designs and fabricates 4 MHz full-bridge Class-D module prototypes based on SiC MOSFETs, using Xilinx ZYNQ-XC7Z100 FPGA(AMD, San Jose, CA, USA) as the control chip, to validate the rationality of the overall control scheme. Finally, this work is concluded, and an outlook is given in Section 6.

2. Overall Introduction to the Digital Control Scheme

This paper utilizes a full-bridge Class-D amplifier for driving ICP, with the main circuit shown in Figure 2. In the circuit, L and R represent the equivalent resistance and inductance of the ICP coil, respectively. S1–S4 are MOSFETs, and C1–C4 represent the parasitic output capacitance of S1–S4. Cin is the energy storage capacitor, and Vin denotes the input DC voltage. To reduce the turn-off losses of the MOSFETs and achieve resonance, an adjustable vacuum capacitor Cr is connected in series within the circuit. The value of Cr is determined by the load to ensure that the resonant frequency between Cr and the load is between 3 and 4 MHz. The output power is kept constant by adjusting the switching frequency and duty cycle of the MOSFETs.

2.1. Digital Control Scheme

The overall control scheme adopted in this paper is shown in Figure 3. The output current signal is measured using a current probe and is divided into two paths for processing. The first current signal is sampled by a high-speed ADC and converted into a digital signal for subsequent calculations and real-time waveform display. The second current signal is processed by a zero-crossing comparator to be converted into a square wave signal for phase measurement. Since the input voltage is a known quantity, the output power can be obtained by combining the effective value of the measured output current and the phase difference between the output voltage and current:

$$P=U_{RMS}{·I}_{RMS}·\mathit{cos}\phi$$

(1)

Here, $U_{RMS}$ represents the root mean square (RMS) value of the fundamental wave of the Class-D module’s output voltage, and $I_{RMS}$ is the RMS value of the Class-D module’s output current. $\phi$ denotes the phase difference between the output voltage and current. By adjusting the frequency, control over $\mathit{cos}\phi$ can be achieved, thereby enabling control over the output power.

When the load changes, the difference between the set power and the real-time calculated output power is used as the error signal for control. This error signal is processed by a PID controller to generate a frequency signal for controlling the MOSFETs. By changing the frequency, phase shift control of the output voltage and current is achieved, thereby controlling the output power. The disadvantage of this control method is that when the output power is low, the phase difference between the output voltage and current approaches 90°, resulting in a large MOSFET turn-off current and higher losses. The advantage is that fast output power control can be achieved simply by adjusting the switching frequency and dead time.

Since the accuracy of the measured phase value affects the accuracy of the output power calculation, obtaining an accurate phase value is crucial. There are two common methods for calculating the phase: The first method involves performing FFT analysis on the voltage and current signals sampled by a high-speed ADC to determine the phase difference. The second method involves measuring the time difference between the zero-crossing points of the voltage and current signals and calculating the phase based on the signal period and the time difference between the zero-crossing points of the two signals. The first method requires a high sampling rate for the ADC. In this paper, the output port voltage is a square wave signal, and the output current is a sine wave signal. The rise time of the square wave is very short, even as low as tens of nanoseconds, and there is ringing, which causes severe spectral leakage when performing FFT analysis on the square wave, affecting the phase calculation. Additionally, FFT analysis requires high hardware performance, and since the control needs to be in real-time, all calculations must be completed within one switching cycle; otherwise, the system’s performance will be affected.

The second method requires additional zero-crossing comparators and edge detection circuits. The phase is indirectly calculated by measuring the delay between two pulse edges, but its accuracy can be high, reaching 53 ps in this paper, and the measurement is completed automatically and in real-time without complex calculations. However, this method requires that the harmonics of the two signals be small to achieve good results. However, due to the ringing at the output port voltage, directly measuring the output voltage and current signals may lead to abnormal calculations, causing the system to malfunction.

To solve this problem, this paper proposes using the drive signal instead of the voltage signal for phase measurement. Taking Figure 4 as an example, the drive signals S2 and S3 are inverted and delayed by $t_1$ to obtain signal V, which can be used to replace the output port voltage. The calculation method for the delay time $t_1$ is given in the next section. The current signal is converted into a square wave signal I after passing through the zero-crossing comparator. The phase between the voltage and current can be obtained by measuring the delay between signal V and signal I. In practical implementation, it should be noted that the delay time of signal V needs to consider the delay of the drive circuit, the delay of the PCB wiring, the error delay of the current probe, and other factors, and calibration should be performed according to the actual circuit. In addition, in the above phase measurement method, the lower the harmonic content of the current, the better the actual effect. The load at the output end of the Class-D power amplifier can be equivalent to an RLC load. The relationship between the n-th current harmonic $I_n$ and the fundamental current $I_1$ under different load quality factors Q is shown in Equation (2). When the equivalent load quality factor is 5, the ratio of the fundamental to the third current harmonic is approximately 40:1, which meets the requirements. Since the load Q value in this paper is much greater than 5, this method is feasible.

$$\left|{\displaystyle \frac{I_n}{I_1}}\right|=\left|{\displaystyle \frac{1}{n}}·{\displaystyle \frac{1}{1+jQ\left(\frac{n^2-1}{n}\right)}}\right|\approx {\displaystyle \frac{1}{Q(n^2-1)}}$$

(2)

2.2. Dynamic Dead Time Calculation

Soft switching becomes essential for Class-D amplifiers operating at high frequencies (particularly above 1 MHz). Two primary soft-switching techniques exist: Zero Current Switching (ZCS) and Zero Voltage Switching (ZVS). For power MOSFETs, ZVS implementation is critical due to their significantly higher turn-on losses compared to turn-off losses [31]. Furthermore, non-ZVS operation at high frequencies induces severe ringing phenomena, which distort gate-driving signals and risk catastrophic amplifier failure [6].

Dead time directly determines ZVS achievement in Class-D amplifiers [32,33]. Figure 5 illustrates output voltage, current waveforms, and driving signals of a full-bridge Class-D amplifier under varying dead time configurations. Figure 5b,c achieve ZVS, whereas Figure 5a,d fail. In Figure 5a, insufficient dead time prevents complete charging/discharging of the MOSFET’s parasitic output capacitance (Coss) before switch closure. Figure 5d demonstrates excessive dead time, allowing resonant current reversal to reverse-charge Coss before switching. Optimal ZVS occurs in Figure 5b, where switching coincides with full Coss charge/discharge. Figure 5c introduces marginally longer dead time, triggering conduction of the MOSFET’s body diode. As diode conduction incurs forward voltage drop losses, prolonged dead time exacerbates conduction losses, especially in GaN FETs.

Fixed dead time settings may fail to maintain ZVS under load variations. While auxiliary resonant networks can enforce ZVS [34,35,36,37,38], they introduce additional losses—a critical drawback for high-frequency, frequency-modulated applications. Dynamic dead time adjustment thus emerges as the superior approach. This section derives the theoretical framework for optimal dead time calculation.

Figure 4 is used to analyze the optimal dead-time calculation method. To derive the expression for the optimal dead time, $t_{\phi }$ must first be determined. $t_{\phi }$ represents the time corresponding to the phase shift between voltage and current and is related to the period T as follows:

$$t_{\phi }={\displaystyle \frac{\phi }{2·\pi }}·T={\displaystyle \frac{\phi }{\omega }}$$

(3)

From Figure 4 and Figure 5b, the optimal dead time, D, satisfies:

$$Q={\int }_{t_{\phi }-{\displaystyle \frac{D}{2}}}^{t_{\phi }+{\displaystyle \frac{D}{2}}}{i}_{AC}dt={\int }_{t_{\phi }-{\displaystyle \frac{D}{2}}}^{t_{\phi }+{\displaystyle \frac{D}{2}}}{I}_{AC}·\sin \left(\omega t\right)dt=2V_{in}{C}_{oss}$$

(4)

Q represents the area of the shaded region in Figure 4, indicating the charge required for complete charging and discharging of the parasitic output capacitance. Combining (3) and (4), D is derived as:

$$D={\displaystyle \frac{2}{\omega }}\mathrm{a}\mathrm{r}\mathrm{c}\mathrm{s}\mathrm{i}\mathrm{n}\left({\displaystyle \frac{\omega V_{in}{C}_{oss}}{I_{AC}\sin \left(\phi \right)}}\right)={\displaystyle \frac{2}{\omega }}\mathrm{a}\mathrm{r}\mathrm{c}\mathrm{s}\mathrm{i}\mathrm{n}\left({\displaystyle \frac{\frac{V_{in}}{I_{AC}}}{\frac{\sin \left(\phi \right)}{\omega C_{oss}}}}\right)={\displaystyle \frac{2}{\omega }}\mathrm{a}\mathrm{r}\mathrm{c}\mathrm{s}\mathrm{i}\mathrm{n}\left({\displaystyle \frac{\left|Z\right|}{X_c·\mathrm{s}\mathrm{i}\mathrm{n}\left(\phi \right)}}\right)$$

(5)

Here, $\left|Z\right|=V_{in}/I_m$, $V_{in}$ is the input voltage, $I_m$ is the peak value of the output current, $X_C=1/\left(\omega C_{oss}\right)$, $C_{oss}$ is the value of the MOSFET’s parasitic output capacitance. In practical applications, owing to factors such as drive delay and the error associated with $C_{oss}$ modeling, the dead time is typically set somewhat larger than the calculated dead time. It should be adjusted based on the measured results and is typically at least 10 ns larger than the calculated value mentioned above.

Based on Figure 4 and the preceding analysis, the condition for ZVS is:

$$\left\{\begin{array}{c}{t}_d=t_{\phi }+t_1\\ t_1=0.5D\\ D=\tau \\ t_d\ge \tau \end{array}\right.$$

(6)

Simplifying these yields:

$$t_{\phi }\ge 0.5D$$

(7)

Given that $t_{\phi }$ is measured in real time, it can be compared with the calculated optimal dead time to determine ZVS. This approach eliminates the need for an additional ZVS detection circuit. Since all half/full-bridge resonant topologies exhibit RLC-equivalent output loads, this ZVS detection and dynamic dead time adjustment methodology offers universal applicability in power electronics systems.

3. High-Precision Digital Control Implementation Scheme

3.1. High-Precision DPFM Implementation Principle

For DPWM that only requires changing the duty cycle, the rising edge of one PWM signal is always aligned with the clock signal and is used as a reference benchmark to delay other edges. To achieve precise control over the frequency of the generated modulation pulses, it is necessary to calculate the fine delay t′ for the next cycle during the current cycle and use this as the starting point to calculate the delays for other pulses in the next cycle, as shown in Figure 6. Figure 6 illustrates the timing diagram of a high-precision DPFM, where t1 and t2 are the delays of the rising and falling edges of DPFM1 relative to the rising edge of the reference clock, respectively. t3 and t4 are the delays of the rising and falling edges of DPFM2 relative to the rising edge of the reference clock, respectively. These delays are calculated during the previous switching cycle of the current switching cycle (e.g., 250 ns of 4 MHz). This method can achieve high-precision duty cycle delays and period delays, with a wide adjustable range. However, the disadvantage of this method is the need for real-time computation. This paper chooses to implement the aforementioned algorithm using FPGA.

The FPGA circuit structure implementing the high-precision DPFM algorithm is shown in Figure 7 [39]. The rising and falling edges of each modulation pulse are controlled by two IDELAYE2 modules via RS flip-flops, with the delay time of each IDELAYE2 module calculated in real-time by the CONTROL module, with a clock frequency of 200 MHz. The IDELAYE2 module, IDELAYCTRL module, and PLL module are built-in modules of the Xilinx (now a part of ADM) FPGA development environment and can be directly called. Among them, the IDELAYE2 module is responsible for achieving high-precision delay and can subdivide the reference clock into 5 bits. The IDELAYCTRL module realizes the dynamic calibration of the delay of the IDELAYE2 module. The PLL module is a phase-locked loop that achieves frequency division of the clock. The CONTROL module is a custom module that mainly calculates the delay value transmitted to the IDELAYE2 module. For the application scenario in this paper, where the PFM frequency ranges from 3.3 MHz to 6 MHz, a 200 MHz clock is selected for IDELAYE2 to achieve a delay precision of 78 ps. Given the requirement for symmetry in the dead time of the two drives within the same bridge arm of the full-bridge Class-D power amplifier, the PFM period is configured with a precision of 156 ps. This ensures symmetry between the two drives when the PFM period setting word is odd.

To verify the stability of the Digital PWM/PFM scheme, it is necessary to test the PWM signals output by the FPGA. The oscilloscope used is the MSO4304A, with a maximum sampling rate of 5 Gsa/s. For ease of observation, the oscilloscope is set to the infinite persistence display mode, gradually increasing the pulse width by 936 ps (six minimum adjustable units), operating for 10 min at each pulse width, and superimposing different test results onto the same graph, as shown in Figure 8. Since the oscilloscope has a sampling rate of 5 Gsa/s, the measurement error is 200 ps. From the graph, the width of the persistence is observed to be around 300 ps, and the stability of the generated PWM essentially meets the requirements.

In engineering applications, frequency counters are often utilized to measure frequency. The fundamental operation of a frequency counter involves counting the number of pulses over a defined time span from start to endpoints to determine the frequency. The frequency measured by a frequency counter represents the average pulse frequency measured over a specified duration. This paper employs the MSO4304A oscilloscope, equipped with an integrated frequency counter function, which offers an effective digit count of five and achieves an average accuracy of 10 ps for pulses with periods below 1 $\mathsf{\mu }$s.

The PFM frequency range is set between 3.3 MHz and 6 MHz, with a period interval of 15.6 ns at various test points. The PFM test results at different frequencies are obtained by tallying the readings from the frequency counter, as depicted in Figure 9. In the graph, the horizontal axis represents the internal set values of the FPGA, and the vertical axis indicates the period values of PFM. It is evident that the measured values align with the set values. Additionally, for closer examination near 4 MHz, the cycle is incrementally adjusted in the smallest adjustable unit, and the test results are presented in Figure 9b. The graph shows that the set values and the actual measurements are essentially superimposed, with discrepancies within 6 ps.

3.2. High-Precision Rapid Phase Measurement Implementation Scheme

The phase measurement section transforms phase measurement into time measurement by determining the time difference between the zero-crossing points of voltage and current, thereby calculating the phase difference. While the simplest approach to measure the time difference between the rising edges of two signals involves using a clock signal for edge detection, the measurement precision is constrained by the clock period and cannot be significantly enhanced. If the clock frequency of the counter is 200 MHz and the measured signal frequency is 4 MHz, the accuracy of phase measurement is:

$$\theta =4 \mathrm{M}\mathrm{H}\mathrm{z}·360°·5 \mathrm{ns}=7.2°$$

(8)

This accuracy cannot satisfy the requirements of digital control. To improve measurement accuracy, this paper combines a counter with a CARRY4 delay chain to measure the delay from the signal rising edge to the clock edge. CARRY4, a dedicated hardware resource in FPGA, is primarily employed for arithmetic operations such as addition and subtraction but can also function as a high-precision delay unit [40,41,42,43]. The measurement precision of this method is determined by the delay of each stage in the delay chain, and the computational principle of the high-precision time measurement scheme is illustrated in Figure 10. The delay measurement results of the two signals can be represented as:

$$Time=cnt+t_1-t_2$$

(9)

$cnt$ represents the counter value, t1 represents the time from the first signal’s rising edge to the clock’s rising edge, and t2 represents the time from the second signal’s rising edge to the clock’s rising edge, as shown in Figure 10. The non-uniformity of the delay chain and the delay variations caused by temperature changes can affect the measurement results. However, since the calculation involves taking the difference between two fine delays, this influence can be effectively reduced.

The phase measurement module includes a coarse counter (implemented by a counter whose clock is 200 MHz), a delay chain, a decoder, and a delay calculation section, with the overall structure shown in Figure 11. The delay chain translates the measurement result into N zeros and ones (where N is the number of delay units), with a one indicating that the signal has reached this delay unit and a zero indicating that the signal has not yet reached this delay unit. The decoder determines the detailed fine delay value by counting the number of ones, as shown in Figure 12 [44]. Finally, the delay calculation module adds the coarse count and the fine delay value to obtain the overall delay calculation result.

The design of the fine delay module composed of CARRY4 delay units will be detailed in the following. The FPGA design tool used in this study is VIVADO 2017.4. Since the counter clock is 200 MHz, the fine–delay range needs to be longer than 5 ns. Given that each CARRY4 unit has a delay of approximately 53 ps, a delay chain made up of 100 CARRY4 units is chosen. Under such circumstances, when the measured signal frequency is 4 MHz, the accuracy of phase measurement becomes:

$$\theta =4 \mathrm{M}\mathrm{H}\mathrm{z}·360°·53 \mathrm{ps}=0.076°$$

(10)

Compared with the case where only the counter is used for phase measurement, the accuracy is enhanced approximately 100 times.

As shown in Figure 12, upon entering CARRY4, the signal passes through one multiplexer and four MUXCY (multiplexer Carry) units before being output. Owing to the different delay values of the MUXCY and multiplexer, employing them separately as delay units would complicate the delay value calculation. Therefore, in this study, the entire CARRY4 is utilized as the delay unit, and its 53 ps delay precision is adequate for the study requirements. For future improvements in time-measurement accuracy, it is proposed to divide CARRY4 into two parts by grouping one MUXCY with one multiplexer and grouping three MUXCYs together. Nevertheless, this approach requires an evaluation of whether the delay error can meet the specified requirements.

The propagation path of the input signal through the delay chain composed of CARRY4 units is depicted in Figure 13. Upon entering the FPGA chip’s interior from the external environment, the signal first traverses an IBUF buffer before entering the CARRY4 delay chain. As illustrated in Figure 13, the initial CARRY4 unit encountered by the input signal is connected to CYINT, rather than CI. The reason for this is that CI lacks a connection to interface with external signals and can solely be linked to the CO of an adjacent CARRY4 unit. Commencing with the second CARRY4 unit, the connection configuration follows a CI-in and CO-out topology. The combined effect of the IBUF buffer and line delay, along with the distinct connection of the first CARRY4 unit relative to the subsequent ones, results in a considerable measurement error.

This study performs post-synthesis simulation on the aforementioned design. Initially, a specified input signal, configured to transition from a low to a high level, is applied. The time elapsed from the input signal to the output CO [3] of the first CARRY4 unit is measured, revealing a substantial delay of up to 1.453 ns. Subsequently, the time from the IBUF buffer to the output CO [3] of the first CARRY4 unit is determined to be 706 ps, as depicted in Figure 14. These measurement results indicate that the delay incurred before the signal reaches the first CARRY4 unit significantly surpasses that of a single CARRY4 unit, thereby introducing a substantial error into the measurement outcome. However, since this study determines the phase by assessing the delay of two signals and subsequently computing their difference, ensuring that the propagation–path delays of the two signals entering the FPGA are identical can mitigate this impact. Nevertheless, if one of the two signals fails to reach the first CARRY4 unit, resulting in a fine–delay measurement of 0, the aforementioned error persists. This error, ranging between 0 and 1.453 ns, remains indeterminate. To address this issue, this study introduces the following solution. In the event that the output of the first CARRY4 unit is 0, an additional clock cycle is introduced to store the fine–delay result, and a clock cycle is deducted during the delay–result calculation. This approach effectively resolves the initial-value error of the delay chain.

Subsequently, the delay of each CARRY4 unit is measured through simulation, with the measurement methodology presented in Figure 15. Statistical analysis indicates that the time difference between the output of the first CARRY4 unit and that of the second is 60 ps, while the delay between other CARRY4 outputs amounts to 53 ps. This discrepancy may stem from routing considerations, as the first CARRY4 unit is positioned slightly farther from the second. However, this variation is deemed acceptable within the context of this study.

To validate the rationality of the phase-measurement scheme proposed herein, the aforementioned logic design is implemented utilizing the XILINX ZYNQ XC7Z100 chip, with the development board’s appearance showcased in Figure 16. The experimental setup employs a dual-channel waveform generator to produce two sine signals, each featuring a 4 MHz frequency, adjustable phase, and a peak-to-peak voltage of 3.3 V. These signals are input into the development board and subsequently converted into square-wave signals with a fixed 1.8 V amplitude via a high-speed voltage-zero-crossing comparator prior to being fed into the FPGA for delay measurement. The phase difference between the two sine signals is varied from 0 degrees to 90 degrees. For each phase difference, it is maintained for a duration of 40 min, with one data point extracted from the measurement results every second. The difference between the measured phase-difference-corresponding time and the set phase-difference-corresponding time is computed to generate a histogram illustrating the measurement-error distribution across different phase conditions. Throughout the operation, the temperature of ZYNQ is monitored in real-time via the chip’s internal ADC. Owing to the cooling effect of a fan situated atop the chip, the temperature gradually elevates from an ambient 20 °C to 39 °C before stabilizing.

Since the error distribution of the measurement results under different phases exhibits no significant discrepancies, the histogram of the error distribution obtained for a phase difference of 30$°$ is presented here, as shown in Figure 17. In Figure 17, the horizontal axis denotes the error value, while the vertical axis represents the count of points falling within each error interval. Given that the delay value of each delay unit employed in the computation is 53 ps, the calculated error manifests as an integer multiple of 53 ps. Figure 17 reveals that the measured error distribution adheres to a normal distribution pattern, with nearly all errors confined within 150 ps, equivalent to three delay units. Consequently, this level of precision is deemed acceptable.

3.3. Output Power Calculation

When a Class-D full-bridge inverter drives an RLC load, the expression for the output power can be obtained using the fundamental wave analysis method as follows [45]:

$$P_{out}={\left({\displaystyle \frac{\frac{2\sqrt{2}{V}_{in}}{\pi }}{Z}}\right)}^{2}R={\displaystyle \frac{8}{{\pi }^2}}{\displaystyle \frac{V_{in}^2}{R}}\mathit{cos}(\phi {)}^2$$

(11)

where Z is the output impendence. When the output power remains constant, if the input voltage also remains unchanged, then $\mathit{cos}(\phi {)}^2/R$ remains constant. Definition:

$$C={\displaystyle \frac{P_{out}}{V_{in}^2}}{\displaystyle \frac{{\pi }^2}{8}}={\displaystyle \frac{\mathit{cos}(\phi {)}^2}{R}}$$

(12)

The variation range of R under different C and phase shift angle $\phi$ can be derived, as shown in Figure 18. It can be seen that the smaller the C, the greater the variation range of R. When the output power is required to be constant, the greater the input voltage, the larger the variable range of R.

Next, we analyze the control accuracy of the output power when the input voltage is fixed. The output power as a function of frequency is expressed as follows:

$$P_{out}={\displaystyle \frac{8}{{\pi }^2}}{\displaystyle \frac{V_{in}^2}{R}}\mathit{cos}(\phi {)}^2={\displaystyle \frac{8V_{in}^2}{{\pi }^2}}{\displaystyle \frac{R}{R^2+{(\omega L-\frac{{\omega }_0^{2}L}{\omega })}^2}}$$

(13)

Derivative of output power with respect to angular frequency:

$${\displaystyle \frac{d{P}_{out}}{d\omega }}={\displaystyle \frac{8V_{in}^2}{{\pi }^2}}\cdot {\displaystyle \frac{R\cdot 2\left(\frac{{\omega }_0^{2}L}{\omega }-\omega L\right)\cdot \left(L+\frac{{\omega }_0^{2}L}{{\omega }^2}\right)}{{\left[R^2+(\omega L-\frac{{\omega }_0^{2}L}{\omega }{)}^2\right]}^2}}$$

(14)

Assuming an ICP inductance of 2 µH, a resonant frequency of 3.4 MHz, an input voltage of 55 V, and a minimum period adjustment unit of the MOSFET drive signal of 156 ps, the percentage change in output power corresponding to a one minimum adjustment unit change in the MOSFET drive signal period at different switching frequencies is shown in Figure 19 for different equivalent load resistances R. It can be observed that the larger the equivalent load resistance, the higher the precision of frequency control. At almost 45° phase shift, the control precision is lowest for different R values. When the phase shift angle is below 45°, the smaller the phase shift angle, the higher the power control precision.

4. Simulation Analysis

To evaluate the digital control strategy during ICP start-up and plasma generation, this study conducts simulations using MATLAB 2022b. The model, constructed with Simulink’s blue components, accurately replicates physical processes. The circuit configuration is illustrated in Figure 20. Parasitic inductances of $L_{line1}$ to $L_{line8}$ is set as 8 nH. The simulation incorporates the three key parasitic capacitances of the MOSFET (Coss, Crss, Ciss), with values extracted from the c3m0065090j datasheet. These capacitances are dynamically adjusted using a lookup table that responds to input voltage variations.

In the initial stage, the load is characterized by L = 2 μH, R = 0.5 Ω, and Cr = 1100 pF, with a resonant frequency of 3.39 MHz. During ICP ignition, the equivalent inductance change rate is set at 4 μH/ms, and the resistance change rate is 40 Ω/ms [22]. The input voltage is set to 100 V, and the initial switching frequency is 5 MHz. The frequency is then reduced until the output power reaches 20 W, marking the end of the start-up process. PID control is then initiated, with the output power set to 500 W to ignite the plasma, during which the load changes rapidly. After the load stabilizes, the output power is increased to 1 kW. The changes in the main physical quantities during the entire process are shown in Figure 21.

As shown in Figure 21d, the digital control scheme has achieved good power control during rapid load changes. When the set power transitions from 500 W to 1 kW, the power supply achieves the power transition within 6 μs. When the output power is 500 W and 1 kW, the power amplifier output voltage $V_{out}$, resonant current $i_{AC}$, and the voltage $V_{ds}$, current $i_{ds}$, and drive voltage $V_{gs}$ across the MOSFET are shown in Figure 22 and Figure 23, respectively. It can be seen that when the voltage $V_{ds}$ across the MOSFET drops to 0 V, the drive voltage $V_{gs}$ rises from −4 V to 16 V, thereby achieving zero-voltage switching. As shown in Figure 21c, throughout the entire operating process, the dead time is always less than the maximum dead time, thus ensuring ZVS throughout the entire operating process.

5. Experimental Results

This paper presents a prototype designed to ascertain the viability of the digital control strategy discussed. Given the high-frequency operation of the switching components, factors including immunity to driving interference, thermal management of MOSFETs, and precedents set by other researchers in the MHz frequency range for MOSFET selection were considered [6,46]. In light of these, the SiC MOSFET (Model: C3M0065090J) is chosen for this study, and a Class-D module prototype is constructed, as shown in Figure 24. The isolated driver chip used is the NSI6601C, with a drive voltage range specified as −4 V to +16 V. The current probe model is a CYBERTEK CP8030B. It features a bandwidth of DC-50 MHz, a rise time of ≤7 ns, and can measure continuous currents up to 30 A and peak currents up to 50 A.

Owing to the extremely high operating frequency of the Class-D module in this application, excessive parasitic inductance within the PCB traces can adversely affect operation. Therefore, it is essential to minimize the parasitic inductance of the bridge arms during PCB design. The layout of the two bridge arms of the Class-D amplifier must be as symmetrical as possible. Once the PCB design is completed, the PCB layout can be exported to Q3D software (ANSYS Electromagnetics Suite 2021 R1) for finite element simulation to obtain the parasitic inductance and resistance of the power loop, thereby facilitating subsequent simulation and debugging, as shown in Figure 25. In this layout, the simulated parasitic inductance of the bridge arm traces is 8 nH, corresponding to $L_{line1}$ to $L_{line8}$ in Figure 20.

Additionally, during the experimental process, a common-mode inductor is added to the output of the DC power supply preceding the Class-D module to prevent common-mode noise from interfering with the operation of the preceding DC/DC converter. In this paper, a 1 mH common-mode inductor is used. For effective heat dissipation, the base plate of the Class-D module is an aluminum substrate with water cooling, as shown in Figure 26.

This paper utilizes the Xilinx ZYNQ-XC7Z100 FPGA as the primary control unit for implementing high-precision control of switching frequency, processing of high-speed ADC data, high-precision phase measurement, and real-time computation of dead time. The experimental platform is depicted in Figure 27.

The input voltage is set to 55 V. The resonant capacitor Cr is 1100 pF. The load coil is cylindrical and sealed with high-borosilicate glass, containing argon gas at a pressure of 76 Torr. It has a diameter of 20 mm and a length of 120 mm. Given the limited thermal endurance of high-borosilicate glass, the duration of each experiment is capped at 10 s.

The process begins with initiating the power supply at a low output power. Subsequently, a high voltage is applied to ignite the argon gas and generate plasma, after which the output power is increased to sustain the plasma. Figure 28 illustrates the simulation results of the primary physical quantities throughout the operational process, with the marked points indicating the actual measured points. This figure delineates three stages: step 1 denotes the initial low-power startup phase, step 2 indicates the transition where the output power is varied, and step 3 is the phase dedicated to maintaining plasma generation. The duration of step 2 is approximately 50 microseconds, which can be adjusted by tuning the closed-loop PID parameters as required.

At the start-up time of the Class-D module, the switching frequency is set to 4 MHz, with the output voltage and current waveforms depicted in Figure 29a, and the measured efficiency is 71%. Following this, a frequency reduction initiation commences, continuing until the preset output power of 50 W is achieved, at which the switching frequency stands at 3.85 MHz, concluding the start-up phase. Subsequently, the output power is set to 300 W, with the corresponding voltage and current waveforms illustrated in Figure 29b, and the switching frequency at this juncture is 3.67 MHz, and the measured efficiency is 90.34%. The efficiency is relatively low at low output power levels. However, as the output power increases, the efficiency significantly improves. Throughout the process, the quality factor Q of the load is greater than 10. The THD of output current is 3.11% in Figure 29a and 2.05% in Figure 29b. As evident from Figure 29, the switching frequency fluctuates by a total of 0.33 MHz during this process, achieving precise control over output power.

6. Conclusions

This paper introduces a high-precision digital control strategy for Class-D amplifiers to directly drive variable loads. It controls the output power by dynamically adjusting the frequency and ensures the achievement of ZVS through dynamic dead-time tuning. Compared to conventional approaches, this scheme does not require an impedance matching network. It controls the output power by dynamically adjusting the frequency, which allows for faster power regulation and more flexible control, showing promise for industrial application.

However, since the output power adjustment is made by altering the phase shift angle without changing the input voltage, an increase in the phase shift angle leads to increased reactive power and reduced efficiency. For future work, integrating a high-dynamic-response DC/DC converter ahead of the Class-D amplifier, managed by a unified controller, could be explored. This converter would regulate the output power while the Class-D amplifier maintains the minimum phase for ZVS. The precision of the output power control would then rely on the converter’s regulation accuracy. Employing a high-precision DPWM to manage the DC/DC converter could achieve accuracy exceeding 12 bits, significantly enhancing the precision of power control.