On the Implementation of “Dead Time” in a Synchronous Step-Down Converter

Abstract

The paper investigates and addresses the “dead time” of a synchronous step-down converter implemented with P-channel and N-channel transistors. The transistors are controlled by a single driver, and “dead time” is implemented with external circuits and Schottky diodes. The influence of the Schottky diode capacitance on “dead time” is considered. Mathematical expressions were derived, showing the ratio of the value of this capacitance to the input capacitance of the transistor and the influence of this ratio on the shape of the leading edge of the pulse for switching on the transistor. The results of computer simulations are given for different ratios of the two capacitances. It was found that the capacitance of the Schottky diode must be much lower than the input capacitance of the transistor. The results of the mathematical description and computer simulations were used to select a suitable transistor and Schottky diode and are applied in the subsequent practical implementation. Conclusions and recommendations were made for a synchronous step-down converter, as well as for other cases of implementing “dead time” in the manner considered.

1. Introduction

The main issues in the design of DC/DC converters are presented in [1]. The difference between the continuous and discontinuous current modes through the inductance is discussed, for example, in [2]. Typically, a synchronous step-down converter is implemented with two N-channel MOSFETs [3]. Issues related to the efficiency of such a converter are considered, for example, in [4,5,6,7]. The requirements for controlling MOSFETs are considered in many scientific works, such as [8,9,10,11,12]. In cases where the supply voltage does not exceed the maximum allowable gate-source voltage of a P-channel MOSFET, the upper N-channel transistor in a synchronous buck converter can be replaced by a P-channel transistor. This provides certain advantages in terms of controlling both transistors. It can be implemented by a single driver with a push–pull output, as shown in Figure 1. In this way, some additional elements needed to provide the control voltage of the upper transistor in case it is also N-channel—such as a capacitor, diode, and additional circuits—are avoided [13]. However, it should be noted that in the proposed control in Figure 1, one of the two transistors is always on, while in the case of two N-channel transistors, both can be turned off under certain circumstances. This is a known disadvantage of the variant considered in this study, which is suitable, for example, when charging low-power energy storage elements—batteries and ultracapacitors. In this case, constant current regulation and voltage limitation can be carried out, and when the maximum charging voltage is reached, the electronic regulator for this voltage remains operational, i.e., both transistors can be switched. Issues related to regulation and the rest of the control system are not the subject of consideration in this research. The charging circuits of the input capacitances of the two transistors are presented in Figure 1 (red lines) and the discharge circuits (blue lines). The additional elements to the gates of the transistors (the two resistors and the Schottky diode) are known and often recommended. Through these circuits, the so-called “dead time” is implemented when controlling the transistors. The goal is to turn one transistor on with a certain delay compared to turning the other off. This problem is known and also exists in other converters using phase leg transistors [14]. Different methods for implementing “dead time” are known [15,16,17,18,19,20]. For the circuit of a synchronous converter using two N-channel MOSFETs, controllers in an integrated circuit are proposed, with different methods for “dead time” implementation [21,22,23,24]. The proposed drivers with built-in “dead time” implementation are characterized by higher accuracy compared to the circuit considered in the article. However, they cannot be used at low supply voltages, such as for the needs of the present application.

The present work focuses on the implementation with the circuits shown in Figure 1. The operating principle is as follows:

At a low level at the driver output (when the lower transistor at its output is turned on), the input capacitance of the lower N-channel transistor is discharged through diode $D_1$ and the driver output. At the same time, the input capacitance of the upper P-channel transistor is charged through resistor $R_3$ to a voltage approximately equal to the supply +U (the difference is due to the voltage on the transistor at the driver output). At a high level at the driver output (when the upper transistor at its output is turned on), the input capacitance of the upper P-channel transistor is discharged through diode $D_2$ and the driver output. At the same time, the input capacitance of the lower N-channel transistor is charged through resistor $R_1$ to a voltage approximately equal to the supply +U (the difference is due to the voltage on the transistor at the driver output). Since the charging of the input capacitances occurs through a resistor, the idea is to change its value and the charging time constant to change the turn-on delay time. It can be longer than that of turn-off because the capacitance discharge occurs through the low-resistance Schottky diode [25].

In the literature known to the authors, no methodology for sizing these circuits is described, especially with regard to the problem described below. This problem may occur in low-power converters where the input power sources are small photovoltaics, piezoelectric elements, etc. In these cases, the transistors used are low-power. Characteristic features of low-power MOSFETs are the low threshold voltage $U_{th}$ (usually 0.7–1.5 V) and the low value of the input capacitance $C_{iss}$ (usually tens to hundreds of pF). When controlling power MOSFETs, the described problem oes not arise since their threshold voltage is high (usually above 4.5 V) and their input capacitance is larger (up to several tens of nF).

Description of the problem. When controlling the transistors in the manner shown in Figure 1, the authors observed the oscillograms shown in Figure 2 and Figure 3. The supply voltage of the converter was 3.3 V. In Figure 2-CH2, a steep trailing edge is observed in the voltage of the drains of both transistors (point A, Figure 1), i.e., the lower transistor turned on very quickly. At the same time, a sharp decrease is observed in the supply voltage on CH1. These are signs of simultaneous conduction of both transistors, i.e., a single-arm short circuit. From CH1 in Figure 3, it can be seen that at the same moment in time, the gate-source voltage of the lower transistor increased steeply, and it was established that the rate of increase was not affected by the change in the value of the resistor R1 from Figure 1. This prompted a more detailed study of these circuits as described below.

2. Mathematical Descriptions and Study

Essential to the solution of the described problem is the consideration of the influence of the Schottky diode capacitance when applying a signal to turn on the transistor. The study was carried out using the circuit shown in Figure 4, where the Schottky diode capacitance $C_j$ and the input capacitance of the transistor $C_{iss}$ were added to the elements $D_1, R_1, R_2$ in Figure 1. The equivalent circuit for mathematical description is presented in Figure 5.

It was assumed that the input voltage was increased stepwise to a value of 1 (single input pulse $u_{in}=1$), and the change in the output voltage $u_{GS}$, which is the gate-source voltage of the transistor, was examined.

The expressions for the impedances from the circuit in Figure 5 in operator form are as follows:

$$Z_1\left(s\right)={\displaystyle \frac{R_1}{1+s·R_1·C_1}};Z_2\left(s\right)={\displaystyle \frac{R_2}{1+s·R_2·C_2}}.$$

(1)

For a single input, the output voltage has the following form:

$$u_{GS}\left(s\right)={\displaystyle \frac{1}{s}}.{\displaystyle \frac{Z_2\left(s\right)}{Z_1\left(s\right)+Z_2\left(s\right)}}.$$

(2)

It can also be represented as follows:

$$u_{GS}\left(s\right)={\displaystyle \frac{A}{a+s}}+{\displaystyle \frac{B}{s\left(a+s\right)}},$$

(3)

where

$$A={\displaystyle \frac{C_1}{C_1+C_2}},$$

(4)

$$B={\displaystyle \frac{R_2}{R_1+R_2}},$$

$$a={\displaystyle \frac{1}{\tau }},$$

$$\tau ={\displaystyle \frac{R_1·R_2·\left(C_1+C_2\right)}{R_1+R_2}}.$$

When switching from the Laplace domain to the time domain, the change in output voltage over time is obtained:

$$u_{GS}\left(t\right)={A·e}^{-{\displaystyle \frac{t}{\tau }}}+B·\left(1-e^{-{\displaystyle \frac{t}{\tau }}}\right).$$

(5)

Figure 6 presents the two terms of expression (5)—the first with a blue line, the second—with a green line, and their sum—with a red line.

From Figure 6, it can be observed that the output voltage $u_{GS}$, which is the gate-source voltage of the transistor, has a sharp increase at the initial moment, which depends on the ratio of the two capacitances $C_1$ (the capacitance of the Schottky diode) and $C_2$ (the input capacitance of the MOSFET). For example, if $C_2\gg C_1$ the value of the initial increase will be of a negligible value. If the two capacitances are equal, this value will be half the value of the input voltage. However, if $C_1\gg C_2$, the initial increase may be close to the value of the input voltage. This effect is observed in the upper oscillogram of Figure 3. The problem is that, depending on the ratio of the two capacitances, the value of the initial increase may be greater than the value of the threshold voltage $U_{th}$ of the transistor. In such a situation, “dead time” is not implemented, and the effect described in the introduction is observed.

Formula (5) can be used to determine the value of the “dead time” depending on the value of the resistor $R_1$ at known other values. For this purpose, it is presented as follows:

$$u_{GS}\left(t\right)={\left(A-B\right)e}^{-{\displaystyle \frac{t}{\tau }}}+B.$$

(6)

By substituting $t=t_d$ and $u_{GS}\left(t_d\right)=U_{th}$, we obtain the following expression:

$$t_d=\tau ·ln{\displaystyle \frac{A-B}{U_{th}-B}}.$$

(7)

Substituting the values from (4) into (7) gives the following:

$$t_d={\displaystyle \frac{R_1·R_2·\left(C_1+C_2\right)}{R_1+R_2}}·ln{\displaystyle \frac{\frac{C_1}{C_1+C_2}-\frac{R_2}{R_1+R_2}}{U_{th}-\frac{R_2}{R_1+R_2}}}.$$

(8)

Since the equations were derived using a unit input, the value of $U_{th}$ should be set in units relative to the maximum value of the driver’s output voltage. For example, if it is 3 V, and the threshold voltage is 1.8 V, then in Formula (8), $U_{th}$ = 0.6.

In Formula (8), the capacitance values are known from reference data for the selected elements—Schottky diode, MOSFET, and Zener diode parallel to the gate-source junction. The value of the resistor $R_2$ is usually 10 K. It remains to calculate the value of $t_d$ for different values of $R_1$ and choose the appropriate value of the resistor.

For example, for variant 4 of

Table 1. Variants for providing “dead time” for a signal to turn on the lower transistor.

	Schottky Diode (Diode) Capacitance, pF	Transistor, Zener Diode Capacitance, pF	Value of A, Starting Voltage G-S at 3 V from the Driver, V	$\mathbf{Transistor} {\mathit{U}}_{\mathit{G}\mathit{S}\left(\mathit{t}\mathit{h}\right)}$, min. Value, V
Variant 1	SS34,$C_j=500 \mathrm{p}\mathrm{F}$	BSS214N, $C_{iss}=107 \mathrm{p}\mathrm{F}$	0.837, 2.51 V	0.7
Variant 2	SS34, $C_j=500 \mathrm{p}\mathrm{F}$	UT6402G, $C_{iss}=265 \mathrm{p}\mathrm{F}$	0.654, 1.962 V	1.0
Variant 3	SS14, $C_j=140 \mathrm{p}\mathrm{F}$	UT6402G, $C_{iss}=265 \mathrm{p}\mathrm{F}$	0.345, 1.035 V	1.0
Variant 4	SS14, $C_j=140 \mathrm{p}\mathrm{F}$	UT6402G, $C_{iss}=265 \mathrm{p}\mathrm{F}$, BZM55C5V1, $C_{jz}=100 \mathrm{p}\mathrm{F}$	0.277, 0.831 V	1.0
Variant 5	1N4148W-G, $C_j=2 \mathrm{p}\mathrm{F}$	UT6402G, $C_{iss}=265 \mathrm{p}\mathrm{F}$	0.0075, 0.0225 V	1.0
Variant 6	1N4148W-G, $C_j=2\mathrm{p}\mathrm{F}$	UT6402G, $C_{iss}=265\mathrm{p}\mathrm{F}$, BZM55C5V1, $C_{jz}=100 \mathrm{p}\mathrm{F}$	0.00544, 0.0163 V	1.0

considered below, the values are as follows: $C_1=140 \mathrm{p}\mathrm{F}$; $C_2=365 \mathrm{p}\mathrm{F}$; $R_2=10 \mathrm{K}$. With a minimum threshold voltage of 1 V for the MOSFET and an output voltage from the driver of 3 V, in Formula (8), $U_{th}={\displaystyle \frac{1}{3}}\approx 0.33$. After calculation, a value of $t_d$ = 111 ns is obtained for resistor value $R_1=500 \mathsf{\Omega }$.

A computer simulation using the program OrCAD 9.2 was performed using models of real diodes and transistors. The results are shown and commented on below.

Variant 1—Schottky diode 1N5819 with a capacitance of 150 pF [26], transistor with an input capacitance of 150 pF. The input signal had a maximum value of 5 V. The simulation circuit and the results are shown in Figure 7.

It can be observed that when a signal was applied to turn on, the initial peak of the output voltage was 2.5 V, consistent with coefficient A in Figure 6. When switched off, an initial retention of about 0.3 V (the voltage across the switched-on Schottky diode) was observed. It is clear that this combination will not achieve “dead time” implementation for transistors with a threshold voltage below 2.5 V.

Variant 2—Schottky diode 1N5819 with a capacitance of 150 pF [26], transistor with an input capacitance of 500 pF. The input signal had a maximum value of 5 V. The simulation circuit and the results are shown in Figure 8.

It can be observed that when a signal was applied to turn on, the initial peak of the output voltage was approximately 1 V, consistent with coefficient A in Figure 6. When switched off, an initial retention of about 0.3 V (the voltage across the switched-on Schottky diode) was observed. It is clear that this combination will not achieve “dead time” implementation for transistors with a threshold voltage below 1 V. When the input capacitance of the transistor increased, the initial spike of the gate-source voltage decreased.

Variant 3—Silicon diode 1N4148 with a capacitance of 3 pF [27], transistor with an input capacitance of 500 pF. The input signal had a maximum value of 5 V. The simulation circuit and the results are presented in Figure 9. This variant was chosen because pulse diodes with a PN junction are characterized by significantly lower capacitance values.

This variant corresponds to the condition $C_2\gg C_1$.

It can be observed that when a signal was applied to turn on, the initial peak of the output voltage was negligibly small, consistent with coefficient A in Figure 6. It is clear that this combination makes implementing “dead time” when turning on the lower transistor easiest even at low threshold voltages. When turning off, an initial voltage retention of about 0.7 V (the voltage across the switched-on diode) was observed. However, this is problematic since, at the same moment, a signal is applied to turn on the upper transistor of the synchronous converter, and if the lower transistor has a threshold voltage of approximately 0.7 V, it may remain on for a short time. This would make it difficult to implement “dead time” when turning on the upper transistor. For this reason, the authors recommend using Schottky diodes, as shown in the circuit in Figure 1.

Variant 4—Connecting a Zener diode in parallel with the gate-source junction of the transistor. The diode has protective functions described in the literature [8,9]. The schematic diagram together with the capacitances is shown in Figure 10: Schottky diode 1N5819 with a capacitance of 150 pF [23], transistor with an input capacitance of 500 pF, Zener diode BZX84C5V6 surface-mount device with a capacitance of 200 pF [28]. The input signal had a maximum value of 5 V. The simulation circuit and the results are shown in Figure 11.

This variant differs from variant 2 only in the inclusion of the Zener diode. Comparison of the timing diagrams in Figure 11 with those in Figure 8 shows that the initial peak was reduced to about 0.9 V, which would facilitate the implementation of “dead time” for transistors with a threshold voltage above 1 V. In addition to the protective function, the authors recommend placing a Zener diode for the reasons discussed in this article as well.

3. Experiment

The initially implemented variant for the lower transistor in Figure 1 is the following: transistor BSS214N with capacitance $C_{iss}=107 \mathrm{p}\mathrm{F}$ and threshold voltage $U_{th}=0.7 \mathrm{V}$ [29] and a Schottky diode SS34 with capacitance $C_j=1 \mathrm{n}\mathrm{F}÷500 \mathrm{p}\mathrm{F}$ [30]. The oscillograms shown in Figure 2 and Figure 3 correspond to this variant. From the previous consideration, it is clear that this variant is unsuitable. Table 1 shows various possible variants for implementation—combinations of Schottky diodes and transistors with or without a Zener diode. Those shown in red are unsuitable, while the one in yellow is not preferable, since the results are close to the limit. From the point of view of “dead time”, variants 4, 5, and 6 are suitable—as shown in green. Variants 5 and 6 are not preferred due to the considerations expressed when commenting on the results in Figure 9. The preferred implementation variant is 4, shown in blue in the first column of Table 1. It uses a Schottky diode SS14, which has a significantly lower capacitance than SS34 [31].

The last three variants in Table 1 were evaluated from the following point of view: when turning on the upper transistor in Figure 1 and increasing the voltage at point A, through the feedback capacitance $C_{rss}$ of the lower transistor, its gate-source capacitance is charged (Miller effect) [32]. Shortly before this (to ensure the “dead time”), there is a low level at the driver output. In this situation, due to the feedback, the input capacitance would be charged to a voltage equal to the sum of the voltage drop on the Schottky diode (or the pulse diode with a PN junction) and the voltage on the lower transistor of the driver. This sum of voltages must remain less than the threshold voltage of the lower transistor, otherwise it may turn on as well. With a sharp increase in voltage at point A, the consideration made in the previous part can be applied. The results in

Table 2. Ensuring the off state of the lower transistor through the feedback capacitance when the upper transistor is turned on.

	Schottky Diode (Diode), Forward Voltage, V Driver Output Low Voltage, V	$\mathbf{UT}6402\mathbf{G}, {\mathit{C}}_{\mathit{R}\mathit{s}\mathit{s}}=56 \mathbf{p}\mathbf{F}$	Value of Starting Voltage G-S at 3 V from D-S,V	$\mathbf{Transistor} {\mathit{U}}_{\mathit{G}\mathit{S}\left(\mathit{t}\mathit{h}\right)}$, min. Value, V
Variant 4	SS14, $0.3V$, LPV7215, $V_{oL}=0.3 \mathrm{V}$ Total, 0.6 V < 1 V	UT6402G, $C_{iss}=265 \mathrm{p}\mathrm{F}$, BZM55C5V1, $C_{jz}=100 \mathrm{p}\mathrm{F}$	0.4 V	1.0
Variant 5	1N4148W-G, $0.75 \mathrm{V}$ LPV7215, $V_{oL}=0.3 \mathrm{V}$ Total, 1.05 V > 1 V	UT6402G, $C_{iss}=265 \mathrm{p}\mathrm{F}$	0.523 V	1.0
Variant 6	1N4148W-G, $0.75 \mathrm{V}$ LPV7215, $V_{oL}=0.3 \mathrm{V}$ Total, 1.05 V > 1 V	UT6402G, $C_{iss}=265 \mathrm{p}\mathrm{F}$, BZM55C5V1, $C_{jz}=100 \mathrm{p}\mathrm{F}$	0.4 V	1.0

show that from such a point of view, variants 5 and 6 are borderline (shown in yellow). Variant 4 (in green) is also suitable in this regard.

After the implementation assessment, variant 4 was chosen, and the section of the board corresponding to the circuit under consideration is shown in Figure 12. All electronic components correspond to variant 4 (shown in blue in the first column of Table 2).

In the variants presented in the two tables, the authors compared the possibilities for an accessible and quick solution to the problem described at the beginning of the article. Other combinations of MOSFETs, Schottky diodes, and Zener diodes are also possible. During initial development, different options should be sought and evaluated in terms of price and market availability before a choice is made.

Schottky diodes $D_6$ and $D_7$ were SS14 and correspond to $D_2$ and $D_1$ in Figure 1. Resistors $R_{10}$ and $R_{13}$ consisted of two parallel-connected resistors with a value of 1 K and correspond to $R_3$ and $R_1$ in Figure 1. Resistors $R_9$ and $R_{10}$ had a value of 10 K and correspond to $R_4$ and $R_2$ in Figure 1. Zener diodes BZM55C5V1 were soldered to these resistors. Transistor M1 (P-channel) was BSP250. Transistor M2 (N-channel) was UT6402G. The two drains pins were connected externally to the left terminal of the inductor in the circuit if Figure 1 (point A—Figure 1).

Figure 13 and Figure 14 show the recorded oscillograms. The operating frequency of the converter was 17 kHz, and the supply voltage was 3.3 V.

From CH2 in Figure 13, the gradual increase in the gate-source voltage of the N-channel transistor when turned on (to implement “dead time” when turning off the P-channel transistor) and a rapid decrease (to implement “dead time” when turning on the P-channel transistor) are observed.

From CH2 in Figure 14, it can be observed that there were no short-term dips in the supply voltage both during switching on and off of the N-channel transistor. The measured current consumed by the power source in this case was significantly lower than in the case shown in Figure 2. This is proofs of the correct implementation of “dead time” according to the circuit in Figure 10 for the two transistors in a synchronous step-down converter.

It should be noted that with a change in temperature, the parameters of the diodes and the transistor change. The authors worked with the minimum threshold voltage of transistor UT6402 at the highest temperature, taken from the graphical dependence in [33].

4. Conclusions

The paper investigated the “dead time” of a synchronous step-down converter implemented with P-channel and N-channel transistors. The implementation of “dead time” with external components when controlled by a driver with a push–pull output was considered. The main attention was paid to the influence of the Schottky diode capacitance. The main conclusions are as follows:

• It is recommended to implement external circuits for the gate of the transistor according to the circuit in Figure 10.
• When designing “dead time” circuits, it is necessary that the Schottky diode capacitance be significantly lower than the input capacitance of the transistor.
• Based on Formula (5) and Figure 6, compliance with the threshold voltage of the MOSFET must also be checked.
• It is not recommended to use a pulse diode with a PN junction instead of a Schottky diode due to the larger forward voltage drop across the diode with a PN junction. When the upper transistor is turned on, due to feedback capacitance, it is possible for the input capacitance of the lower transistor to be charged to a voltage higher than the threshold voltage.
• It is recommended to include Zener diodes with the lowest possible reference voltage (but greater than the maximum threshold voltage of the lower transistor) in parallel with the gate-source junction. Zener diodes with a lower reference voltage have a greater capacitance. In addition to their protective function, these diodes also facilitate the implementation of “dead time.”
• Formula (8) can be used to determine the value of “dead time” $t_d$ at different values of the resistor $R_1$ and known values of the other quantities.

The considerations and conclusions presented in this article refer not only to the circuit in Figure 1. They can be applied in all cases of implementation of “dead time” according to the circuit of Figure 10.

The results obtained in this article can be applied to low-power systems such as energy harvesting systems, for example, with a piezoelectric element or a small photovoltaic system; battery or ultracapacitor charging systems; and powering IoT systems.