Design and Experimental Validation of a High-Boost Full-Bridge Converter with Extended ZVS Range and Stable Efficiency Under Wide Load Variations

Abstract

This paper introduces a new four-switch, high-voltage, high-step-up converter employing two transformers. The topology enables Zero-Voltage Switching (ZVS) across all primary switches for operating conditions ranging from no load to full load. A voltage-quadrupler and a voltage-doubler rectifier are used on the secondary sides of the transformers, enabling reduced turn-off current for the voltage-quadrupler diodes and Zero-Current Switching (ZCS) turn-off for the voltage-doubler diodes, thereby ensuring high efficiency across diverse load levels. Notably, the voltage stress experienced by the voltage-multiplier diodes is significantly lower than the output voltage, thereby rendering the converter exceptionally suitable for high-voltage applications such as electron beam welding (EBW). The voltage gain surpasses that of the conventional phase-shift full-bridge (PSFB) converter, permitting a lower transformer turns ratio and thus reducing winding resistivity. The removal of the substantial output inductor leads to a lighter and more compact design, eliminating insulation concerns associated with inductor windings. This paper details the operation of the proposed converter, supported by experimental results from a 500-W prototype with a 150-V input and 2-kV output, which confirm its high performance and operational advantages.

1. Introduction

High-voltage power supplies (HVPS) are critical components in various applications, ranging from industrial processes to advanced scientific research. HVPS are available in a broad range of sizes, from pocket-sized units [1] to larger dimensions [2], and can deliver power from low to very high levels. HVPS play a crucial role in many advanced applications, such as particle accelerators, medical imaging, and industrial equipment, including microwave generators, electrostatic precipitators, physical experiments, and X-ray generators.

Among various DC/DC converters, resonant converters, leveraging LC combinations such as the LLC configuration, enable high-frequency (HF) operation of the converter [3], while simultaneously reducing the converter size at elevated frequencies. The importance of high efficiency and high-voltage gain in converters is particularly critical in high-power HVPS applications such as electron beam welding (EBW). This significance has led to increased interest in the use of resonant converters, whether single-phase or three-phase, to achieve better performance and reliability [4,5]. One of the key converter topologies used in these systems is the phase-shift full-bridge (PSFB) converter. Thanks to its Zero-Voltage Switching (ZVS) capability, the PSFB effectively reduces switching losses and electromagnetic interference, making it highly suitable for high-voltage applications.

The PSFB converter enables high-power operation by maintaining ZVS across a wide load range and keeping switch stress at the input level, reducing switching losses and boosting reliability, yet its principal limitation is the restricted ZVS range of the lagging-leg switches under varying load. This limitation primarily stems from the transformer’s leakage inductance, whose energy-storage capacity is limited and thus cannot accommodate large load variations [6]. This issue is critical in industry due to large nominal-load fluctuations. While soft switching in standard PSFB converters can be maintained over a narrow load range, efficiency drops markedly at light loads, hurting performance and cost-effectiveness. Research seeks better load adaptability and efficiency across the load spectrum. Approaches include reducing magnetizing inductance (but with higher conduction losses and lower power density), adding a series external inductor or increasing transformer leakage inductance (raising duty-cycle losses and secondary stress), and employing synchronous double rectifiers to cut conduction losses and achieve ZVS during switching, minimizing overall switching losses. An example of this is the Phase-shifted PWM-controlled DC/DC converter with synchronous rectifiers, which has been introduced for photovoltaic applications [7].

To ensure ZVS of the lagging switches, various techniques have been developed. One such approach involves employing two series-connected transformers, leveraging the magnetizing inductors of both to fully charge and discharge the switches’ junction capacitances, thus achieving ZVS [8]. In many studies, such as [9], replacing a larger transformer with two smaller transformers of similar specifications—though it increases the overall cost—can lead to improved performance and higher efficiency of the converter. Other approaches include utilizing multi-state switching cells, such as the three-state switching cell (3SSC) [10] and the four-state switching cell (4SSC) [11]. These arrangements aid in the reduction of magnetic components’ dimensions, mass, and volume, while also alleviating the current stress on switches. Additionally, they markedly improve the voltage gain, with the extent of enhancement directly related to the number of modules employed. However, the lack of galvanic isolation between the voltages of input and output stages, coupled with a current-fed topology, constrains their applicability in high-voltage environments. In [12], a high-boost isolated DC–DC converter is proposed for DC microgrid applications, employing an integrated active switched-capacitor (ASC) cell. However, this ASC converter primarily offers Zero-Current Switching (ZCS) turn-off for the diodes and ZCS turn-on for the switches. Applying an energy-recovery circuit (ERC) to the output side of the conventional PSFB converter eliminates the loss of ZVS, duty-cycle loss, and circulating current [13].

For high step-up gain and high-voltage applications such as EBW, increasing the transformer turns ratio is usually necessary to achieve a higher output voltage. However, this approach introduces insulation challenges at high voltages and, due to the proportional increase in leakage inductance, adversely affects the voltage step-up ratio. To mitigate these issues, voltage-multiplier cells (VMC) are often connected on the output side, enabling comparable voltage gains with a reduced transformer turns ratio [14]. Additionally, the use of an auxiliary half-bridge (HB) transformer in the PSFB converter structure has been theoretically analyzed in [15]. Another approach involves the use of a coupled inductor and/or built-in transformer VMC structure, such as those discussed in [16,17]. For example, a modified VMC has been applied to a single-switch boost converter to enhance voltage gain in [16]. However, the power delivery capacity of this solution remains limited due to its single-switch configuration. In [17], although two switches are employed with the second switch operating in a complementary manner to the first, the voltage gain obtained does not represent a significant improvement in relation to the converter’s size. To further increase voltage and power capacity, researchers have developed modular and multilevel versions of the PSFB. These configurations, such as the asymmetrical input-parallel, output-series (IPOS) and input-parallel, output-parallel (IPOP) topologies, allow multiple units to work together seamlessly. They offer advantages like scalability, fault tolerance, and reduced stress on individual components, enabling the construction of very high-voltage systems. For example, Power output can be enhanced using interleaved, IPOS full-bridge converters [18], which incorporate voltage-doubler cells on the secondary sides, achieving high-voltage gain but primarily suited for low input voltage applications. Also, in [2], an asymmetrical modular IPOP phase-shifted full-bridge (IPOP-PSFB) converter is proposed for high-power uses, to enhance overall system efficiency.

In comparison to voltage-fed converters, current-fed topologies typically offer higher voltage gains but face substantial challenges at high input voltages, where switches must sustain substantial voltage stresses. A high-voltage, isolated DC–DC topology with a full-bridge (FB) current-fed quasi-Z-source (qZS) has been proposed in [19]. This converter employs duty cycle (D) control to enable both boost and buck modes, effectively addressing start-up challenges. The converter is in boost mode when parameter D is greater than 50%. Within the qZS network, a voltage clamping loop plays a crucial role in mitigating voltage spikes across the switches, ensuring stable and reliable operation. To overcome these difficulties, several high-voltage gain, soft-switching solutions have been proposed—for example, circuits where ZCS is achieved for output diodes and main switches turn on under ZVS conditions [20]. However, in high-input-voltage scenarios, the main switches experience high-voltage stresses. A flyback-forward converter that has a secondary transformer connected in series with a voltage-doubler rectifier has been introduced [21], where two main switches operate with ZVS and the voltage-doubler diodes switch under zero-current conditions. Despite these advantages, the current-fed configuration is less suitable for high-input-voltage applications.

Innovations involving coupled inductors, integrated with single or multiple switching devices, have also been explored [22,23,24,25]. For instance, a four-switch, parallel-input structure with dual coupled inductors was presented in [23], demonstrating potential for high-boost gains. In [24], to further boost voltage gain, a voltage-multiplier cell was added to the output. Similarly, a voltage-multiplier cell and a three-winding coupled inductor for a dual-switch converter suggested in [25]. Other work, such as [26], evaluated input-parallel, output-series configurations with VMCs, highlighting advantages such as electrical isolation and high gain, though the voltage stress on main switches in these topologies remains significant. To mitigate these stresses, a full soft-switching range dual FB converter was introduced in [27]. This design uses eight switches—four MOSFETs and four IGBTs—and employs two output-series transformers alongside a voltage-doubler rectifier on one secondary side. Despite its high performance, the increased complexity and decreased reliability due to the higher number of switches present practical challenges. Alternatively, a full-bridge circuit with a non-dissipative snubber and an additional active switch on the secondary side has been proposed to eliminate circulating currents and duty-cycle losses [28]. Still, voltage spikes across secondary rectifier diodes, worsened by higher leakage inductance, constitute a substantial problem, necessitating the use of overrated diodes and inductors to withstand these spikes. To address this, a clamping diode circuit on the primary side of the transformer introduced in [29], reducing voltage spikes. At the same time, asymmetrical pulse-width modulation (APWM) techniques decrease RMS currents and conduction losses. Achieving ZVS of the main switches through passive auxiliary circuits has also been suggested [30], where during freewheeling, the primary current drops to the magnetizing current, eliminating circulating losses at full load.

Despite these advancements, the high-step-up gain characteristic remains a critical feature—especially for applications like EBW—where the ability to achieve substantial voltage transformation efficiently is paramount. In this context, the present study proposes a novel topology featuring a combined half-bridge and full-bridge transformer with integrated VMCs on each secondary side, as depicted in Figure 1. Compared to the conventional PSFB converter, this configuration extends the lagging switches’ ZVS range by leveraging the magnetizing current of both transformers, eliminating the need to increase leakage inductance. The resonance between the voltage-doubler capacitors and the full-bridge transformer’s leakage inductance significantly reduces the current stresses on the voltage-quadrupler diodes during switching intervals. Notably, the resonant frequency ($f_r$) of the half-bridge section is tuned to achieve ZCS for the voltage-doubler diodes, thereby decreasing current flowing through the primary side. This yields substantial RMS-current reduction and lowered conduction losses relative to the conventional PSFB. Furthermore, the suggested converter achieves approximately five times higher voltage gain relative to a standard PSFB, making it an ideal candidate for high-boost and high-voltage applications requiring exceptional efficiency and performance.

Following this, Section 2 describes the operating principles and provides a comprehensive theoretical analysis of the suggested converter. Section 3 offers detailed design guidelines and criteria for component selection, ensuring optimal performance. Section 4 presents the experimental results from a prototype with specifications of Vin = 150 V, Vout = 2000 V, and Pout = 500 W, which confirm the viability and efficacy of the proposed topology. Finally, Section 5 provides a summary of the study’s findings.

2. Proposed Converter Structure

2.1. Operational Principles

Figure 1 and Figure 2 illustrate the circuit diagram and the steady-state operating waveforms of the suggested converter. Its operational principles are divided into two symmetrical parts, with the first half-cycle described as follows. It is assumed that the capacitances $C_{O1}$ and $C_{O2}$ are significantly larger than $C_{S1}$ and $C_{S2}$. Additionally, the voltage-multiplier capacitor $C_P$ is assumed to be much larger than $n_2^2·(C_{S3}\left|\right|C_{S4})$, where $C_P$ is referred to the primary side. The duty cycle (D) is taken as 0.5, which indicates that each switch is driven for half of the switching period. The $f_r$ is established by the interaction between the leakage inductance of the HB transformer and the reflected voltage-doubler capacitors. The switching frequency ($f_s$) is maintained close to this $f_r$. The converter’s control schematic is shown in Figure 3. Initially, the output voltage is sampled using two resistors. The sampled signal is then applied to an isolated DC interface. The isolated signal is fed into an LPC1768 microcontroller, which compares it to a reference to produce an output error signal. This error is processed by a PI controller, whose parameters are implemented in the microcontroller. Finally, the microcontroller adjusts the phase-shift command to the extent determined by the PI controller. The appropriate dead time for the leading and lagging branches has been implemented in the microcontroller. Ultimately, the microcontroller generates four pulses, which drive the optocouplers; the optocoupler outputs then convert these into gate pulses for the converter’s MOSFETs.

According to the half-bridge LLC converter analysis in [31], the voltage gain of this HB section remains nearly constant under varying load conditions, implying that $V_2$ is steady. Consequently, $V_1$ and $V_2$ added together make up the total output voltage, with voltage regulation achieved by controlling $V_1$ through phase-shifted switching techniques. The operating modes of the system are illustrated in Figure 4, with each mode’s performance described as follows.

• Mode 1 (${\mathit{t}}_{\mathbf{0}}-{\mathit{t}}_{\mathbf{1}}$). At $t_0$, ZVS of the lagging-leg switch $S_2$ is achieved by the magnetizing currents $I_{Lm1}$ and $I_{Lm2}$. Consequently, the junction capacitor of $S_2$ is discharged while the voltage across $S_4$ rises to $V_{in}$. The leading-leg switch $S_1$ is conducting, causing $V_{p1}$ to ramp from 0 to $V_{in}$ at $t_0$. In addition, the primary current $I_{pri1}$ increases due to resonance between the voltage-doubling capacitors and the leakage inductor $L_{lk1}$. When the primary-side current exceeds the magnetizing current of the transformer, a current $I_{sec1}$ flows through diodes $D_1$ and $D_3$, contributing to the charging of $C_{S_2}$ and the discharging of $C_{S_1}$, respectively. In this mode, $I_{pri2}$ becomes negative, forward-biasing $D_6$ and charging $C_{S_4}$. The governing equations for the primary and magnetizing currents are derived as follows Equations (1)∼(9). Equations (1) and (2) are obtained from solving the Laplace-domain equations. Equation (3) pertains to the primary voltage of the full-bridge transformer. Equation (3) expresses the turn ratio of the secondary winding to the primary winding of the transformer. Equations (8) and (9) relate to the resonant frequencies of the transformer in the full-bridge and half-bridge configurations.

$$I_{pri1}\left(t\right)={\displaystyle \frac{n_1}{Z_{0_1}}}·[n_1{V}_{in}-V_{C{s}_2}\left(t_0\right)]·sin\left({\omega }_{r_1}(t-t_0)\right)+I_{Lm1}\left(t\right)$$

(1)

$$I_{Lm1}\left(t\right)=I_{Lm1}\left(t_0\right)·cos\left({\omega }_m(t-t_0)\right)+{\displaystyle \frac{V_{C{s}_2}\left(t_0\right)}{n_1·Z_{m1}}}·sin\left({\omega }_m(t-t_0)\right)$$

(2)

$$V_{P1}=V_{Pri1}+V_{Lk1}$$

(3)

$$n_i={\displaystyle \frac{N_{s_i}}{N_{p_i}}},i=1,2$$

(4)

$${\omega }_{m1}={\displaystyle \frac{1}{n_1\sqrt{L_{m1}{C}_{r1}}}}$$

(5)

$$Z_{0_1}=n_1\sqrt{{\displaystyle \frac{L_{lk1}}{C_{r1}}}}$$

(6)

$$Z_{m1}={\displaystyle \frac{1}{n_1}}\sqrt{{\displaystyle \frac{L_{m1}}{C_{r1}}}}$$

(7)

$${\omega }_{r_i}={\displaystyle \frac{1}{n_i\sqrt{L_{l{k}_i}{C}_{r_i}}}},i=1,2$$

(8)

$$C_{r1}=C_{s1}\left|\right|C_{s2},C_{r2}=C_{s3}\left|\right|C_{s4}$$

(9)

• Mode 2 (${\mathit{t}}_{\mathbf{1}}-{\mathit{t}}_{\mathbf{2}}$). At $t_1$, a gate pulse is applied to $S_2$, and it turns on under the ZVS condition. The current $I_{pri1}$ exceeds $I_{Lm1}$, so on the secondary side of transformer $T_1$, diodes $D_1$ and $D_3$ conduct, and resonance persists between the voltage-doubling capacitors and the leakage inductor $L_{lk1}$. Because this mode closely resembles Mode 1, the equations derived for Mode 1 remain applicable to Mode 2 as well.

• Mode 3 (${\mathit{t}}_{\mathbf{2}}-{\mathit{t}}_{\mathbf{3}}$). This operating mode of the converter is initiated with the shutdown of switch $S_1$. The attainment of ZVS for $S_3$ is achieved through the positive primary current $I_{pri1}$, its traversal through the junction capacitors of $S_1$ and $S_3$ and causing $V_{p1}$ decreases to zero. At $t_2$, $I_{pri1}$ exceeds $I_{Lm1}$, continuing conduction of $D_1$ and $D_3$. $D_3$ is forward biased, so the voltage across $Lm1$ becomes ${\displaystyle \frac{V_{C_{S_2}}}{n_1}}$. Consequently, a negative voltage which of ${\displaystyle \frac{-V_{C_{S_2}}}{n_1}}$ is utilized for the leakage inductor of $T_1$, causing $I_{pri1}$ to decrease rapidly toward the magnetizing current.

• Mode 4 (${\mathit{t}}_{\mathbf{3}}-{\mathit{t}}_{\mathbf{4}}$). Because of the negative voltage across $L_{lk1}$, $I_{pri1}$ decreases until it becomes less than $I_{Lm1}$. This causes the current in the output diodes $D_1$ and $D_3$ to reverse, making these diodes reverse-biased, and discharging their junction capacitors. Simultaneously, $D_2$ and $D_4$ are charged/discharged, respectively. The voltage-quadrupler diodes are off during this interval, and $T_1$ does not convey energy to the converter output. $I_{pri1}$ becomes equal to $I_{Lm1}$ and flows reversely through $S_3$, ensuring full discharge of its junction capacitor and maintaining ZVS. In the latter part of the mode mentioned above, two events coincide: (i) the voltage on the junction capacitor of $S_1$ is charged to the input source level, and (ii) the primary current $I_{pri1}$ flows through the body diode of $S_3$.

• Mode 5 (${\mathit{t}}_{\mathbf{4}}-{\mathit{t}}_{\mathbf{5}}$). $S_3$ is turned on and $V_{p1}$ is maintained at 0 V. The $I_{Lm1}$ passes through $S_2$, $S_3$ and the primary side of transformer $T_1$ which results in increased conduction loss. $I_{pri2}$ exhibits sinusoidal behavior because the leakage inductor of $T_2$ resonates with voltage-doubler capacitors on the $T_2$’s secondary side. The magnitude of $I_{pri2}$ exceeds $I_{Lm2}$, causing $D_6$ to conduct. At the end of this mode, $I_{pri2}$ equals $I_{Lm2}$.

• Mode 6 (${\mathit{t}}_{\mathbf{5}}-{\mathit{t}}_{\mathbf{6}}$). At $t_5$, $I_{pri2}$ equals $I_{Lm2}$ and then its magnitude begins to decrease. As a result, $I_{sec2}$ reverses direction, passing through junction capacitors of $D_5$ and $D_6$. This causes the voltage across $D_5$ and $D_6$ to decrease and increase, respectively, leading to commutation between the two diodes. $V_{D5}$ becomes equal to $V_{C_{S_3}}$ and concurrently $V_{D6}$ equals $V_{C_{S_4}}$. At this point, $I_{sec2}$ equals to zero and ZCS is achieved for $D_6$ during turned off.

• Mode 7 (${\mathit{t}}_{\mathbf{6}}-{\mathit{t}}_{\mathbf{7}}$). During this interval, $I_{pri2}$ remains equal to $I_{Lm2}$ and $I_{sec2}$ is zero. Therefore, the voltage-doubler diodes are OFF, and no energy transfer occurs to the load. The transformers’ primary sides, $T_1$ and $T_2$, are circulating with tiny magnetizing currents, $I_{Lm1}$ and $I_{Lm2}$, respectively. The currents through $S_3$ and $S_2$ are unequal; while the current flowing through $S_2$ is the total of the magnetizing currents of $T_1$ and $T_2$, the magnetizing current at primary side of $T_1$ flows through $S_3$.

• Mode 8 (${\mathit{t}}_{\mathbf{7}}-{\mathit{t}}_{\mathbf{8}}$). This mode initiates when $S_2$ turns off. The $I_{Lm1}$ and $I_{Lm2}$ pass through $S_2$ and $S_4$’s junction capacitors. The junction capacitor of $S_2$ charges to Vin, while that of $S_4$ is discharged. These magnetizing currents help achieve ZVS for the lagging switch $S_4$. As a result, $V_{p2}$ increases to $V_{in}$, while $V_{p1}$ decreases to $-V_{in}$. $I_{pri1}$ falls below $I_{Lm1}$ as a result of a negative voltage being applied across $T_1$’s leakage inductor. $I_{sec1}$ thus passes directly through the junction capacitors of $D_2$ and $D_4$ and in reverse through those of $D_1$ and $D_3$. As a result, the voltage across $D_1$ and $D_3$ increases, while those across $D_2$ and $D_4$ decreases. When the voltages across $D_2$ and $D_4$ reach zero, they turn on, and $I_{sec1}$ passes through these diodes. At the moment $D_1$ and $D_3$ are OFF. Meanwhile, $L_{lk2}$ receives a positive voltage, which causes the slope of the primary current of $T_2$ to becomes positive. Consequently, the absolute value of $I_{pri2}$ becomes lower than $I_{Lm2}$. As a result, $I_{sec2}$ flows through the junction capacitors of $D_5$ and $D_6$, discharging and charging them, respectively. Finally, the voltage across $D_5$ drops to zero, causing $D_5$ to turn ON, while $D_6$ remains OFF.

2.2. Analysis of the Proposed Converter

2.2.1. DC Conversion Ratio

The proposed converter consists of two main parts. To obtain the equation for voltage gain, the FB and HB sections must be analyzed separately. The output voltages of FB and HB parts are denoted as $V_1$ and $V_2$, respectively. The resulting voltage is subsequently derived from the total of $V_1$ and $V_2$. For the purpose of simplifying the analysis, dead times are neglected, since their duration is considered insignificant in relation to the switching period. The equations of $I_{pri1}$ and $I_{Lm1}$ are obtained and expressed as Equations (1) and (2), respectively. In mode 1, $D_1$ and $D_3$ are ON. The secondary side current can be described as Equation (10).

$$I_{sec1}\left(t\right)={\displaystyle \frac{1}{Z_{0_1}}}[n_1{V}_{in}-V_{C_{s_2}}\left(t_0\right)]sin\left({\omega }_{r}1(t-t_0)\right)$$

(10)

During each half-switching period, the average value of $I_{sec1}$ is split into two equal segments: one flowing through $D_1$ and $D_3$, and the other through $D_2$ and $D_4$. The average value is then expressed as Equation (11).

$$\overline{I_{sec1}}={\displaystyle \frac{2f_s}{{\omega }_{r1}·Z_{0_1}}}[n_1{V}_{in}-V_{C_{s_2}}\left(t_0\right)]·[1-cos({\displaystyle \frac{2\pi D{f}_{r1}}{f_s}})]$$

(11)

D denotes the power delivery duration during each half of the switching cycle. Assuming the capacitors on the secondary side function as constant voltage sources, these values are derived:

$$\overline{V_{C_{o_1}}}=2\overline{V_{C_{s_2}}}={\displaystyle \frac{V_1}{2}}$$

(12)

$$\overline{V_{C_{o_1}}}+\overline{V_{C_{s_2}}}+\overline{V_{C_{s_1}}}=V_1$$

(13)

Because the circuit operates in steady state, the mean current flowing through $C_{o_1}$ or $C_{o_2}$ is equal to the output current. However, the currents of $C_{s_1}$ and $C_{s_2}$ differs from those of $C_{o_1}$ or $C_{o_2}$. For instance, in each half-switching period, the current flowing through $C_{s_1}$ equals the total of the charging current from $C_{o_1}$ and the output current. Consequently, the mean current of $C_{s_1}$ (similarly $C_{s_2}$) is twice the output current.

$$\mathrm{\Delta }{V}_{C_{s_2}}={\displaystyle \frac{1}{C_{s_2}}}\int I_{C_{s_2}\left(t\right)}dt={\displaystyle \frac{V_1}{R_o{C}_{s_2}{f}_s}}$$

(14)

Therefore $V_{C_{s_2}}\left(t_0\right)$ can be obtained:

$$V_{C_{s_2}\left(t_0\right)}=\overline{V_{C_{s_2}\left(t\right)}}-{\displaystyle \frac{\mathrm{\Delta }{V}_{C_{s_2}}}{2}}={\displaystyle \frac{V_1}{4}}-{\displaystyle \frac{V_1}{2R_0{C}_{s_2}{f}_s}}$$

(15)

From Equations (11) and (15), $V_1$ can be represented as Equations (16) and (17). To simplify the aforementioned relationships, the ratio of the resonance frequency of Transformer $T_1$ ($f_{r1}$) to $f_s$ has been substituted with Equation (18).

$$V_1={\displaystyle \frac{1}{4}}·R_o·\overline{I_{sec1}}$$

(16)

$${\displaystyle \frac{V_1}{V_{in}}}={\displaystyle \frac{n_1}{\frac{1}{4}-\frac{2\pi Z_{0_1}F}{R_o}·[1-\frac{2}{1-cos\left(2\pi DF\right)}]}}$$

(17)

$$F={\displaystyle \frac{f_{r1}}{f_s}}$$

(18)

The primary side of the transformer $T_2$ and the $C_P$ are subjected to a square-wave voltage. Since the HB section operates near the resonant frequency, it is appropriate to approximate the voltage waveform using the fundamental harmonic of the square wave, neglecting higher-order harmonics. The voltage-doubler rectifier on the secondary of $T_2$ is implemented accordingly. As previously noted, the half-bridge operates at or close to the resonant frequency. From [31], in this operating mode, the parameter $M_g$ in Equation (19) is approximately unity across the entire load range. Using these assumptions, Equation (24) expresses the voltage gain of the HB section.

$$M_g=\left|{\displaystyle \frac{L_n{f}_{n2}^2}{[(L_n+1)f_{n2}^2-1]+j\left[(f_{n2}^2-1)f_{n2}{Q}_e{L}_n\right]}}\right|$$

(19)

where

$$L_n={\displaystyle \frac{L_{m2}}{L_{r2}}}$$

(20)

$$f_{n2}={\displaystyle \frac{f_s}{f_{r2}}}$$

(21)

$$R_e={\displaystyle \frac{8}{{\pi }^2}}·R_o$$

(22)

$$Q_e={\displaystyle \frac{1}{R_e}}·\sqrt{{\displaystyle \frac{L_{r2}}{C_{r2}}}}$$

(23)

$${\displaystyle \frac{V_2}{V_{in}}}=n_2·M_g\simeq n_2$$

(24)

By combining Equations (17) and (24), Equation (25) is obtained, which expresses the voltage gain of the proposed boosting converter. To assess the voltage efficiency of the proposed converter under varying load, Figure 5 is presented. The figure shows the load variation ranging from 20% to 100% of the nominal load. As observed, the duty cycle on the horizontal axis varies from 0 to 0.5, with the maximum voltage gain occurring at 0.5 and the minimum at 0.

$${\displaystyle \frac{V_{out}}{V_{in}}}={\displaystyle \frac{V_1}{V_{in}}}+{\displaystyle \frac{V_2}{V_{in}}}\simeq {\displaystyle \frac{n_1}{\frac{1}{4}-\frac{2\pi Z_{0_1}F}{R_o}·[1-\frac{2}{1-cos\left(2\pi DF\right)}]}}+n_2$$

(25)

2.2.2. Extended ZVS Range

Due to the energy stored in the large output filter inductor of a conventional PSFB converter, ZVS of the leading-leg switches is readily achievable. However, the lagging-leg switches exhibit a narrow ZVS range, as their operation depends on the energy stored in the leakage inductor. This energy is often insufficient at light loads to fully charge and discharge the junction capacitors of the lagging switches. To overcome this limitation in the proposed converter, when $S_1$ turns off, $I_{pri1}$ exceeds $I_{Lm1}$, as shown in Figure 6. Consequently, the energy stored in the leakage inductor at $t_2$ must exceed the energy stored in the output capacitors of $S_1$ and $S_3$ to realize ZVS for the leading-leg switches. Although this is often insufficient by itself, the energy stored in the magnetizing inductor at $t_3$ additionally contributes to the ZVS of these switches. Therefore, Equation (26) must be established to satisfy ZVS conditions for $S_1$ and $S_3$:

$${\displaystyle \frac{1}{2}}·L_{lk1}·I_{{pri1|}_{t=t_2}}^2+{\displaystyle \frac{1}{2}}·L_{m1}·I_{{Lm1|}_{t=t_3}}^2\ge C_{oss}·V_{in}^2$$

(26)

During mode 2 ($t_1$$t_2$, as shown in Figure 6), a voltage equal to $-V_{C_{S2}}/n_1$ is applied to $L_{lk1}$. Consequently, the linear current decay on the primary side of $T_1$ can be determined. Applying Equations (27) and (28), the numerical methods can be employed to determine the required dead time and the magnetizing inductance necessary to guarantee ZVS of the leading switches. Equation (27) is derived under the condition that, concurrently with achieving ZVS, the current is decreasing. Therefore, the average current is taken approximately, and $t_2$ plus the required duration for forming ZVS is used as the dead time. The current decreases nearly linearly, so this averaged current facilitates the discharge of the switch capacitors and hence enables ZVS.

$$I_{ZVS-lead}={\displaystyle \frac{I_{{pri1|}_{t=t_2}}+I_{{pri1|}_{t=t_2+t_{dead-lead}}}}{2}}$$

(27)

$$t_{dead-lead}=C_{oss}·{\displaystyle \frac{2V_{in}}{I_{ZVS-lead}}}$$

(28)

In the proposed topology, the magnetizing currents $I_{Lm1}$ and $I_{Lm2}$ provide the necessary conditions to achieve ZVS of the lagging-leg switches. Since $I_{Lm1}$ varies with changes in the duty cycle, and the energy stored in $L_{m1}$ decreases at light loads, ZVS may be lost if this is managed correctly. However, by designing the HB section to operate at an optimal frequency, it can actively contribute to the ZVS process. This ensures that, during transition intervals, the energy stored in $I_{Lm2}$ remains constant across all load conditions.

To harness this advantage, the resonant frequency $f_{r2}$ should be tuned to be close to $f_s$, or slightly higher. This operating mode, in addition to ZVS of the lagging-leg switches, ensures ZCS for the voltage-doubler diodes over the entire load range. According to Figure 5, for ZVS of $S_2$ and $S_4$, Equation (29) should be established. Equation (29) analyzes the ZVS condition for the leg from an energy perspective, ensuring that the inductor energy exceeds the switch-capacitor energy to guarantee ZVS.

$${\displaystyle \frac{1}{2}}·(L_{m1}+L_{lk1})·I_{{Lm1|}_{t=t_9}}^2+{\displaystyle \frac{1}{2}}·(L_{m2}+L_{lk2})·I_{{Lm2|}_{t=t_9}}^2\ge C_{oss}·V_{in}^2$$

(29)

During the transition interval, the magnetizing currents flow through the output capacitors of $S_2$ and $S_4$. Therefore, Equation (30) represents the dead time between the lagging-leg switches. This Equation presents the fundamental capacitor relationship for the leg; at these instants, the primary current of the transformers equals their magnetizing current, and this current serves to discharge the switch capacitors, enabling ZVS.

$$t_{dead-lag}=C_{oss}·{\displaystyle \frac{2V_{in}}{I_{Lm1}+I_{Lm2}}}$$

(30)

2.2.3. Efficient Energy Transfer Comparison

The proposed converter consists of two sources of energy. The first source is the PSFB topology, which delivers energy to the output during the active phases, i.e., when $S_1$ and $S_2$ or $S_3$ and $S_4$ are ON. The second source is the half-bridge converter, which transfers energy during the active and freewheeling phases of PSFB except the orange region indicated in Figure 7c. The interval during which no energy transfer occurs to the output in the proposed PSFB converter is illustrated in Figure 7. The comparative performance of this converter with respect to circulating currents is analyzed in comparison to the conventional PSFB and HB topologies. From this perspective, the proposed design outperforms existing PSFB converters in terms of energy transfer efficiency.

The circulating currents and conduction losses are significantly minimized in the proposed topology. At the start of the freewheeling phases, $I_{pri1}$ drops rapidly to the magnetizing current. In contrast, in a traditional PSFB, the primary current during freewheeling equals the reflected load current, resulting in higher circulating currents and associated losses. The half-bridge section of the proposed converter typically operates near or at the resonant frequency. Consequently, the circulating current is approximately $I_{Lm2}$, and due to the short duration, the energy circulated is minimal. Therefore, both the FB and HB parts of the proposed converter operate with reduced circulating losses, as visually summarized in Figure 7.

2.2.4. ZCS Condition

Since the half-bridge operates below the resonant region, the primary current of $T_2$ reaches the magnetizing current value before the end of the drive pulse duration. This causes the voltage-doubler diodes to turn off with ZCS. To tune the resonant condition of the HB section closely above the switching frequency, the voltage-doubler capacitors should be chosen slightly smaller than the value obtained from the following relation, ensuring the resonant frequency exceeds $f_s$:

$$C_{s_{3,4}}<{\displaystyle \frac{1}{8{\pi }^2{n}_2^2{L}_{lk2}{f}_s^2}}$$

(31)

As illustrated in Figure 6, to ensure ZVS of the leading-leg switches $S_1$ and $S_3$ in the broad range of load variations, $f_{r1}$ is chosen to be less than $f_s$. This selection also reduces switching losses and decreases the current stress on the output diodes $D_1$∼$D_4$ during the transitions, compared to the triangular waveform generated when $f_{r1}$ is significantly slower than $f_s$. Considering these conditions, the resonant frequency is selected to minimize the peak value of $I_D$, which leads to a decrease in the conduction losses. This choice results in quasi-sinusoidal waveforms for the diode currents $I_{D_1}$∼$I_{D_4}$. Figure 8 indicates the peak of $I_{D_1}$∼$I_{D_4}$ according to the voltage-quadrupler capacitance ($C_{S_1}$ or $C_{S_2}$), under the parameters: $L_{lk1}$ = 19 μH, $R_O$ = 8 kΩ and $f_s$ = 71 kHz. The peak value of $I_{D_1}$∼$I_{D_4}$ is optimized when $C_{S_1}$ or $C_{S_2}$ exists around 28 nF. From Equations (10) and (15), the maximum diode current $I_D$ is calculated by Equation (32).

$$I_{D_1\sim D_4,max}={\displaystyle \frac{1}{2Z_{0_1}}}[n_1{V}_{in}-{\displaystyle \frac{V_1}{4}}+{\displaystyle \frac{V_1}{2R_o{C}_{S_2}{f}_s}}]$$

(32)

3. Design Considerations

Specifications of the proposed converter are as follows: the transferred power is 500 W, the input voltage $V_{in}$ = 150 V, and an output voltage $V_{out}$ = 2 kV.

3.1. Selection of Main Switches

The RMS currents through the lead and lag switches should be computed separately and based on the underlying mathematical relations. These currents can be expressed as follows:

$$I_{Lead,rms}=\sqrt{f_s[{\int }_0^{D{T}_s}{I}_{pri1}^{2}dt+{\int }_{D{T}_s}^{T_s-t_{dead}}{I}_{Lm1,pk}^{2}dt]}$$

(33)

$$I_{Lag,rms}=\sqrt{f_s·K}$$

(34)

where ${\int }_0^{D{T}_s}{I}_{pri1}^{2}dt$ and K are calculated as outlined in Equations (35) and (36). The parameters used in the previous relations are explicitly presented in Equations (37)∼(43).

$$\begin{array}{cc}\hfill & {\int }_0^{D{T}_s}{I}_{pri1}^{2}dt={\displaystyle \frac{A_1^2}{2}}·(D{T}_s-{\displaystyle \frac{sin\left(2{\omega }_{r1}D{T}_s\right)}{2{\omega }_{r1}}})+D{T}_s{I}_{L_{m1pk}}^2+{\displaystyle \frac{B_1^{2}D{T}_s^3}{3}}+{\displaystyle \frac{2A_1{I}_{Lm1,pk}}{{\omega }_{r1}}}·(1-cos\left({\omega }_{r1}D{T}_s\right))\hfill \\ & +B_{1}D{T}_s^2{I}_{Lm1,pk}+2A_1{B}_1({\displaystyle \frac{sin\left({\omega }_{r1}D{T}_s\right)}{{\omega }_{r1}^2}}-{\displaystyle \frac{D{T}_s·cos\left({\omega }_{r1}D{T}_s\right)}{{\omega }_{r1}}})\hfill \end{array}$$

(35)

$$\begin{array}{cc}\hfill & K={\displaystyle \frac{2A_1{A}_2}{{\omega }_{r1}-{\omega }_{r2}}}·[cos\left({\omega }_{r1}D{T}_s\right)·sin\left({\omega }_{r2}D{T}_s\right)]-{\displaystyle \frac{2A_1(I_{Lm2,pk}+B_{2}D{T}_s)}{{\omega }_{r1}}}·cos\left({\omega }_{r1}D{T}_s\right)+{\displaystyle \frac{2A_1{B}_2}{{\omega }_{r1}^2}}·sin\left({\omega }_{r1}D{T}_s\right)\hfill \\ & -{\displaystyle \frac{2A_2{B}_{1}D{T}_s}{{\omega }_{r2}}}·cos\left({\omega }_{r2}D{T}_s\right)+{\displaystyle \frac{2A_2{B}_1}{{\omega }_{r2}^2}}·sin\left({\omega }_{r2}D{T}_s\right)-{\displaystyle \frac{2A_2{I}_{Lm1,pk}}{{\omega }_{r2}}}·(cos\left(0.46{\omega }_{r2}{T}_s\right)-1)+{\displaystyle \frac{2A_1{I}_{Lm1,pk}}{{\omega }_{r1}}}\hfill \\ & +2I_{Lm1,pk}{I}_{Lm2,pk}D{T}_s+(B_2{I}_{Lm1,pk}+B_1{I}_{Lm1,pk})·D^2·T_s^2+[I_{Lm1,pk}^2+2I_{Lm1,pk}{I}_{Lm2,pk}](0.46-D)T_s\hfill \end{array}$$

(36)

$$I_{Lm1,pk}={\displaystyle \frac{V_{1}D{T}_s}{8n_1{L}_{m1}}}$$

(37)

$$I_{Lm2-pk}={\displaystyle \frac{V_2{T}_s}{8n_2{L}_{m2}}}$$

(38)

$$A_1={\displaystyle \frac{n_1}{Z_{0_1}}}·[n_1{V}_{in}-V_{C_{S2}}\left(t_0\right)]$$

(39)

$$A_2={\displaystyle \frac{n_2}{Z_{0_2}}}·[{\displaystyle \frac{n_2{V}_{in}}{2}}-V_{C_{S3}}\left(t_0\right)]$$

(40)

$$B_1={\displaystyle \frac{V_1}{4n_1{L}_{m1}}}$$

(41)

$$B_2={\displaystyle \frac{V_2}{2n_2{L}_{m2}}}$$

(42)

$$V_{C_{S3}}\left(t_0\right)={\displaystyle \frac{V_2-\mathrm{\Delta }{V}_{C_{S3}}}{2}}={\displaystyle \frac{V_2}{2}}-{\displaystyle \frac{I_o}{4C_{S_3}{f}_s}}$$

(43)

3.2. Selection of Resonant Frequencies

To decrease the current stress and reverse recovery loss of the rectifier diodes, the resonant frequency of the HB part ($f_{r2}$) should be close to, and slightly higher than $f_s$. Since the leakage inductance cannot be adjusted without adding an extra inductor, the voltage-doubler capacitors must be selected using Equation (31). The resonant frequency of the FB part ($f_{r1}$) should be chosen to ensure wide-range operation of ZVS in the leading-leg switches and to minimize the peak current of the voltage-quadrupler diodes. Consequently, $C_{S1}$ and $C_{S2}$ should be selected according to Equation (32) and based on Figure 8. As noted earlier, $f_{r1}$ is lower than $f_s$.

3.3. Design of the Magnetizing Inductors and Transformers

As the fundamental factors, the stored magnetic energy in the inductors and the dead-time influence ZVS in the main switches. Figure 9 and Figure 10 illustrate, respectively, the energy stored in the magnetizing inductance and in the leakage inductance of $T_1$, and the required dead time for ZVS of the leading-leg switches. Both figures are plotted against variations in the magnetizing inductance $L_{m1}$ and load condition. The magnetizing inductance $L_{m1}$ = 1.2 mH and the dead time $t_{dea{d}_{lead}}$ = 130 ns are selected to ensure the occurrence of ZVS for the leading-leg switches. Figure 11 and Figure 12 are related to the ZVS performance of the lagging-leg switches. By adjusting the magnetizing inductance of $T_2$ to 1 mH ($L_{m2}$ = 1 mH), the required dead time $t_{dea{d}_{lag}}$ = 400 ns is chosen to ensure ZVS at the 5% load as well. The secondary-to-primary ratio of the transformers can be calculated using Equation (25), assuming $n_1$ and $n_2$ are equal.

A primary consideration is the transformer’s leakage inductance, which is inherently difficult to control precisely. The design process begins by setting the magnetizing inductance of the transformer, followed by measurement of the interleaved leakage inductance after fabrication. The targeting of the mid-point resonant behavior then aims to realize ZCS in the half-bridge section using the leakage inductor as the energy-storage element. Choosing a minimal capacitance would necessitate a higher switching frequency, which conflicts with the goals of high-power operation and can exacerbate switching losses and electromagnetic interference. Conversely, selecting a tiny capacitor would not yield the desired performance due to the influence of parasitic capacitances and the distributed effects of PCB capacitances.

If the voltage-doubler capacitors (or the equivalent capacitor in the doubler network) are increased to around 100 nF or more, the switching frequency must be reduced to maintain ZCS, which would degrade the overall power density—unfavorable for high-power applications. Therefore, not every capacitor value is suitable to achieve ZCS. In practice, capacitor values tend to be in the nanofarad range, typically around 1 to 30 nF. A balanced operating frequency around 70 kHz was selected, which led to the identification of a capacitor value of 12 nF conducive to achieving ZCS. For the quadrupler configuration, the objective was to minimize the peak current through the diodes. To achieve this objective, Figure 8 illustrates the optimized capacitor value for the voltage-quadrupler.

4. Experimental Results

To validate the effectiveness and performance of the suggested converter, a 500-W prototype is built and tested according to Figure 13. The specifications of the converter are input voltage $V_{in}$ = 150 V, output voltage $V_{out}$ = 2 kV and switching frequency $f_s$ = 71 kHz. The values and parameters of the equipment employed in the converter are listed in

Table 1. Component list of the laboratory-tested prototype.

	Parameters	Value/Description
Input voltage	$V_{in}$	150 V
Output voltage	$V_{out}$	2 kV
Output power	$P_{out}$	500 W
Switches	$S_1$∼$S_4$	IRFP460LC
Output diodes	$D_1$∼$D_6$	UF5408
Turn ratio (1:n1), (1:n2)	$n_1$, $n_2$	$N_{P_1}$ = 19, $N_{S_1}$ = 57; $N_{P_2}$ = 33, $N_{S_2}$ = 100; $n_1$ = $n_2$ = 3
Magnetizing inductance	$L_{m1}$, $L_{m2}$	$L_{m1}$ = 1.2 mH $L_{m2}$ = 1 mH
Leakage inductance	$L_{lk1}$, $L_{lk2}$	$L_{lk1}$ = 19 μH $L_{lk2}$ = 22 μH
Capacitors of secondary side	$C_{S_1}$, $C_{S_2}$	28 nF
	$C_{S_3}$, $C_{S_4}$	12 nF
	$C_P$	6.8 μF
	$C_{O_1}$, $C_{O_2}$	1.1 μF
	$C_O$	2.75 μF
Switching frequency	$f_s$	71 kHz

. For simplicity of the analysis, the secondary turns of both transformers are taken equal to the primary turns, i.e., a turns ratio of 3 ($n_1$ = $n_2$ = 3). Accordingly, Figure 14 shows the specifications of the primary currents of Transformers 1 and 2 ($I_{pri1}$ and $I_{pri2}$) and the currents through switches 2 and 3 under full load conditions. Figure 15a,b illustrate the ZVS operation of the main switches at full load. ZVS at 5% load is achieved by leveraging the inductive energy and adjusting the dead time accordingly. Figure 15c,d display ZVS of the main switches at 5% load, demonstrating that the converter maintains ZVS from no load up to full load. Furthermore, as shown in Figure 16, the experimental results verify the ZCS of the voltage-doubler diodes. As a consequence of quasi-sinusoidal operation, the turn-off current stress on the voltage-quadrupler diodes is significantly reduced compared to their triangular-waveform counterpart.

Losses and Efficiency Analysis

The measured efficiency of the 500-W prototype, in comparison to a conventional PSFB converter, is illustrated in Figure 17. The peak efficiency attains approximately 94.5% at 75% load. Notably, the efficiency gains are even more pronounced at light loads below 25%, primarily thanks to the ZVS operation of lagging-leg switches. The absence of an output inductor also contributes to efficiency improvement. To evaluate the performance of the converter in both soft-switched and hard-switched operation, the impact of soft switching on converter efficiency is presented. The proposed converter demonstrates near-constant efficiency across a wide range of load variations, even under severe loading conditions. This characteristic implies that the device maintains robust performance without a priori limitations across diverse load ranges.

Figure 18 provides an assessment of losses across various devices at full load. As previously mentioned, the elevated RMS currents in the lagging-leg switches contribute to increased losses compared to the leading leg. Additionally, the paper presents a comparative assessment of losses, detailing the performance of the converter in both soft-switched and non-soft-switched modes. Losses associated with each converter component are quantified for the two operating states, highlighting the benefits and trade-offs of implementing soft switching. For comparative analysis,

Table 2. Detailed comparison of the proposed converter with other structures.

		Conventional PSFB	[32]	[33]	Proposed Converter
Simplified Voltage Gain		${\mathit{n}}_{\mathbf{1}}$	$\mathbf{2}{\mathit{n}}_{\mathbf{1}}$	$\mathbf{5}{\mathit{n}}_{\mathbf{1}}$	$\mathbf{4}{\mathit{n}}_{\mathbf{1}}$+${\mathit{n}}_{\mathbf{2}}$
Switches	Current stress	High circulating current	moderate circulating current	low circulating current	Low circulating current
	Switching loss	ZVS failure of the lagging leg	high at $f_r$ < $f_s$	high at $f_r$ < $f_s$	Wide ZVS range
Diodes	Voltage stress	$V_{out}$	$V_{out}$	0.2$V_{out}$∼0.5$V_{out}$	0.2$V_{out}$∼0.4$V_{out}$
	Switching loss	High (hard switching)	ZCS only at $f_r$ < $f_s$	ZCS only at $f_r$ < $f_s$	Reduced loss of $D_1$∼$D_4$ and ZCS of $D_5$ and $D_6$
Component Count	L	1	0	0	0
	C	1	1	6	7
	D	4	8	6	6
	S	4	4	6	4
	T	1	2	1	2
	Total	11	15	19	19

outlines the specifications of the proposed converter in relation to the traditional PSFB converter and other similar structures. Under identical voltage gain conditions, the switches in the proposed converter endure significantly reduced stress due to diminished circulating currents, thereby resulting in a much wider ZVS range. Additionally, the diodes demonstrate lower losses and, in certain instances, operate under ZCS conditions. Moreover, the voltage gain requirement for the transformers in the proposed converter is one fifth that of the PSFB converter.

5. Conclusions

This study presents an innovative voltage-fed converter that has been meticulously optimized for high efficiency and considerable voltage gain. The experimental and analytical validations confirm that the proposed topology surpasses the conventional PSFB converter in several critical aspects. Key advantages include addressing large circulating currents, expanding the ZVS range for lagging-leg switches, stable efficiency under wide load variations, and mitigating issues related to hard switching in rectifier diodes. Unlike traditional PSFB configurations, where the output filter inductor experiences a voltage stress equal to the output voltage—necessitating large inductors in high-voltage applications to ensure insulation—the proposed converter eliminates this requirement. Furthermore, its elevated voltage gain provides substantial advantages in high step-up applications. The voltage stress on the secondary windings of both transformers is considerably lower than the output voltage, which further mitigates the insulation challenges typically associated with winding design. By integrating theoretical analysis with experimental findings, these benefits are distinctly substantiated, rendering the proposed converter highly appropriate for high step-up, high-voltage applications such as electron beam welding.