High-Efficiency Multistage Charge Pump Rectifiers Design

Abstract

This paper presents an advanced radio frequency (RF)–direct current (DC) power conversion architecture based on a multistage Cockcroft–Walton topology. The proposed design achieves an enhanced voltage conversion ratio while maintaining superior RF-DC conversion efficiency under low input power conditions. To address the inherent limitations of cascading Cockcroft–Walton topologies with class-F load networks, a novel ground plane isolation technique was developed, which utilizes the reverse-side metallization of the circuit board. A 5.8 GHz two-stage Cockcroft–Walton voltage multiplier rectifier was fabricated and characterized. Measurement results demonstrate that the circuit achieves a maximum output voltage of 7.4 V and a peak conversion efficiency of 70.5% with an input power of only 30 mW, while maintaining stable performance across varying load conditions. A comparison with a two-stage Dickson rectifier reveals that the Cockcroft–Walton rectifier exhibits superior output voltage and conversion efficiency. The proposed architecture delivers significant improvements in power conversion efficiency and voltage multiplication capability compared to conventional designs, establishing a new benchmark for low-power wireless energy harvesting applications.

1. Introduction

The rapid advancement of wireless communication technologies and Internet of Things (IoT) applications has driven a growing demand for microwave energy harvesting solutions [1]. Traditional battery-powered systems are constrained by limited energy storage, high replacement costs, and environmental concerns. Microwave wireless power transmission (MWPT) technology overcomes these limitations by providing a sustainable energy supply for low-power devices [2,3]. Figure 1 presents a system block diagram of microwave wireless energy transfer employed to power nodes in an IoT system.

Microwave rectifiers are critical components in wireless power transmission (WPT) systems, as they convert RF signals into usable DC power [4,5]. Their conversion efficiency directly determines the overall performance of the system. Current applications face two key challenges: first, conversion efficiency remains low under low input power conditions; second, many IoT modules require higher supply voltages (e.g., NB-IoT modules (12 V), LoRa modules (12 V), and low-power linear regulators (2–18 V)). Conventional voltage multiplier configurations, including Dickson and Cockcroft–Walton rectifiers, have been developed to meet these voltage requirements [6,7,8,9,10]. However, conventional rectifiers—such as single-shunt and single-series structures—only achieve 30–40% conversion efficiency in the microwave frequency range. Furthermore, their output voltage is relatively low (typically below 5 V under low input power), which severely restricts their practical application [11].

To improve efficiency, a class-F load has been integrated into rectifier designs. The class-F load structure combines λ/4 microstrip lines with open stubs, forming a ground-coupled equivalent capacitance to enhance rectification efficiency [12,13,14,15,16]. Figure 2a illustrates a single-stage voltage-doubling rectifier circuit with a class-F load. Derived from class-F power amplifier harmonic tuning networks, this architecture exhibits distinct impedance characteristics: zero impedance at even harmonics and infinite impedance at odd harmonics. This optimized impedance profile minimizes the overlap between diode current and voltage waveforms, while enabling energy recycling through the reflection of higher-order harmonics—thereby improving circuit efficiency [17]. Experimental results show that charge pump circuits based on class-F load achieve significantly higher rectification efficiency than traditional designs [18,19].

To boost output voltage, a charge pump topology was integrated into microwave rectifiers, enabling a 5 V output under low input power conditions [20,21,22]. Subsequently, multistage charge pump rectifiers—capable of generating higher output voltages—have attracted increasing attention [20,23]; common multistage topologies include Dickson and Cockcroft–Walton rectifiers. Due to limitations in cascading performance, the structurally simple Dickson and class-F Dickson rectifiers have become focal points of research [24,25,26,27]. However, research on class-F multistage Cockcroft–Walton rectifiers remains limited, primarily because class-F loads are incompatible with the cascading mechanism of Cockcroft–Walton rectifiers.

To address the cascading challenges of multistage Cockcroft–Walton rectifiers incorporating class-F load structures, this study proposes an inter-stage DC isolation architecture. This approach achieves high rectified output voltage under low input power while preserving conversion efficiency. The proposed solution can be directly integrated into low-power-density energy-receiving systems, eliminating the need for additional DC conversion stages and simplifying the overall circuit structure. To validate the proposed topology, a 5.8 GHz DC-isolated two-stage Cockcroft–Walton rectifier was designed and fabricated. Experimental results demonstrate a maximum conversion efficiency of 70.5% and an output voltage of 7.4 V with an input power of only 30 mW, confirming both high efficiency and elevated output voltage under low input power conditions. For comparison, a two-stage Dickson charge pump rectifier with a class-F load achieved a conversion efficiency of 69% and an output voltage of 5.45 V under the same 30 mW input power.

2. Materials and Methods

2.1. Multi-Stage Charge Pump Rectifiers Theoretical Analysis

In rectifiers, conversion efficiency is determined by the difference between the theoretical efficiency of the circuit topology and its associated losses. Diode loss (L_d) is typically the dominant loss component in rectifier circuits. Thus, the rectifier efficiency (η) can be expressed as follows:

$$\begin{array}{c}\eta =\left(1-L_d\right)\times 100\%\end{array}$$

(1)

where the theoretical efficiency of all aforementioned rectifier topologies is 100%. For single-stage voltage doubler rectifiers, the output voltage equals twice the maximum input AC voltage. The voltage relationship within the circuit is therefore as follows:

$$\begin{array}{c}Max\left(v_{in\left(ac\right)}\right)=V_{d\left(dc\right)}={\displaystyle \frac{V_o}{2}}\end{array}$$

(2)

According to diode operating principles, the maximum diode current (I_max) is given by Equation (3), where is the diode saturation current, e is the electron charge, K is the Boltzmann constant, and T is the temperature in Kelvin:

$$\begin{array}{c}{I}_{max}=I_s\left(\mathit{exp}\left({\displaystyle \frac{e}{KT}}\times {\displaystyle \frac{V_o}{2}}\right)-1\right)\end{array}$$

(3)

The frequency characteristics of the charge pump rectifier depend on the diode and the intrinsic frequency response of the circuit topology. The cutoff frequency of the rectifier is expressed as follows:

$$\begin{array}{c}\left\{\begin{array}{c}{f}_{diode-cutoff}={\displaystyle \frac{1}{2\pi R_S{C}_j}}\\ f_{rectifier-cutoff}={\displaystyle \frac{1}{2\pi R_L{C}_0}}\end{array}\right.\end{array}$$

(4)

where R_s is the diode series resistance, C_j is the diode junction capacitor, R_L is the rectifier load, and C₀ is the output boost capacitor. Diode power loss (P_D) is calculated using Equation (5), where v_D(t) and i_D(t) are the time-varying diode voltage and current, respectively, and T is the signal period:

$$\begin{array}{c}{P}_D=\frac{1}{T}{\int }_0^T{v}_D\left(t\right)i_D\left(t\right)dt\end{array}$$

(5)

Owing to the impedance characteristics of the class-F load—zero impedance at even harmonics and infinite impedance at odd harmonics—the impedance (Z(f)) is defined as follows:

$$\begin{array}{c}f\left(x\right)=\left\{\begin{array}{cc}\hfill Z_D,& f=f_0\hfill \\ \hfill 0,& f=2n{f}_{0}n=1,2,3,\cdots \hfill \\ \hfill \infty ,& f=\left(2n+1\right)f_0\hfill \end{array}\right.\end{array}$$

(6)

For a single-stage voltage doubler rectifier with a class-F load, the time-varying diode current and voltage are expressed by Equations (6) and (7), respectively:

$$\begin{array}{c}{I}_d\left(t\right)={\displaystyle \frac{I_{max}}{\pi }}+{\displaystyle \frac{I_{max}}{2}}\mathit{cos}\omega t+{\displaystyle \frac{2I_{max}}{2\pi }}\mathit{cos}\left(2\omega t\right)+\cdots +{\displaystyle \frac{2I_{max}}{(1-(2n{)}^2)}}\mathit{cos}\left({\displaystyle \frac{n\pi }{2}}\omega t\right)\end{array}$$

(7)

$$\begin{array}{c}{V}_d\left(t\right)=V_{dc}-v_1\mathit{cos}\left( \omega t\right)+v_3\mathit{cos}\left( 3\omega t\right)+\cdots +v_{2n+1}\mathit{cos}\left[ \left(2n+1\right)\omega t\right]\end{array}$$

(8)

For an n-stage rectifier under identical matching conditions and input power, the output voltage of the n-stage charge pump rectifier is n times that of a single parallel rectifier. However, the voltage across each diode remains the same as in a single-diode parallel circuit, while the current through each diode is reduced to 1/n. The diode power loss for the n-stage rectifier is thus as follows:

$$\begin{array}{c}{P}_D={\displaystyle \frac{1}{T}}{\int }_0^{T}n{V}_D\left(t\right)-{\displaystyle \frac{1}{n}}{I}_D\left(t\right)dt\hfill \\ ={\displaystyle \frac{1}{T}}{\int }_0^T(n{V}_{\mathit{dc}}-n{v}_1\mathit{cos}(\omega t)+\cdots )({\displaystyle \frac{I_{\mathit{max}}}{n\pi }}+{\displaystyle \frac{2I_{\mathit{max}}}{2n}}\mathit{cos}(\omega t)+\cdots )\hfill \end{array}$$

(9)

Consequently, although the number of diodes doubles in a single-stage voltage doubler circuit, the actual diode power loss remains equivalent to that in single-diode parallel/series circuits. Rectifier circuits incorporating class-F load structures achieve identical conversion efficiency to single-diode parallel/series or single-stage voltage doubler circuits while providing higher output voltage.

2.2. Multi-Stage Charge Pump Rectifiers Design Methods

Due to the inherent voltage boost limitations of single-stage charge pumps, multistage configurations are necessary for applications requiring higher output voltages. In multistage Dickson rectifiers, combinations of microstrip transmission lines and open stubs can directly replace C_o, forming a parasitic capacitance with the ground (Figure 3a). In contrast, C_o in multistage Cockcroft–Walton rectifiers connects between the outputs of adjacent stages (Figure 3b). Direct substitution of C_o with a class-F load structure causes output voltage equalization between adjacent stages (due to transmission line characteristics), which negates the voltage multiplication effect. Thus, class-F load structures cannot be directly integrated into multistage Cockcroft–Walton rectifiers.

The rectifiers were designed using a substrate with a thickness of 0.8 mm, a dielectric constant of 2.55, and a dissipation factor of 0.0018. The input-side boost capacitor was model GRM155R71H104 (Murata Manufacturing Co., Ltd., Tokyo, Japan) with a capacitance of 10,000 pF, and HSMS286C (Broadcom Limited, Palo Alto, CA, USA) diodes were used.

2.2.1. Design of the Two-Stage Dickson Charge Pump Rectifiers

As shown in Figure 3a, the input ports of the multistage Dickson rectifier are connected in parallel to single-stage rectifiers, which are then connected in series to achieve voltage boosting. A balanced power distribution network with parallel feeding is therefore essential. To minimize mutual interference between single-stage rectifiers, a Wilkinson power distribution network was employed for signal feeding.

Figure 4 shows a photograph of the two-output Wilkinson power dividers, and presents its measured S-parameters. At 5.8 GHz, the reflection coefficient (|S11|) is less than −30 dB, the isolation between output ports (|S23|) is less than −20 dB, and the output power at ports 2 and 3 is approximately −3.2 dB (corresponding to a division loss of 0.2 dB).

Ports 2 and 3 were designed for 50 Ω matching, with a single-stage rectifier connected in parallel to each port. Figure 5 shows the simulation results for the single-stage rectifier, indicating a maximum rectification efficiency of 78% at an optimal load of 1100 Ω and an input power of 30 mW. The matching network was designed to interface with the 50 Ω input port. The two-stage Dickson rectifier was constructed by connecting single-stage rectifiers to the Wilkinson power distribution network and then cascading an additional single-stage rectifier in series at the output.

2.2.2. Two-Stage Cockcroft–Walton Charge Pump Rectifiers Design

Unlike Dickson rectifiers, Cockcroft–Walton rectifiers connect their output capacitors to the output of the previous stage. Class-F load structures cannot be directly applied to multistage Cockcroft–Walton rectifiers because the open-short components in class-F loads act as ground-shorted capacitors. When cascading Cockcroft–Walton rectifiers with class-F loads, the input of the second stage must connect to the output of the first stage; however, the first stage’s output is effectively grounded (due to the class-F load), which reduces the second stage’s output voltage and prevents voltage multiplication.

To address this issue, this study utilized the DC ground on the backside of the circuit board and developed a specific topology for the F-type load incorporated into the Croft-Walton rectifier. The DC output voltage of each stage is connected to the DC ground of the next stage. In this topology, capacitors isolate the DC components of adjacent stages, while the output voltage of the previous stage elevates the ground potential of the subsequent stage. This approach isolates inter-stage DC signals while preserving high-frequency characteristics, ensuring unchanged transmission performance for each stage. As a result, conversion efficiency remains nearly identical to that of single-stage rectifiers, while achieving higher output voltage.

Figure 6 presents the schematic diagram of a two-stage Cockcroft–Walton rectifier with DC isolation structure. Each stage comprises two capacitors and two diodes. The first stage includes capacitor C1, class-F load structure, and diodes D1 and D2. The second stage contains C2, class-F load, and diodes D3 and D4. GND1 and GND2 serve as independent DC grounds for the first and second stages, respectively. To achieve voltage multiplication, the DC output of the first charge pump stage connects to the second stage’s DC ground, specifically, the class-F load structure output connects to GND2. C_DC represents the DC isolation capacitor between the two stages. To minimize the impact of parasitic components on the rectifier, we selected a high DC isolation capacitance value of 10,000 pF.

To validate the proposed circuit topology, we implemented a 5.8 GHz two-stage Cockcroft–Walton rectifier incorporating class-F load structures. An impedance matching network was designed between the power input port and capacitor C1 to ensure that power is efficiently transferred to the diode for rectification, and Figure 7 depicts the S-parameter simulation results of the circuit. The reflection coefficient is very small at the operating frequency, indicating that the input impedance is well-matched so that the rectifying power can be delivered into the circuit with high efficiency.

Figure 8 shows photographs of the fabricated circuit, with the front and back layouts mirrored for comparison. DC isolation capacitors provide isolation and connection between the two stages’ ground planes, ensuring different boosted DC voltages per stage while maintaining uniform AC distribution across the ground plane for proper rectifier operation.

3. Results

Figure 9 shows the block diagram of the measurement system. Prior to testing, the system was calibrated and bias-adjusted to improve measurement precision and reduce systematic errors. The input power at the rectifier’s input port was measured using power sensor B (recording the actual input power), and the offset of power sensor A was adjusted to match sensor B readings.

The rectifier’s input power was monitored via a coupler connected to a power meter for accurate measurement. Specifically, a microwave signal generator produced the test signal, which was amplified by a power amplifier to meet the required input power. A circulator routed reflected signals to the power meter for real-time monitoring, while a multimeter measured the rectifier’s DC output voltage for comprehensive performance analysis.

3.1. Results for Two-Stage Dickson Rectifiers

Figure 10 shows the photograph of the two-stage Dickson class-F charge pump rectifier. Figure 11 presents the measured conversion efficiency and reflection coefficient for input powers of 30 mW, 45 mW, 60 mW, and 75 mW. The maximum conversion efficiency is approximately 69% at 45 mW input power, with an efficiency of 68% at 30 mW.

Conversion efficiency varies by approximately 5% across the tested input power range. When diodes operate in the linear region, no increase in diode loss was observed under equivalent operating conditions. Figure 12 shows the output voltage of the two-stage Dickson rectifier: the maximum output voltage is approximately 9 V at 75 mW input power and 1500 Ω load, while the output voltage is 5.4 V at 30 mW input power.

3.2. Results for Two-Stage Cockcroft–Walton Rectifiers

Figure 12a presents measured conversion efficiency and output voltage versus load resistance. At 30 mW input power, rectification efficiency exceeds 70% across 1800–2500 Ω, with a maximum efficiency of 70.1% and output voltage of 7.2 V at the optimal load of 2100 Ω. Figure 12b illustrates the relationship between conversion efficiency, reflection, and input power at a fixed 2100 Ω load, with peak performance (70.5% efficiency, 7.4 V output) achieved at 30 mW input power.

4. Discussion

This paper enhances multi-stage rectifier performance by replacing conventional output capacitors with class-F loads. According to the operational principle of charge pump rectifiers, each diode in a single-stage rectifier is biased at the same DC voltage. As shown in Figure 13, the output capacitors of Dickson and Cockcroft–Walton multi-stage rectifiers exhibit different biasing due to structural differences. In the Dickson circuit (Figure 13a), the output smoothing capacitor bias increases with the number of stages: for N stages, the bias is N times the single-stage output voltage. In contrast, each stage of the Cockcroft–Walton rectifier (Figure 13b) exhibits an output capacitor bias equivalent to the single-stage output voltage, due to the series relationship of output capacitive biases.

However, the microstrip line in class-F structures typically has low equivalent capacitance, making it difficult to maintain high voltage bias. This leads to reduced output voltage in multistage Dickson rectifiers, as diode bias decreases with the number of stages—further lowering overall conversion efficiency. In contrast, the Cockcroft–Walton circuit maintains consistent output capacitor bias across stages, ensuring stable diode bias in multistage configurations. This enables higher voltage generation while preserving system efficiency. Experimental results confirm this: at 30 mW input power, the two-stage Dickson rectifier achieves a maximum output voltage of 5.4 V and 68% efficiency, while the two-stage Cockcroft–Walton rectifier reaches 7.4 V and 70.5% efficiency. In future work, maximum power point tracking (MPPT) technology—adapted from other energy harvesting fields—will be integrated to optimize the rectifier’s power supply management [28].

Table 1. Comparison with related rectifier circuits.

Ref	Frequency (GHz)	Input Power (mW)	Efficiency (%)	Output Volt (V)	Load Resistance (Ω)	Size (mm2)	Topology
[20]	0.8	6.3 a	66.6	9 b	2500	22 × 24	Dickson
[23]	1.9	63 a	78.2	5.5 b	600	38 × 15	Charge pump
[29]	2.45	20 a	37.5	1.7	20,000	—	Cockcroft–Walton
[30]	5.2	251	64.1	5.1	1150	19 × 18	Dickson
[31]	5.8	126	73.2	5.5 c	330	26 × 12	Single Shunt
[32]	5.8	12.5	43%	—	1500	—	Dickson
Our work	5.8	30	70.5	7.2	2100	50 × 70	Cockcroft–Walton
	5.8	30	68	5.4	1500	50 × 90	Dickson

^a Power values in references given in dBm have been converted for comparison. ^b Estimated from the results in the reference. ^c Calculated from input power, conversion efficiency, and load resistance.

compares the proposed rectifier with previously reported designs, showing superior RF-DC conversion efficiency and output voltage under low input power conditions.

5. Conclusions

This study proposes an innovative cascaded topology for Cockcroft–Walton charge pump rectifiers integrated with class-F filter structures. Circuit DC ground isolation techniques are employed to address cascading challenges between consecutive stages. A two-stage Cockcroft–Walton prototype demonstrates high rectification efficiency and elevated output voltage under low input power conditions. For comparison, a two-stage Dickson rectifier exhibits lower output voltage and efficiency, attributed to its output capacitor bias characteristic (diode bias decreases with increasing stages).

The proposed architecture can be directly integrated into power-receiving terminals, eliminating the need for DC voltage conversion stages and reducing system complexity. It shows great promise for powering low-power sensor networks and wearable monitoring devices.