Sub-Module Capacitor Voltage Ripple Suppression in MMDTC-Based PET Using Three-Port Active Bridge

Abstract

For power electronic transformer (PET) based Modular Multilevel DC-Link Based T-type Converters (MMDTC) with Double Active Bridges (DABs) (namely DABs-based MMDTC-PET), the sub-module capacitor voltages exhibit relatively large ripples. To reduce the voltage ripple of sub-module capacitors, this paper proposes a novel MMDTC-PET structure that utilizes the Three-Port Active Bridges (TABs) to replace the DABs as the isolation stage (TABs-based MMDTC-PET). When the two full bridges of the TAB on the primary side adopt identical phase-shift modulation, the two sub-module capacitors within the upper and lower arms form a parallel connection. This configuration endows the sub-module capacitors with switched-capacitor characteristics, suppressing voltage ripple in the sub-module capacitors and enabling power ripple flow to the secondary side. Meanwhile, by leveraging the characteristic that the AC power components of the upper and lower arm sub-modules have equal amplitudes but opposite phases, these AC power components are mutually canceled on the secondary side of the TAB. Simulation and experimental results verify the effectiveness of the proposed scheme.

1. Introduction

Power Electronic Transformers (PETs) are popular power electronic devices integrating power electronics with high-frequency transformers. Unlike traditional transformers [1,2,3], PETs provide not only voltage conversion and electrical isolation but also advanced regulation functions including fault isolation, power quality regulation, and voltage/current control [4,5].

PETs are categorized into single-stage, two-stage, and three-stage configurations based on conversion series. Three-stage PETs offer the most comprehensive functionality, widest adjustment range, and highest practicality [6,7]. As shown in Figure 1, the three-stage structure comprises input, isolation, and output stages. The isolation stages usually adopt double active bridge (DAB). PETs typically interface with medium- and high-voltage grids. Due to voltage withstand limitations of power devices, multilevel topologies like CHB and MMC have become standard for PET input stages [8,9,10,11]. However, CHB- and MMC-based PETs suffer from high device count and complex control requirements. This paper proposes the Modular Multilevel DC-Link Based T-type Converter (MMDTC) as the PET input stage [12]. Like CHB-PET and MMC-PET, MMDTC sub-module capacitors generate low-frequency voltage ripples, requiring large capacitance values for suppression. Reducing sub-module capacitor voltage ripple enables lower capacitance values and lower hardware costs.

Reference [13] exploits the phase relationship between arm output voltages and capacitor voltages, allowing substantial sub-module capacitor ripple to reduce capacitance requirements. However, this method is limited to reactive power compensation applications. Current capacitor voltage ripple reduction methods primarily target CHB-PET and MMC-PET systems, employing four main approaches: Additional hardware circuits, harmonic injection, control strategy optimization, and power path construction. The hardware circuit approach involves large-capacity capacitors and additional filters [14,15,16]. While simple and effective, it significantly increases PET volume and cost. The harmonic injection approach, widely used in CHB- and MMC-PETs [17,18], is unsuitable for MMDTC since it lacks circulating current loops and synthesizes line voltage through upper and lower arm outputs, making both circulating current and zero-sequence voltage injection inapplicable. Control strategy optimization mitigates capacitor voltage ripple through enhanced algorithms. Reference [19] introduced a three-phase AC/DC/DC converter controller that reduces capacitance by eliminating ripple. Reference [20] developed active ripple suppression techniques. Reference [21] presented phase-shift control with feedback linearization and second-order ripple feedforward based on large-signal DC/DC converter models. Reference [22] proposed output impedance-based methods using current feedforward to reduce capacitor values. However, the above control optimization methods demonstrate limited ripple suppression capability.

The power path construction method creates paths to decouple ripple power from sub-module capacitors and transfer it to the low-voltage side for cancelation, thereby reducing or eliminating voltage ripple. References [23,24,25] integrate CHB with single-inductor four-active-bridge configurations to establish low-frequency ripple power paths, minimizing sub-module capacitor ripple without complex control. Reference [26] employs primary synchronous switch modulation of four-port active bridges to enable switched-capacitor characteristics in three-phase MMC arms, achieving ripple power cancelation through three-phase symmetry. Reference [27] presents a three-phase integrated PET topology that reduces DC-link capacitor values by 85%. Reference [28] integrates an isolated three-port DC-DC converter with MMC, providing fundamental-frequency power paths to reduce capacitor voltage ripple. Reference [29] introduces cascaded modular isolated back-to-back PET with six-terminal active bridges, proposing switching synchronization hybrid phase-shift modulation to decouple low-frequency ripple components. Reference [30] links all sub-module capacitors to a common bus for switched-capacitor operation, substantially reducing capacitor values without additional voltage balance control. Reference [31] integrates MMC with resonant push-pull converters to create power decoupling paths among sub-modules, naturally eliminating second-harmonic circulating current and reducing ripple voltage. While these methods theoretically enable complete ripple suppression by exploiting power ripple symmetry, most rely on mutual coupling control among three-phase sub-modules of MMC or CHB. This increases switching device driving complexity, reduces control flexibility, and is unsuitable for MMDTC with only a single DC link.

To address the inherent limitations of existing capacitor voltage ripple suppression methods for MMDTC-based PET, this paper proposes a novel approach utilizing TABs in the isolation stage. The main contributions of this work are summarized as follows:

(1)

Novel TAB-based topology for MMDTC-PET: A TAB-based MMDTC-PET structure is proposed where the two input terminals of each TAB are connected to corresponding sub-modules in the upper and lower arms, respectively. This configuration enables direct power coupling between paired sub-modules while maintaining isolation from the LVDC bus.

(2)

Switched-capacitor principle implementation: By employing identical phase-shift modulation for the two input-side full bridges of TAB, the sub-module capacitors in upper and lower arms naturally form a switched-capacitor configuration under high-frequency switching states to suppress the capacitor voltage ripple.

(3)

Inherent ripple power cancelation mechanism: The proposed scheme leverages the characteristic that AC power components in upper and lower arms have equal amplitudes but opposite phases. These components are automatically transferred through the low-impedance switched-capacitor path to the secondary side where they cancel out, achieving ripple suppression without active control intervention.

2. DAB-Based MMDTC-PET

2.1. Topology Structure

Similarly to CHB- and MMC-PETs, the input port of each DAB is individually connected to its corresponding submodule. The output port of all DABs are connected in parallel to form a low-voltage DC (LVDC) bus, as illustrated in Figure 2. The MMDTC adopts a T-type configuration comprising three phases (A, B, and C). Each phase consists of three high-voltage switching devices, which can be implemented using thyristors, IGCTs, or series-connected IGBTs [12,13]. The DC-link is formed by the series connection of the upper and lower arms. Each arm comprises N cascaded half-bridge submodules (HBSMs), with all HBSMs utilizing IGBT-based power modules.

2.2. Working Principle

The working principle of the DAB-based MMDTC-PET can be described as follows: The upper and lower arm generate non-negative multilevel voltage waveforms according to a predetermined pattern. Subsequently, the T-type structure synthesizes the desired three-phase multilevel line voltages based on this pattern. Specifically, the switching functions of each phase in the T-type structure are defined as S_x (x = a, b, c), where S_x = 1, 0, and −1 correspond to the conduction states of the upper, middle, and lower switches in phase x, respectively. Each fundamental frequency cycle is divided into six sectors (I–VI), with the operational modes of the T-type structure defined accordingly within these sectors. Based on these operational modes, the relationship between the arm output voltage and the line voltage can be derived, as illustrated in Figure 3.

Power from the high-voltage grid is delivered to the input port of each DAB through the HBSM After conversion by the DABs, the power is subsequently transferred to the LVDC bus. It should be noted that capacitor C (Figure 2b) serves as an interface for power transfer between the HBSM and the DAB. However, due to inherent power fluctuations at the HBSM input, voltage ripple across the capacitor is unavoidable. The generation mechanism of this voltage ripple will be elaborated in the following section.

2.3. The Generation Mechanism of Voltage Ripple Across Capacitor

The output phase-voltages of MMDTC are defined as follows:

$$\left\{\begin{array}{c}{u}_{\mathrm{AO}}=V\sin (\mathsf{\omega }t+{\displaystyle \frac{\mathsf{\pi }}{6}})\\ u_{\mathrm{BO}}=V\sin (\mathsf{\omega }t-{\displaystyle \frac{\mathsf{\pi }}{2}})\\ u_{\mathrm{CO}}=V\sin (\mathsf{\omega }t+{\displaystyle \frac{5\mathsf{\pi }}{6}})\end{array}\right.$$

(1)

where V denotes the amplitude of the output phase voltage, and ω = 2πf. Based on Equation (1), the expression for the three-phase line voltage can be derived as follows:

$$\left\{\begin{array}{l}{u}_{\mathrm{AB}}=\sqrt{3}V\sin (\mathsf{\omega }t+{\displaystyle \frac{\mathsf{\pi }}{3}})\\ u_{\mathrm{BC}}=\sqrt{3}V\sin (\mathsf{\omega }t-{\displaystyle \frac{\mathsf{\pi }}{3}})\\ u_{\mathrm{CA}}=-\sqrt{3}V\sin (\mathsf{\omega }t)\end{array}\right.$$

(2)

As shown in Figure 3, the upper and lower arm voltages, u_UN and u_NL, can be derived as follows:

$$u_{\mathrm{UN}}=\left\{\begin{array}{ll}\sqrt{3}V\sin \theta ,& \theta \in [0,{\displaystyle \frac{\mathsf{\pi }}{3}})\\ \sqrt{3}V\sin (\theta +{\displaystyle \frac{\mathsf{\pi }}{3}}),& \theta \in [{\displaystyle \frac{\mathsf{\pi }}{3}},{\displaystyle \frac{2\mathsf{\pi }}{3}}]\end{array}\right.$$

(3)

$$u_{\mathrm{NL}}=\left\{\begin{array}{ll}-\sqrt{3}V\sin (\theta -{\displaystyle \frac{\mathsf{\pi }}{3}}),& \theta \in [0,{\displaystyle \frac{\mathsf{\pi }}{3}})\\ \sqrt{3}V\sin (\theta -{\displaystyle \frac{\mathsf{\pi }}{3}}),& \theta \in [{\displaystyle \frac{\mathsf{\pi }}{3}},{\displaystyle \frac{2\mathsf{\pi }}{3}}]\end{array}\right.$$

(4)

where $\theta =\mathsf{\omega }t-floor(\mathsf{\omega }t/({\displaystyle \frac{2\pi }{3}}))$, and the floor function is represented by floor(x).

The three-phase output current of MMDTC is defined as follows:

$$\left\{\begin{array}{l}{i}_{\mathrm{a}}=I\sin (\mathsf{\omega }t+{\displaystyle \frac{\mathsf{\pi }}{6}}+\phi )\\ i_{\mathrm{b}}=I\sin (\mathsf{\omega }t-{\displaystyle \frac{\mathsf{\pi }}{2}}+\phi )\\ i_{\mathrm{c}}=I\sin (\mathsf{\omega }t+{\displaystyle \frac{5\mathsf{\pi }}{6}}+\phi )\end{array}\right.$$

(5)

where I denotes the amplitude of the output current, whereas φ signifies the power factor angle. According to the working principle of the T-type structure depicted in Figure 3, the arm current can be deduced as follows:

$$i_{\mathrm{up}}=-I\sin (\theta +{\displaystyle \frac{\pi }{6}}+\phi )\theta \in [0,{\displaystyle \frac{2\mathsf{\pi }}{3}}]$$

(6)

$$i_{\mathrm{low}}=\left\{\begin{array}{ll}I\sin (\theta -{\displaystyle \frac{\pi }{2}}+\phi )& \theta \in [0,{\displaystyle \frac{\mathsf{\pi }}{3}})\\ I\sin (\theta +{\displaystyle \frac{5\pi }{6}}+\phi )& \theta \in [{\displaystyle \frac{\mathsf{\pi }}{3}},{\displaystyle \frac{2\mathsf{\pi }}{3}}]\end{array}\right.$$

(7)

Neglecting the power losses within the MMDTC and assuming equal power transmission through each HBSM, the power delivered to each HBSM in both the upper and lower arms can be derived from Equations (3), (4), (6) and (7).

$$p_{\mathrm{up}}=\left\{\begin{array}{ll}{\displaystyle \frac{\sqrt{3}VI}{2\mathrm{N}}}[\cos (2\theta +{\displaystyle \frac{\mathsf{\pi }}{6}}+\phi )-\cos ({\displaystyle \frac{\mathsf{\pi }}{6}}+\phi )],& \theta \in [0,{\displaystyle \frac{\mathsf{\pi }}{3}})\\ {\displaystyle \frac{\sqrt{3}VI}{2\mathrm{N}}}[-\sin (2\theta +\phi )-\cos ({\displaystyle \frac{\mathsf{\pi }}{6}}-\phi )],& \theta \in [{\displaystyle \frac{\mathsf{\pi }}{3}},{\displaystyle \frac{2\mathsf{\pi }}{3}}]\end{array}\right.$$

(8)

$$p_{\mathrm{low}}=\left\{\begin{array}{ll}{\displaystyle \frac{\sqrt{3}VI}{2\mathrm{N}}}[\cos (2\theta -{\displaystyle \frac{5\mathsf{\pi }}{6}}+\phi )-\cos ({\displaystyle \frac{\mathsf{\pi }}{6}}-\phi )],& \theta \in [0,{\displaystyle \frac{\mathsf{\pi }}{3}})\\ -{\displaystyle \frac{\sqrt{3}VI}{2\mathrm{N}}}[-\sin (2\theta +\phi )+\cos ({\displaystyle \frac{\mathsf{\pi }}{6}}+\phi )],& \theta \in [{\displaystyle \frac{\mathsf{\pi }}{3}},{\displaystyle \frac{2\mathsf{\pi }}{3}}]\end{array}\right.$$

(9)

By expanding the above equations using Fourier series analysis and neglecting higher-order harmonic terms, the power expressions for the HBSMs can be written as:

$$p_{\mathrm{up}}(t)\approx {\mathrm{a}}_0+{\mathrm{a}}_1\cos (3\mathsf{\omega }t)-{\mathrm{b}}_1\sin (3\mathsf{\omega }t)$$

(10)

$$p_{\mathrm{low}}(t)\approx {\mathrm{a}}_0-{\mathrm{a}}_1\cos (3\mathsf{\omega }t)+{\mathrm{b}}_1\sin (3\mathsf{\omega }t)$$

(11)

where ${\mathrm{a}}_0=-{\displaystyle \frac{3VI}{4\mathrm{N}}}\cos (\phi )$, ${\mathrm{a}}_1={\displaystyle \frac{6\sqrt{3}VI}{5\mathsf{\pi }\mathrm{N}}}\cos (\phi )$, ${\mathrm{b}}_1=-{\displaystyle \frac{4\sqrt{3}VI}{5\mathsf{\pi }\mathrm{N}}}\cos (\phi )$.

As clearly observed from Equations (10) and (11), the power transmitted by the HBSMs consists of a DC component and a triple-frequency component. Furthermore, the amplitudes of the triple-frequency power transmitted by the HBSMs in the upper and lower arms are identical, while their phases are opposite.

To facilitate the analysis of power flow characteristics between the HBSM and DAB, power transmission schematic diagrams of the upper and lower arm submodules are presented. As shown in Figure 4, p_upD and p_lowD denote the power flowing into the DAB from HBSM of the upper and lower arms, respectively; p_upC and p_lowC represent the power flowing into the capacitors C; and p_L denotes the power delivered to the LVDC bus. For the DC components in p_up and p_low, the capacitive impedance approaches infinity at DC. Consequently, these DC components are entirely transferred to the DAB. In contrast, the capacitive impedance is relatively low for the AC components, allowing only a portion of the AC components to reach the DAB, while the remainder is absorbed by the capacitor. This diversion of AC components to the capacitor C_up (C_low) inevitably generates voltage ripple across it, which will be analyzed in detail in the following section.

Assuming that the proportion of the AC component transmitted to the DAB is denoted by ξ, then p_upD and p_lowD can be mathematically expressed as follows:

$$\left\{\begin{array}{l}{p}_{\mathrm{upD}}={\overline{p}}_{\mathrm{up}}+\xi {\tilde{p}}_{\mathrm{up}}\\ p_{\mathrm{lowD}}={\overline{p}}_{\mathrm{low}}+\xi {\tilde{p}}_{\mathrm{low}}\end{array}\right.0\le \xi \le 1$$

(12)

where ${\overline{p}}_{\mathrm{up}}$, ${\tilde{p}}_{\mathrm{up}}$, ${\overline{p}}_{\mathrm{low}}$ and ${\tilde{p}}_{\mathrm{low}}$ denote the DC and AC components of p_up and p_low, respectively.

Furthermore, the AC power across capacitors C_up and C_low is obtained:

$$\left\{\begin{array}{l}{\tilde{p}}_{\mathrm{upC}}=(1-\xi ){\tilde{p}}_{\mathrm{up}}\\ {\tilde{p}}_{\mathrm{lowC}}=(1-\xi ){\tilde{p}}_{\mathrm{low}}\end{array}\right.0\le \xi \le 1$$

(13)

Based on the principle of instantaneous power conservation, the following relationship can be derived:

$${\tilde{p}}_{\mathrm{upC}}\approx \mathrm{C}{\overline{u}}_{\mathrm{C}\text{\_}\mathrm{up}}{\displaystyle \frac{\mathrm{d}{\tilde{u}}_{\mathrm{C}\text{\_}\mathrm{up}}}{\mathrm{d}t}}$$

(14)

where ${\overline{u}}_{\mathrm{C}\text{\_}\mathrm{up}}$ represents the DC component of the capacitor voltage, while ${\tilde{u}}_{\mathrm{C}\text{\_}\mathrm{up}}$ corresponds to its AC component.

Furthermore, the instantaneous voltage across the capacitor in the upper arm can be expressed as derived in Equation (15). Similarly, the instantaneous voltage across the capacitor in the lower arm is given by Equation (16).

$${\tilde{u}}_{\mathrm{C}\text{\_}\mathrm{up}}(t)=U_{\mathrm{peak}}-{\displaystyle \frac{VI(1-\xi )(\mathsf{\pi }-3\theta )[\cos (3\theta -\phi )+5\cos (3\theta +\phi )]}{5\sqrt{3}\mathrm{CN}\mathsf{\pi }{\overline{u}}_{\mathrm{c}\text{\_}\mathrm{up}}\mathsf{\omega }}},\theta \in [0,{\displaystyle \frac{2\mathsf{\pi }}{3}}]$$

(15)

$${\tilde{u}}_{\mathrm{C}\text{\_}\mathrm{low}}(t)=U_{\mathrm{peak}}+{\displaystyle \frac{VI(1-\xi )(\mathsf{\pi }-3\theta )[\cos (3\theta -\phi )+5\cos (3\theta +\phi )]}{5\sqrt{3}\mathrm{CN}\mathsf{\pi }{\overline{u}}_{\mathrm{c}\text{\_}\mathrm{low}}\mathsf{\omega }}},\theta \in [0,{\displaystyle \frac{2\mathsf{\pi }}{3}}]$$

(16)

By applying Fourier expansion to Equations (15) and (16), the corresponding frequency-domain representations can be obtained:

$${\tilde{u}}_{\mathrm{C}\text{\_}\mathrm{up}}(t)\approx {\mathrm{c}}_0-{\mathrm{c}}_1\cos (3\mathsf{\omega }t)-{\mathrm{d}}_1\sin (3\mathsf{\omega }t)$$

(17)

$${\tilde{u}}_{\mathrm{C}\text{\_}\mathrm{low}}(t)\approx {\mathrm{c}}_0+{\mathrm{c}}_1\cos (3\mathsf{\omega }t)+{\mathrm{d}}_1\sin (3\mathsf{\omega }t)$$

(18)

where

$$\begin{array}{l}{\mathrm{c}}_0=U_{\mathrm{peak}}+{\displaystyle \frac{24VI(1-\xi )\sin (\phi )}{30\sqrt{3}\mathsf{\pi }\mathrm{CN}{\overline{u}}_{\mathrm{c}\text{\_}\mathrm{up}}\mathsf{\omega }}}\\ {\mathrm{c}}_1={\displaystyle \frac{2VI(1-\xi )\sin (\phi )}{5\sqrt{3}\mathsf{\pi }\mathrm{CN}{\overline{u}}_{\mathrm{c}\text{\_}\mathrm{up}}\mathsf{\omega }}}\\ {\mathrm{d}}_1=-{\displaystyle \frac{\sqrt{3}VI(1-\xi )\cos (\phi )}{5\mathsf{\pi }\mathrm{CN}{\overline{u}}_{\mathrm{c}\text{\_}\mathrm{up}}\mathsf{\omega }}}\end{array}$$

(19)

As can be observed from Equations (17) and (18), a triple-frequency ripple voltage is generated across the capacitor. The magnitude of this ripple voltage is inversely proportional to the transmission ratio ξ. In other words, an increase in ξ results in a decrease in the triple-frequency ripple. Ideally, when ξ = 1, the triple-frequency ripple in the capacitor voltage disappears entirely.

However, the DAB operates in a high-frequency state and exhibits relatively high input inductive impedance [32], which significantly hinders the transmission of the AC component. Consequently, ξ tends to be small, indicating that the majority of the AC component from the HBSM will flow into the capacitor. To mitigate capacitor voltage fluctuations, a capacitor with a relatively large capacitance value is typically required.

Interestingly, increasing the transmission ratio ξ can reduce the capacitor voltage ripple, thereby allowing for a lower required capacitance value. To achieve this, this paper proposes using the TAB in place of the DAB. By applying the switched-capacitor principle to decrease the input inductive reactance and consequently increase the transmission ratio ξ, the capacitor voltage ripple can be effectively suppressed. The detailed analysis is presented as follows.

3. The Proposed TAB-Based MMDTC-PET

3.1. Topology Structure

The topology of the TAB-based MMDTC-PET is illustrated in Figure 5. The TAB comprises two input ports and one output port. These input ports are, respectively, connected to a sub-module in the upper and lower arms, while the output port is linked to the LVDC.

The equivalent model of the TAB is illustrated in Figure 6a. The two full-bridges at the input port of the TAB employ an identical phase-shift modulation strategy, as detailed in Figure 6b. Here, u₁ and u₂ represent the output voltages of these two full-bridge converters at the input port, respectively, while u₃ denotes the output voltage at the output port. The phase angles of the modulation signals for the two input-side full bridges are denoted by β₁ and β₂, with β₁ = β₂. The phase angle of the modulation signal for the output-side full bridge is β₃, and the phase-shift angle is defined as β = β₃ − β₁. By adjusting the magnitude of this phase-shift angle β, the power flow through the TAB can be effectively controlled.

All three full-bridge employ PWM modulation with a switching period of T_s and a duty cycle of 50%. During the first half of the switching period T_s1, the switching devices S₁/S₄ and S₅/S₈ are turned on. As a result, both input-side full-bridges output a positive voltage level, allowing the capacitors C_up and C_low to be directly connected in parallel. Similarly, during the second half of the switching period T_s2, the switching devices S₂/S₃ and S₆/S₇ are activated. Again, both input-side full bridges generate a negative voltage level, enabling C_up and C_low to be connected in parallel as illustrated in Figure 6c,d. Under high-frequency PWM modulation, C_up and C_low together form a switched-capacitor structure, enabling continuous charging and discharging between the two capacitors.

3.2. Analysis of the Voltage Ripple Suppression Principle

Figure 7a presents a schematic diagram of the current flow path in the switched-capacitor circuit, while Figure 7b illustrates the corresponding equivalent impedance model. In these diagrams, i_{sm_up} and i_{sm_low} denote the equivalent AC current sources representing the sub-modules. Due to the very low line impedance of the two capacitors connected in parallel, their voltages constrain each other and tend to equalize.

In the TAB, no external inductor is connected to the primary side of the transformer winding. However, the transformer winding inherently exhibits leakage inductance. Taking into account the influence of the transformer’s leakage impedance, L_up and L_low represent the leakage inductances of the transformers associated with the upper and lower arm sub-module.

Define the equivalent impedances of the upper and lower arm sub-modules as Z_up and Z_low, respectively, as illustrated in Figure 7c,d. Taking the upper arm as an example, its equivalent input impedance with respect to the lower arm is:

$$Z_{\mathrm{up}}=Z_{\mathrm{Clow}}+Z_{\mathrm{Llow}}+Z_{\mathrm{Lup}}$$

(20)

where Z_Clow represents the capacitive impedance of the sub-module within the lower arm, and is expressed as Z_Clow = 1/jωC_low. Z_Lup, Z_Llow denote the inductive impedances associated with the leakage inductance, and are given by Z_Lup/low = jωL_up/low.

The ripple currents of the sub-module capacitors in the upper and lower arms, originating from the equivalent AC current source input and the primary side of the TAB, are denoted as i_{Cup/low_sm} and i_Tup/low, respectively. Taking the upper arm as an example, based on the circuit’s equivalent model, the relationships among i_{sm_up}, i_{Cup_sm}, and i_Tup can be derived:

$$\left\{\begin{array}{l}{i}_{\mathrm{sm}\text{\_}\mathrm{up}}=i_{\mathrm{Cup}\text{\_}\mathrm{sm}}+i_{\mathrm{Tup}}\\ i_{\mathrm{Tup}}=i_{\mathrm{sm}\text{\_}\mathrm{up}}.{\displaystyle \frac{Z_{\mathrm{Cup}}}{Z_{\mathrm{Cup}}+Z_{\mathrm{up}}}}\\ i_{\mathrm{Cup}\text{\_}\mathrm{sm}}=i_{\mathrm{sm}\text{\_}\mathrm{up}}.{\displaystyle \frac{Z_{\mathrm{up}}}{Z_{\mathrm{Cup}}+Z_{\mathrm{up}}}}\end{array}\right.$$

(21)

In Figure 7a, the current flowing into the upper arm from the equivalent AC current source i_Tlow is denoted as i_{Cup_Tlow}. According to Kirchhoff’s Current Law (KCL), it can be obtained that i_{Cup_Tlow =} i_Tlow. Based on the superposition theorem and assuming that all sub-module capacitances and transformer parameters are identical, it follows that Z_Cup = Z_Clow = 1/jωC and Z_Lup = Z_Llow = jωL, where C represents the capacitance and L denotes the leakage inductance. Under these conditions, the current i_Cup flowing through the capacitor can be expressed as:

$$\begin{array}{ccc}\hfill i_{\mathrm{Cup}}& =& i_{\mathrm{Cup}\text{\_}\mathrm{sm}}+i_{\mathrm{Cup}\text{\_}\mathrm{Tlow}}\hfill \\ & =& i_{\mathrm{sm}\text{\_}\mathrm{up}}\cdot {\displaystyle \frac{{\mathrm{Z}}_{\mathrm{up}}}{{\mathrm{Z}}_{\mathrm{Cup}}+{\mathrm{Z}}_{\mathrm{up}}}}+i_{\mathrm{sm}\text{\_}\mathrm{low}}\cdot {\displaystyle \frac{{\mathrm{Z}}_{\mathrm{Clow}}}{{\mathrm{Z}}_{\mathrm{Clow}}+{\mathrm{Z}}_{\mathrm{low}}}}\hfill \\ & =& i_{\mathrm{sm}\text{\_}\mathrm{up}}\cdot {\displaystyle \frac{1}{1-\frac{1}{{\mathsf{\omega }}^2\mathrm{CL}}}}\hfill \end{array}$$

(22)

Based on the fundamental relationship between voltage and current in a capacitor, the following expression can be derived:

$${\displaystyle \frac{d{\tilde{u}}_{\mathrm{C}\text{\_}\mathrm{up}}}{dt}}={\displaystyle \frac{1}{(1-\frac{1}{{\mathsf{\omega }}^2\mathrm{CL}})\mathrm{CN}{\overline{u}}_{\mathrm{c}\text{\_}\mathrm{up}}\mathsf{\omega }}}[{\displaystyle \frac{6\sqrt{3}VI\cos (\phi )}{5\mathsf{\pi }}}\cos (2\theta )-{\displaystyle \frac{4\sqrt{3}VI\cos (\phi )}{5\mathsf{\pi }}}\sin (2\theta )],\theta \in [0,{\displaystyle \frac{2\mathsf{\pi }}{3}}]$$

(23)

Integrating the expression yields the voltage across the capacitor:

$${\tilde{u}}_{\mathrm{C}\text{\_}\mathrm{up}}=U_{\mathrm{peak}}+{\displaystyle \frac{\mathrm{L}VI\mathsf{\omega }(\mathsf{\pi }-3\theta )[\cos (3\theta -\phi )+5\cos (3\theta +\phi )]}{5\sqrt{3}\mathrm{N}\mathsf{\pi }{\overline{u}}_{\mathrm{c}\text{\_}\mathrm{up}}(1-{\mathrm{CL}\mathsf{\omega }}^2)}},\theta \in [0,{\displaystyle \frac{2\mathsf{\pi }}{3}}]$$

(24)

when θ = 0, the valley value U_valley is achieved. Let ∆${\tilde{u}}_{\mathrm{C}\text{\_}\mathrm{up}}$ = U_peak − U_valley, that is:

$$\begin{array}{cc}\hfill \Delta {\tilde{u}}_{\mathrm{C}\text{\_}\mathrm{up}}& =U_{\mathrm{peak}}-U_{\mathrm{valley}}\hfill \\ & ={\displaystyle \frac{2\sqrt{3}VI\mathsf{\omega }\cos (\phi )}{5\mathrm{N}{\overline{u}}_{\mathrm{c}\text{\_}\mathrm{up}}(\frac{1}{\mathrm{L}}-{\mathrm{C}\mathsf{\omega }}^2)}}\hfill \end{array}$$

(25)

As can be seen from Equations (22) and (25), the presence of leakage inductance L prevents the ripple current from being completely decoupled from the sub-module capacitor. However, by minimizing the leakage inductance during the design phase, its impact can be significantly reduced. Therefore, the leakage inductance L of the high-frequency transformer in the TAB is designed to be as small as possible, enabling i_cup to approach zero. This indicates that by utilizing the low-impedance characteristic of the switched-capacitor circuit’s equivalent connection, the fluctuating current i_{sm_up} is effectively decoupled from the sub-module capacitor and redirected to the secondary side of the high-frequency transformer at the TAB level, without requiring additional control for ripple power transfer.

Therefore, the ripple power transmission process can be equivalently described as follows: The AC components i_{sm_up/low} are transferred to the secondary side of the high-frequency transformer through the low-impedance path formed in the switched-capacitor circuit. Due to the characteristic that the amplitudes of the low-frequency ripple power in the upper and lower arms are equal while their phases are opposite, the ripple current that would otherwise flow into the sub-module capacitor cancels out on the common low-voltage DC bus, thereby eliminating its impact on the sub-module capacitor. As a result, only DC power flows into the LVDC bus, and the capacitor voltages of the sub-modules in both the upper and lower arms are mutually clamped, exhibiting only minor voltage ripples.

Therefore, the ripple power transmission process can be equivalently described as follows: The AC components i_{sm_up/low} are transferred to the secondary side of the high-frequency transformer through the low-impedance path formed in the switched-capacitor circuit. Due to the characteristic that the amplitudes of the low-frequency ripple power in the upper and lower arms are equal while their phases are opposite, the ripple current that would otherwise flow into the sub-module capacitor cancels out on the common LVDC bus, thereby eliminating its impact on the sub-module capacitor. As a result, only DC power flows into the LVDC bus, and the capacitor voltages of the sub-modules in both the upper and lower arms are mutually clamped, exhibiting only minor voltage ripples.

4. Simulation and Experimental Validation

4.1. Simulation Results

To verify the effectiveness of the proposed TAB in mitigating low-frequency voltage ripple across the capacitor, simulation models for both the DAB-MMDTC-PET and TAB-MMDTC-PET systems were developed using Simulink. The detailed simulation parameters are provided in

Table 1. The main parameters of simulation.

Variable	Symbol	Value
Rated grid phase voltage	Vg	10 kV
AC filtering inductor	Ls	2 mH
Rated active power	Prated	1 MW
Fundamental frequency	f	50 Hz
Number of SMs per arm	N	20
Voltage of submodule capacitor	uc	750 V
Submodule capacitor	C	0.5 mF
Carrier frequency	fc	10 kHz
LVDC bus voltage	uLVDC	750 V
DAB Transformer Turn Ratio	n1:n2	1:1
TAB Transformer Turn Ratio	n1:n2:n3	1:1:1
DAB additional inductor	L	25 μH
TAB additional inductor	L	25 μH
Switching frequency	fs	40 kHz

.

Figure 8a–d present comparative simulation results for both the conventional DAB scheme and the proposed TAB scheme, illustrating output line voltages, output currents, arm voltages, and arm currents. The results demonstrate that the fundamental operational characteristics of the MMDTC remain consistent regardless of the isolation stage configuration employed.

For the conventional DAB scheme, Figure 9 displays current waveforms and corresponding FFT analyses at three critical measurement points: The HBSM output, the sub-module capacitor input, and the DAB input. As shown in Figure 9a, the HBSM output current comprises a DC component of 34 A and a triple-frequency component of 36 A. Figure 9b,c reveals that the triple-frequency AC component predominantly flows into the sub-module capacitor, while the DC component is primarily transferred to the DAB input. These observations validate the theoretical analysis presented in Section 2.3.

For the proposed TAB scheme, Figure 10 presents current waveforms and FFT analyses at the corresponding measurement points. Comparing Figure 9a and Figure 10a, the DC and triple-frequency AC components at the HBSM output remain virtually identical. However, a dramatic reduction in the triple-frequency AC component is observed in the sub-module capacitor current when comparing Figure 9b and Figure 10b. This significant improvement results from the effective redirection of the triple-frequency AC component to the TAB, as evidenced in Figure 10c, demonstrating the successful implementation of the ripple power decoupling mechanism.

Figure 11 compares the capacitor voltages of all sub-modules in both upper and lower arms under the conventional DAB scheme and the proposed TAB scheme. The comparison clearly demonstrates that the sub-module capacitor voltage ripple ratio is dramatically reduced from 24% to 2.5% under identical operating conditions, validating the superior ripple suppression capability of the proposed TAB scheme.

Figure 12a–c illustrates the input and output port currents of the TAB along with their corresponding FFT analyses. The results reveal prominent triple-frequency components in both input ports with opposite phase relationships. Notably, the output port exhibits negligible triple-frequency content, confirming that the equal-amplitude, opposite-phase triple-frequency components from the two input ports effectively cancel at the output. This phenomenon validates the natural ripple cancelation mechanism inherent in the proposed topology.

Figure 13 presents the system’s dynamic response under sudden load variations on the LVDC side. The results include three-phase grid-connected currents (Figure 13a), LVDC bus voltage and current (Figure 13b,c), and sub-module capacitor voltages (Figure 13d). The waveforms demonstrate rapid convergence to steady-state following the load disturbance, confirming the system’s robust dynamic performance and stability under transient conditions.

For a more intuitive comparison, this paper compares the hardware costs of using two DABs versus one TAB structure. Both topologies primarily consist of capacitors, IGBT devices, and high-frequency transformers.

In terms of capacitor cost, the submodule capacitor selection refers to

Table 2. (a). Technical parameters list of capacitor. (b). Comparison results in terms of capacitor costs. (c). Technical parameters list of IGBTs. (d). Comparison results in terms of IGBT costs.

(a)
Model	Capacitance				Cost Per		Normal Voltage
ALF80(1)122FP500	1.2 mF				$19.84		500 V
(b)
Type			Double DABs						Single TAB
Capacitance required			4.8 mF						0.5 mF
Total Number of capacitors			18 (Two in series and nine in parallel)						2 (Two in series)
Total cost			$317.44						$39.68
(c)
Model				Normal Voltage		Cost Per		Rated Current		Switching Frequency
APTGL90H120T3G (IGBT)				1200 V		$112.8		110 A		20–50 kHz
FF50R12RT4HOSA1(IGBT)				1200 V		$60.7		50 A		20–50 kHz
(d)
Type		Double DABs						Single TAB
Total Number of IGBTs		16(FF50R12RT4HOSA1)						8(FF50R12RT4HOSA1) + 4(APTGL90H120T3G)
Total cost		$971.2						$936.8

(a), with the specific model being ALF80(1)122FP500 manufactured by KEMET. Assuming a capacitor voltage fluctuation ratio λ of 2.5%, the required capacitance values for the DAB and TAB schemes were calculated, with the results presented in Table 2(b). The selected capacitors have a rated voltage of 500 V and a nominal capacitance of 1.2 mF. In practical applications, series-parallel combinations are required to achieve the desired capacitance value. Compared to the DAB-based solution, the TAB structure reduces capacitor costs by approximately 87.5%, from $317.44 to $39.68.

Regarding switching device costs, the selected IGBT models are Infineon’s APTGL90H120T3G and FF50R12RT4HOSA1, with detailed parameters provided in Table 2(c). As shown in Table 2(d), since the current flowing through the secondary-side switching devices in the TAB topology is twice that of the primary side, secondary-side devices with double the rated current must be used. Ultimately, the total cost of switching devices is reduced by approximately 3%, from $971.2 to $936.8.

In terms of high-frequency transformers, the conventional DAB approach requires two independent transformers along with their associated magnetic components and control circuits. In contrast, the proposed TAB method uses only one three-winding transformer, effectively reducing the number of magnetic components while maintaining equivalent functionality.

4.2. Experimental Results

Due to the limitations of the power electronics experimental setup in our laboratory, constructing a complete TAB-based MMDTC-PET circuit is highly challenging. Consequently, a simplified experimental approach was adopted, as illustrated in Figure 14. Two DC-DC converters are utilized to emulate the triple-frequency power output of the upper and lower arm submodules in the MMDTC. Specifically, the PWM signals for the DC-DC converters are generated by comparing a modulation wave containing triple-frequency components with a triangular carrier wave. Furthermore, the amplitudes of these triple-frequency components are identical in both modulated waves, but their phases are opposite. The prototype of the experimental platform is illustrated in Figure 15, where RT-LAB serves as the controller and the detailed experimental parameters are summarized in

Table 3. The main experimental parameters.

Variable	Symbol	Value
Rated active power	Prated	500 W
Input voltage of DC-source	U1	105 V
Output voltage of TAB	U2	100 V
Load	R	20 Ω
PWM carrier frequency	fc	10 kHz
Switching frequency	fs	10 kHz
Submodule capacitor	C	470 μF
TAB additional inductor	L	167 μH

.

Figure 16 presents the current waveforms at the three critical measurement points—1′, 2′, and 3′—as shown in Figure 14, along with their corresponding FFT analyses. The current at each measurement point represents the DC-DC converter output current, the capacitor input current, and the TAB input current, respectively. The FFT results demonstrate that the majority of triple-frequency components present in the DC-DC output current are directed toward the TAB, whereas the capacitor input current consists only of higher-order harmonics. Figure 17 illustrates the current waveforms at measurement points 2′, 4′, and 5′. The currents at points 2′ and 4′ correspond to the TAB input current, while the current at point 5′ represents the TAB output current. As shown in Figure 17, the input current to the TAB contains triple-frequency components with opposite phase relationships, whereas the output current is free from such triple-frequency fluctuations.

Figure 18 presents the output voltage waveforms of the DC-DC converter and the TAB output voltage. As shown, the output voltages of the two DC-DC converters exhibit triple-frequency ripple that are phase-opposed. The amplitude of the ripple voltage is 10 V, whereas the TAB output voltage remains consistently stable at 100 V. This indicates that, under the same phase modulation of the two full bridges on the primary side, the triple-frequency ripple component in the input current automatically cancels out on the output side due to the opposite phase characteristics of the triple-frequency components. Only the DC component is transferred to the output side of the TAB, which verifies the effectiveness of the TAB’s cancelation scheme for triple-frequency ripple.

5. Conclusions

This paper proposes a novel TAB-based MMDTC-PET topology to effectively suppress sub-module capacitor voltage ripple. By replacing conventional DABs with TABs and employing identical phase-shift modulation for the two primary-side full bridges, the proposed scheme creates a switched-capacitor configuration that provides a low-impedance path for ripple power. The theoretical analysis reveals that this configuration enables the redirection of triple-frequency AC components away from sub-module capacitors to the TAB secondary side, where they naturally cancel due to their equal-amplitude, opposite-phase characteristics in upper and lower arms. Simulation results demonstrate that the proposed method reduces capacitor voltage ripple from 24% to 2.5%.