Protection Principle of DC Line Based on Fault Component of Line Mode Voltage with Current-Limiting Reactor

Abstract

High-resistance faults on the DC lines of multi-terminal VSC-HVDC grids lead to insufficient protection reliability, and the introduction of current-limiting strategies alters the system’s intrinsic fault characteristics, degrading protection performance. To address these issues, we propose a DC-line protection scheme that is immune to converter control strategies and highly tolerant to fault resistance. First, based on the grid topology, post-fault current paths are analyzed, and the fault characteristics produced solely by the fault-induced voltage source are identified. A sequential overlapping derivative transformation is then employed to magnify the discrepancy between internal and external faults, forming the core of the fault-identification criterion; the zero-mode component is used for pole selection. Finally, a four-terminal VSC-HVDC model is built in PSCAD/EMTDC version 4.6.2 for validation. Simulation results show that, after applying the current-limiting strategy, the characteristic quantity changes only marginally, and the proposed protection can reliably withstand fault resistances of up to 700 Ω.

1. Introduction

With the rapid growth of global energy demand, flexible DC transmission has gradually become an important means for high-voltage, large-capacity power transfer. Implemented with modular multilevel converters, flexible DC technology enables efficient power delivery while avoiding commutation failure and offering flexible reactive-power compensation and control capabilities [1,2,3]. It has been widely applied in cross-regional power transmission, renewable-energy integration, and submarine-cable projects [4,5].

However, in flexible DC systems, the short-circuit current characteristics triggered by line faults are complex and diverse. This complexity becomes more pronounced when current-limiting reactors are introduced [6]. This situation poses new challenges for existing protection schemes: on the one hand, the reactor alters the original fault-current path, rendering the fault features more intricate; on the other hand, its presence makes conventional protection criteria poorly suited to the new fault characteristics. Consequently, achieving efficient and reliable fault identification under the influence of a current-limiting reactor has become a key topic in flexible-DC protection research.

DC line-protection principles can be categorized into double-ended and single-ended schemes [7], where double-ended protection employs electrical quantities from both terminals of the transmission line and is commonly used as backup protection. Ref. [8] analyzed the magnitude and trend of the measured wave impedance in flexible DC systems, introducing Euclidean distance and similarity to distinguish internal from external faults. Ref. [9] addressed the case where a current-limiting reactor is installed at the converter outlet and boundary elements are missing; it constructed a protection principle based on the sign of the resistive part of the measured impedance, requiring no setting values and exhibiting certain noise immunity. Starting from the voltage-traveling-wave refraction coefficient, Ref. [10] proposed a longitudinal protection principle applicable under various boundary conditions, capable of withstanding a 500 Ω fault resistance. Ref. [11] used the waveform similarity of the fault current to construct a fault-identification criterion but neglected the influence of disturbances. Ref. [12] examined the relationship between line-fault current and the local DC-bus transient current, designing a double-ended principle based on their ratio that requires no data synchronization and places low demands on communication. Ref. [13] pointed out that introducing current-limiting control affects transient-current-based line protection and established a longitudinal scheme based on the differential current on both sides of the converter valves.

Single-ended protection relies solely on the electrical quantities at the local terminal, offering high operating speed and simple equipment, and is often used as primary protection [14]. Ref. [15] focused on the first-arriving traveling wave and employed a model-matching method to construct a line-protection principle that can tolerate a 500 Ω fault resistance. Ref. [16] detected faults using the sum of the voltages across the current-limiting reactors on the positive and negative poles, forming an integral criterion that affords rapid detection and strong noise immunity. Ref. [17] analyzed the transient-voltage characteristics of current-limiting reactors, revealing that the time for the mode-1 voltage to reach its peak differs significantly between internal and external faults, and constructed a corresponding criterion. Ref. [18] investigated the influencing factors of the voltage rate of change and proposed a fault-identification scheme based on this parameter, though its tolerance to fault resistance is limited. In general, existing single-ended schemes exhibit poor tolerance to high fault resistance, prompting many researchers to address this issue. Ref. [19] analyzed characteristic quantities under internal and external faults in DC distribution networks and constructed a new criterion by applying time-domain weighting to voltage and current signals within a specified window.

Building on the distinctive characteristics of fault current limiters (FCLs) in DC grids, researchers have recently advanced several protection-oriented methods: Ref. [20] proposes a self-adaptive over-current relay algorithm that accounts for the influence of FCLs. Fault detection is performed via a Z-score test, and the relay operating time is dynamically adjusted according to the ratio of post-fault to pre-fault current means. The scheme achieves high sensitivity and dependability without introducing additional delay, making it suitable for both conventional and smart-grid digital protection systems. Ref. [21] presents a coordinated current-limiting strategy that integrates modular multilevel converters (MMCs) with DC circuit-breakers. By harmonizing timing and parameter settings, the method enhances current-limiting capability in multi-terminal VSC-HVDC grids, extends the permissible protection operating window, and improves selectivity and adaptability across diverse operating scenarios. Through mathematical analysis, Ref. [22] quantifies switching and conduction losses in MMC-topology voltage-source converter (VSC) HVDC stations equipped with FCLs. Using the IEC 62751-1/-2 [23] guidelines and device-datasheet parameters, the authors develop a refined technique for precise power-loss assessment. Ref. [24] introduces a two-stage protection scheme that combines AC-side virtual-impedance control with DC-side current limiting. The coordinated approach strengthens the synergy between current limitation and fault discrimination in MMC half-bridge topologies within multi-terminal DC grids, achieving effective restriction of both AC and DC fault currents as confirmed by simulations. Ref. [25] formulates an impedance-setting method for FCLs based on MATLAB R2021b and ATP-EMTP co-simulation. Constraint conditions for the objective function are derived accurately, and a penalty-function technique transforms the constrained problem into an unconstrained one, which is then solved with a gravitational search algorithm. The approach delivers superior computational efficiency and optimization performance, underscoring its engineering value.

Ref. [26] proposes a control–protection coordination strategy founded on MMC active current-limiting control, which improves the interplay between protection and the current-limiting function and thus alleviates its adverse impact on protection; however, the scheme struggles to operate accurately under high-resistance or single-pole-to-ground faults. Ref. [27] examined the fault characteristics that arise under current-limiting control, assessed the feasibility of conventional traveling-wave relays, and advanced a pilot protection method based on similarity comparison. Focusing on the relationship between fault signatures and the electrical condition of the protected DC transmission line, the authors developed an accurate frequency-dependent line model and adopted a cross-wavelet-based similarity metric that can identify faults with high precision. However, this approach considers only the influence of current-limiting control at the local measurement terminal and does not analyze how remote-end limiting, particularly under fault resistance earthing, affects the similarity-based decision criterion.

Existing protection methods that rely on abrupt changes in DC current or voltage lose discriminatory power under high-impedance faults, and the distinction between internal and external faults becomes blurred, making it difficult to satisfy practical engineering demands for highly sensitive and selective protection. Most prior studies emphasize differences in amplitude or waveform between internal and external faults, yet under high-impedance internal faults, the misoperation rate rises sharply, undermining system security and the reliability of protection. The introduction of current-limiting strategies further complicates fault transients, rendering traditional protection features less stable and less discriminative. A protection principle that is insensitive to the influence of current-limiting reactors and adaptable to high-resistance faults is therefore urgently required.

To this end, this paper proposes a DC line-protection principle based on the fault component of the line-mode voltage across the current-limiting reactor. First, the reactor’s voltage response under fault conditions is analyzed, and the line-mode voltage component is selected as the characteristic indicator. A sequential overlapping derivative transform is then introduced to amplify the characteristic differences between internal and external faults, thereby improving the scheme’s adaptability under high-transition-resistance conditions. Finally, the effectiveness of the proposed principle is verified on a four-terminal flexible DC grid. Simulation results confirm that the method is insensitive to converter control strategies and reliably operates for short-circuit faults with fault resistances of up to 700 Ω.

The main contributions and innovations of this paper are as follows:

• A new DC line-protection scheme based on the fault component of the line-mode voltage across the current-limiting reactor is proposed, which is immune to the influence of current-limiting strategies and remains highly adaptive to high-impedance faults.
• A sequential overlapping derivative (SOD) transform is introduced to magnify the differences between internal and external fault features, thereby enhancing the sensitivity and reliability of the protection criterion under high-impedance conditions.
• A four-terminal VSC-HVDC grid model is built on the PSCAD/EMTDC version 4.6.2 platform, and extensive simulations covering various fault types, fault locations, and transition resistances are carried out to verify the proposed protection scheme.

2. Related Work

2.1. Structure of the DC Grid

Taking a four-terminal ring flexible DC grid as an example, all four converter stations adopt a symmetrical bipolar MMC configuration, and current-limiting reactors are installed at both ends of every DC transmission line. This study takes the Zhangbei ±500 kV true-bipolar MMC four-terminal flexible DC demonstration project as its prototype, which helps to ensure the engineering verifiability of the protection-algorithm evaluation. The topology is illustrated in Figure 1 [28], where Line 1–Line 4 denote the DC overhead transmission lines and P1–P8 indicate the measurement points at both line terminals; the various fault locations are marked in the figure. Using P1 as an example, (f₁, f₂, f₃) correspond to forward-direction internal faults at the sending end, midpoint, and receiving end, respectively; f₄ represents a reverse external fault; and (f₅, f₆) correspond to forward external faults.

In Figure 1, Z_c denotes the line surge wave impedance, which can be calculated using Equation (1); L denotes the current-limiting reactor.

$$Z_{\mathrm{c}}=\sqrt{{\displaystyle \frac{R_l+s{L}_l}{G_l+s{C}_l}}}$$

(1)

where G_l, C_l, R_l, and L_l represent the per-unit-length conductance, capacitance, resistance, and inductance of the line, respectively.

For a DC transmission line, coupling exists between the positive and negative conductors. The fault components of the two poles can be decoupled into line-mode and zero-mode components by Equation (2), where F₀ and F₁ are the zero-mode and line-mode quantities, and F_p and F_n are the fault components of the positive and negative poles, respectively. Because the line-mode wave velocity and the magnitude of the line-mode surge impedance change very little with frequency—and the line-mode wave propagates faster—the line-mode component is employed for all fault analyses in this paper.

$$\left[\begin{array}{c}{F}_0\\ F_1\end{array}\right]={\displaystyle \frac{1}{\sqrt{2}}}\left[\begin{array}{cc}1\hfill & \hfill 1\\ 1\hfill & \hfill -1\end{array}\right]\left[\begin{array}{c}{F}_{\mathrm{p}}\\ F_{\mathrm{n}}\end{array}\right]$$

(2)

2.2. Fault Characteristic Analysis of Current-Limiting Reactors

Taking a positive-pole-to-ground fault on Line 1 as an example, the analysis proceeds as follows. After the fault occurs, the resulting traveling wave propagates from the fault point toward the protection location; when this wave reaches the DC bus, the bus voltage drops and the current of MMC1 increases. With respect to protection point P1, the fault-current contribution of MMC1 can be measured, and, according to the substitution theorem, MMC1 can be modeled as a time-varying current source. At the same time, the voltage at the fault point collapses to zero, which is equivalent to introducing a step-voltage source at the fault location. On this basis, the fault-equivalent network of the four-terminal flexible DC grid is obtained, as shown in Figure 2.

The reactor voltage at protection point P1 can be regarded as the superposition of two contributions: the equivalent current source and the fault-induced voltage source. The following subsections analyze these two effects separately.

2.2.1. Influence of the Converter Equivalent Current Source on the Current-Limiting Reactor Voltage

An analysis is conducted of the fault-current component produced by converter MMC1. After the fault-induced traveling wave reaches the DC bus BUS1, the fault current rises rapidly and splits between Line 1 and Line 4.

To examine how the MMC1 fault current is apportioned between Lines 1 and 4, the complex-frequency (s) domain is employed. The current-propagation model in this domain is shown in Figure 3 [12].

In the figure, the current flowing out of MMC1 is denoted I_MMC1(s); the portion entering Line 1 is I_MMC11(s); and the portion entering Line 4 is I_MMC14(s).

Because the surge impedance of a transmission line is independent of its length, and identical conductors are generally used within the same DC grid, Lines 1 and 4 share the same surge impedance. Likewise, the current-limiting reactors at the sending ends have identical inductances. Hence, the currents in Lines 1 and 4 are equal, as expressed in Equation (3).

$$I_{\mathrm{M}\mathrm{M}\mathrm{C}11}\left(s\right)=I_{\mathrm{M}\mathrm{M}\mathrm{C}14}\left(s\right)$$

(3)

By applying the inverse Laplace transform, it follows that the two currents are equal in the time domain, each amounting to one half of the converter-bus current, as shown in Equation (4).

$$i_{\mathrm{M}\mathrm{M}\mathrm{C}11}\left(t\right)=i_{\mathrm{M}\mathrm{M}\mathrm{C}14}\left(t\right)=0.5i_{\mathrm{M}\mathrm{M}\mathrm{C}1}\left(t\right)$$

(4)

Accordingly, when the converter MMC1 acts alone, the voltage across the current-limiting reactor u_L,MMC1 is given by Equation (5).

$$u_{\mathrm{L}\mathrm{M}\mathrm{M}\mathrm{C}1}\left(t\right)=L{\displaystyle \frac{\mathrm{d}{i}_{\mathrm{M}\mathrm{M}\mathrm{C}11}\left(t\right)}{\mathrm{d}t}}=0.5L{\displaystyle \frac{\mathrm{d}{i}_{\mathrm{M}\mathrm{M}\mathrm{C}1}\left(t\right)}{\mathrm{d}t}}$$

(5)

During normal operation of the DC grid, the converter supplies a stable DC current with only minor fluctuations, and the voltage component across the current-limiting reactor is therefore nearly zero. After a fault occurs, the converter continues to discharge through the DC line toward the fault point, causing the fault current to increase and the reactor-voltage component to rise sharply.

2.2.2. Influence of the Equivalent Fault Voltage Source on the Current-Limiting Reactor Voltage

For a bipolar system, when a single-pole-to-ground fault or a bipolar fault occurs, the line-mode quantity differs only in magnitude, and the amplitude U_f1 of the line-mode traveling wave produced at the fault point can be expressed by Equation (6).

$$U_{\mathrm{f}1}=\left\{\begin{array}{l}{\displaystyle \frac{-\sqrt{2}{U}_{\mathrm{dc}}{Z}_{\mathrm{c}1}}{Z_{\mathrm{c}1}+Z_{\mathrm{c}0}+4R_{\mathrm{f}}}}\hspace{1em}Single-pole-to-ground fault\\ {\displaystyle \frac{-\sqrt{2}{U}_{\mathrm{dc}}{Z}_{\mathrm{c}1}}{Z_{\mathrm{c}1}+R_{\mathrm{f}}}}\hspace{1em}\hspace{1em} Bipolar short-circuit fault\end{array}\right.$$

(6)

In these expressions, Z_c1 and Z_c0 denote the line-mode and zero-mode surge impedances of the DC line, respectively; R_f is the fault resistance at the fault location; and U_DC is the rated DC voltage.

The traveling wave is initiated by the fault: when a short-circuit occurs on the DC line, a fault-generated wave is produced at the fault point and propagates toward both line ends. The initial wavefront at the fault point can be represented as a step signal, whose complex-frequency-domain expression is given in Equation (7).

$$U_{\mathrm{f}1}\left(s\right)={\displaystyle \frac{U_{\mathrm{f}1}}{s}}$$

(7)

For a fault that occurs on the DC line, the fault-induced traveling wave must propagate along the line to the protection location. The transfer function of the voltage traveling wave can be expressed by Equation (8).

$$A\left(s\right)={\displaystyle \frac{1-k_{\mathrm{a}}l}{1+s{t}_{\mathrm{a}}l}}{\mathrm{e}}^{-\frac{sl}{v}}$$

(8)

where v is the wave-propagation velocity; l is the propagation distance; K_a and t_a are the per-unit-length attenuation coefficient and time constant, respectively; (1 − K_al) represents the attenuation of the traveling wave along the line; (1 + st_al) describes the dispersion of the wave; and e^−sl/v accounts for the propagation delay along the line.

Since single-pole and bipolar faults differ only in magnitude, the following analysis is conducted using the single-pole fault as a representative case. When a fault occurs on Line 1, its equivalent Petersen circuit is shown in Figure 4.

For an internal fault, the frequency-domain expression of the fault component is given by Equation (9).

$$\Delta U_{\mathrm{L}\mathrm{f}1}\left(s\right)=2\Delta U_{\mathrm{f}1}\left(s\right)A\left(s\right){\displaystyle \frac{sL}{2\left(sL+Z_{\mathrm{c}1}\right)}}$$

(9)

Taking the inverse Laplace transform of (9) yields the time-domain expression shown in Equation (10).

$$\Delta u_{\mathrm{L}\mathrm{f}1}\left(t\right)\approx {\displaystyle \frac{\Delta u_{\mathrm{f}1}L\left(1-k_{a}l\right)}{L-Z_{\mathrm{c}1}{t}_{\mathrm{a}}l}}\left({\mathrm{e}}^{-{\displaystyle \frac{Z_{\mathrm{c}1}}{L}}t}-{\mathrm{e}}^{-{\displaystyle \frac{t}{t_{\mathrm{a}}l}}}\right)$$

(10)

In the case of an external fault, the fault-induced traveling wave must pass through an additional current-limiting reactor before reaching the protection location, and the first-arriving traveling wave can be expressed by Equation (11) [17].

$$U_{\mathrm{f}.\mathrm{out}}\left(s\right)={\displaystyle \frac{2Z_{\mathrm{c}1}}{2Z_{\mathrm{c}1}+sL}}{U}_{\mathrm{f}1}\left(s\right)$$

(11)

For an external fault, the line-mode fault component of the voltage across the current-limiting reactor is given by Equation (12).

$$\Delta U_{\mathrm{L}\mathrm{f}1}\left(s\right)=2\Delta U_{\mathrm{f}.\mathrm{out}}\left(s\right)A\left(s\right){\displaystyle \frac{s{L}_{\mathrm{dc}}}{2\left(s{L}_{\mathrm{dc}}+Z_{\mathrm{c}1}\right)}}$$

(12)

Taking the inverse Laplace transform of (11) yields the time-domain expression shown in Equation (13).

$$\Delta u_{\mathrm{L}\mathrm{f}1}\left(t\right)\approx 2\Delta u_{\mathrm{f}1}\left(1-k_{\mathrm{a}}l\right)\left({\mathrm{e}}^{-{\displaystyle \frac{Z_{\mathrm{c}1}}{L}}t}-{\mathrm{e}}^{-{\displaystyle \frac{2Z_{\mathrm{c}1}}{L}}t}\right)$$

(13)

In summary, for an external fault, the traveling wave has to traverse an additional current-limiting reactor and a longer distance before it reaches the protection location, so the steepness of its front is markedly reduced and the resulting voltage change across the reactor is far smaller than for an internal fault. Therefore, the line-mode fault component of the reactor voltage can accurately distinguish between internal and external faults.

2.2.3. Extraction of the Fault Component of the Line-Mode Voltage Across the Current-Limiting Reactor

The procedure for obtaining Δu_Lf1 is as follows. First, measure the converter-outlet current according to Equation (5); the voltage across the current-limiting reactor contributed by the equivalent current source can then be obtained. In the calculation, the derivative is replaced by the difference between two sampling points [29], as shown in Equation (14).

$${\displaystyle \frac{\mathrm{d}{i}_{\mathrm{M}\mathrm{M}\mathrm{C}1}\left(t\right)}{\mathrm{d}t}}={\displaystyle \frac{i_{\mathrm{M}\mathrm{M}\mathrm{C}1}\left(m\right)-i_{\mathrm{M}\mathrm{M}\mathrm{C}1}\left(m-1\right)}{T_{\mathrm{s}}}}$$

(14)

In Equation (13), i_MMC1(m) denotes the m-th sample of i_MMC1, and T_s is the sampling interval.

Subtracting the voltage produced by the equivalent current source from the measured reactor voltage yields the reactor voltage due solely to the fault-induced voltage source. Substituting this quantity into Equation (2), the pole–mode transformation provides the required line-mode fault component of the reactor voltage, thus completing the construction of the protection scheme.

2.3. Changes in Electrical-Quantity Characteristics Induced by the Current-Limiting Strategy and Their Impact on Conventional Protection

Under normal operating conditions, the three-phase bridge arms of an MMC converter remain balanced: each phase has the same number of sub-modules inserted in its upper and lower arms, thereby keeping the DC voltage equalized. The numbers of inserted sub-modules in the upper and lower arms are determined by the Nearest Level Modulation strategy as follows.

$$\left\{\begin{array}{l}{N}_{j\mathrm{p}}=\mathrm{round}\left({\displaystyle \frac{V_{\mathrm{r}\mathrm{e}\mathrm{f}j\mathrm{p}}}{V_{\mathrm{cn}}}}\right)\\ N_{j\mathrm{n}}=\mathrm{round}\left({\displaystyle \frac{V_{\mathrm{r}\mathrm{e}\mathrm{f}j\mathrm{n}}}{V_{\mathrm{cn}}}}\right)\end{array}\right.\hspace{1em}(j=\mathrm{a},\mathrm{b},\mathrm{c})$$

(15)

$$\left\{\begin{array}{c}{V}_{\mathrm{r}\mathrm{e}\mathrm{f}j\mathrm{p}}={\displaystyle \frac{1}{2}}{U}_{\mathrm{dc}}-V_{\mathrm{r}\mathrm{e}\mathrm{f}j}-u_{\mathrm{c}\mathrm{i}\mathrm{r}\mathrm{d}j}\\ V_{\mathrm{r}\mathrm{e}\mathrm{f}j\mathrm{n}}={\displaystyle \frac{1}{2}}{U}_{\mathrm{dc}}+V_{\mathrm{r}\mathrm{e}\mathrm{f}j}-u_{\mathrm{c}\mathrm{i}\mathrm{r}\mathrm{d}j}\end{array}\right.\hspace{1em}(j=\mathrm{a},\mathrm{b},\mathrm{c})$$

(16)

$$N_1=N_{j\mathrm{p}}+N_{j\mathrm{n}}=\mathrm{round}\left({\displaystyle \frac{U_{\mathrm{dc}}-2u_{\mathrm{c}\mathrm{i}\mathrm{r}\mathrm{d}j}}{V_{\mathrm{cn}}}}\right)$$

(17)

where N_jp and N_jn denote the numbers of sub-modules inserted in the upper and lower arms of phase j, respectively; V_refjp and V_refjn are the corresponding arm-voltage references; V_cn is the rated capacitor voltage of a single sub-module; U_DC represents the DC-link voltage of the converter; V_refj is the AC reference voltage for phase j; and u_cirdj denotes the circulating-current suppression voltage of phase j.

The DC fault current that arises on the DC side after a fault occurs but before the converter station blocks is governed primarily by the discharge of the sub-module capacitors. Equation (17) shows that the number of sub-modules inserted by the converter depends on the DC-side voltage, the rated voltage of an individual sub-module, and the circulating-current voltage. Since the loop voltage has only a minor influence on the required number of sub-modules, it can be neglected in the calculation; therefore, Equation (17) can be simplified as follows:

$$N_1=\mathrm{round}\left({\displaystyle \frac{U_{\mathrm{dc}}}{V_{\mathrm{cn}}}}\right)$$

(18)

The magnitude of the DC short-circuit current is predominantly determined by the pre-fault DC-link voltage, the initial fault current, and the equivalent impedance of the fault loop. Because the latter two parameters are dictated by the system’s operating condition and inherent design, and are thus difficult to alter in practice, the most practical lever for curbing both the rate of rise and the peak value of the fault current is to modulate the MMC’s DC-side voltage. As shown in Equation (18), lowering the DC voltage can be achieved by decreasing the number of sub-modules inserted in each converter arm. Accordingly, an active current-limiting factor K is introduced to implement an active current-limiting control strategy. With this additional control loop, the DC-link voltage is modified as expressed in Equation (19).

$$U_{\mathrm{dck}}=K{N}_1{V}_{\mathrm{cn}}$$

(19)

Current-limiting strategies pose two main challenges to conventional protection: once the MMC’s active current-limiting control is triggered, both the amplitude and rate of rise of the DC short-circuit current are markedly reduced, so traditional algorithms that rely on fixed current magnitude or di/dt thresholds may fail. Moreover, in multi-terminal VSC-HVDC schemes, the considerable line length introduces propagation delays, and if a fault occurs far from the midpoint, the two current limiters engage at different times; when the ground fault includes fault resistance, the nearer limiter operates first, producing an extra current increment at the remote terminal, distorting the fault-current waveform and jeopardizing protection methods based on waveform similarity.

2.4. Theory of the SOD Transform

The sequential overlapping difference (SOD) transform, also known as the second-order difference transform, is a signal-processing technique often employed for fault-feature extraction. Its mathematical foundation lies in applying successive finite-difference operations to a signal within partially overlapping sliding windows. By taking the k-th-order difference of the data, SOD highlights higher-order characteristics, thereby exposing subtle variations and abnormal patterns that may precede or accompany a fault.

• Increasing the order of the SOD operation accentuates trends and “acceleration” in the signal, making the method more sensitive to weak transients. A third-order SOD, in particular, has been found effective for power-system fault analysis. The main advantages of SOD in fault detection and feature extraction are as follows.
• Enhanced high-order features. Third-order differencing captures the rate of change in a signal’s slope (i.e., its acceleration). When a fault develops, numerous precursors or anomalous behaviors commonly manifest as rapid or accelerating fluctuations in the measured signal. The SOD transform is inherently more sensitive to these patterns than simple first-order differencing, allowing it to capture subtle high-order dynamics that precede a failure event.
• Noise suppression. Random noise in practical measurements is typically low-order and less correlated. Higher-order SOD acts as a high-pass operation that smooths out such noise while retaining genuine, fault-related signal variations. This improves the precision of feature extraction and reduces noise interference in the subsequent analysis.
• Emphasis on non-stationary characteristics. Fault signals are intrinsically non-stationary: their statistical properties evolve over time. By emphasizing the signal’s acceleration, the SOD transform captures transient, non-stationary variations at the instant of fault inception. These fine-scale changes are often imperceptible to first-order differences, but become prominent under SOD.
• Improved fault-identification accuracy. In power-system protection, faults are usually indicated by abrupt or impulsive changes. SOD highlights these discontinuities, yielding more discriminative features for classification and significantly enhancing the accuracy of fault recognition.

In summary, the SOD transform provides a mathematically rigorous yet computationally lightweight means of amplifying fault-related signatures, suppressing noise, and improving the detectability for high-resistance and other challenging fault scenarios.

From the analysis in Section 1, the line-mode voltage fault component of the current-limiting reactor exhibits different fluctuation levels for internal and external faults. Because the sequential overlapping derivative (SOD) transform accentuates abrupt or rapidly changing portions of a signal and suppresses steady parts, SOD is adopted as the feature quantity to distinguish internal from external faults. The k-th-order SOD transform is defined as Equation (20):

$$S_k\left(n\right)={{\displaystyle \sum _{j=1}^{k+1}\left(-1\right)}}^{j+1}{\left(c_j\right)}_{k}Q\left(n-j+1\right)$$

(20)

In the expression, k is the order of the difference; S_k(n) is the k-th-order difference of the corresponding signal; (c_j)k are the SOD transform coefficients, whose values must conform to the rules specified in Equations (21)–(24); Q(n) is the original fault signal, which in this paper refers to the fault component of the line-mode voltage across the current-limiting reactor; n is the instantaneous sample index and must be at least k + 1.

• The first and last coefficients of the SOD transform are both equal to 1:

$${\left(c_1\right)}_k={\left(c_{k+1}\right)}_k=1$$

(21)

2.

The second coefficient of the SOD transform is equal to the order of the transform.

$${\left(c_2\right)}_k=k$$

(22)

3.

The remaining coefficients of the SOD transform are computed by the following expression:

$${\left(c_j\right)}_k={\left(c_j\right)}_{k-1}+{\left(c_{j-1}\right)}_{k-1}$$

(23)

4.

The sum of all the SOD transform coefficients is zero:

$${{\displaystyle \sum \left(-1\right)}}^{j+1}{\left(c_j\right)}_k=0$$

(24)

Accordingly, the first-through fourth-order SOD calculation formulas are given in Equation (25).

$$\left\{\begin{array}{l}{S}_1\left(n\right)=Q\left(n\right)-Q\left(n-1\right)\\ S_2\left(n\right)=Q\left(n\right)-2Q\left(n-1\right)+Q\left(n-2\right)\\ S_3\left(n\right)=Q\left(n\right)-3Q\left(n-1\right)+3Q\left(n-2\right)-Q\left(n-3\right)\\ S_4\left(n\right)=Q\left(n\right)-4Q\left(n-1\right)+6Q\left(n-2\right)-4Q\left(n-3\right)+Q\left(n-4\right)\end{array}\right.$$

(25)

Through the SOD transform, local variations in the signal can be captured more accurately. When a fault occurs, the line-mode voltage across the current-limiting reactor usually exhibits pronounced fluctuations and abrupt transitions near the fault point. Compared with conventional finite-difference algorithms, SOD evaluates the variation characteristics of the signal repeatedly in the overlapping-calculation process, precisely capturing these transitions and thereby highlighting the difference in the fault component. In the following, this method is applied to the line-mode fault component of the reactor voltage for both internal and external faults, and the signals before and after the transform are compared and analyzed.

Figure 5 shows the variation in the line-mode voltage fault component across the current-limiting reactor during an internal fault, along with the corresponding signal after the SOD transform. Under an internal fault, the initial traveling wave generated at the fault point propagates along the line to the reactor, and the line-mode voltage rises rapidly. After the SOD transform, the signal varies more sharply and its peak value increases, meaning that the internal-fault characteristics are magnified.

Figure 6 depicts the line-mode voltage fault component across the current-limiting reactor during an external fault, together with the corresponding signal after the SOD transform. Because the initial traveling wave must traverse not only the entire line but also an additional current-limiting reactor before reaching the protected reactor, the line-mode voltage rises much more slowly. After the SOD transform, the signal varies less sharply and its peak value decreases, so the external-fault features are compressed.

The foregoing analysis demonstrates that the SOD transform enlarges the features of internal faults while compressing those of external faults, offering a clear advantage. It can be foreseen that, as the fault resistance increases for an internal fault, the internal-fault features will diminish and may become indistinguishable from those of an external fault. The SOD transform resolves this issue, endowing the protection scheme with a higher tolerance to fault resistance.

2.5. Selection of the SOD Transform Order

To determine the optimal order of the SOD transform, an internal metallic line fault is selected as the study case, and SOD transforms of different orders are applied; the resulting waveforms are shown in Figure 7.

From Figure 7 and SOD theory, it can be concluded that as the order k increases, the transformed signal becomes steeper. However, the SOD expression also grows more complex with higher orders, increasing computational load and time cost. Verification shows that a third-order SOD transform already discriminates accurately between an internal high-resistance fault and the most severe external fault, while the formula remains relatively simple. Therefore, k = 3 is chosen for the subsequent analysis.

3. Line-Protection Principle Based on the Line-Mode Voltage Across the Current-Limiting Reactor

This section presents the protection scheme in three parts—starting criterion, fault-identification criterion, and pole-selection criterion—and then provides the overall flowchart.

3.1. Starting Criterion

During normal operation, both the DC-line current and the MMC DC-terminal current fluctuate only slightly, so the measured Δu_Lf1 is negligible. Once a fault occurs, the line-mode fault component of the reactor voltage rises rapidly under the action of the traveling wave. Hence, the magnitude of Δu_Lf1 can be used to determine whether a fault has taken place; the starting criterion is defined by Equation (26).

$$\Delta u_{\mathrm{L}\mathrm{f}1}>{\Delta }_1$$

(26)

In Equation (26), Δ₁ is the threshold of the starting criterion. Its value should lie above the maximum Δu_Lf1 observed under normal operation; here Δ₁ = 30 kV. Because the line-mode fault component of the reactor voltage is negative for reverse external faults, the starting criterion simultaneously serves as a directional criterion, distinguishing forward faults from reverse faults.

3.2. Fault-Identification Criterion

According to the previous analysis, the current-limiting reactors at both ends of the DC line form natural electrical boundaries. For an external fault, the fault-induced traveling wave must cross this additional boundary, so its amplitude and front steepness are lower than in an internal fault. The initial variations of the line-mode fault component across the reactor, therefore, differ markedly between internal and external faults. By applying the SOD transform, these differences can be further magnified, thereby enhancing the scheme’s tolerance to fault resistance.

We apply a third-order SOD transform to the line-mode component of the fault voltage to obtain S₃(Δu_Lf1), and define X as the maximum absolute value of S₃(Δu_Lf1), as expressed in Equation (27). When Equation (26) is met, a forward fault is determined. Subsequently, the magnitude of X is used to distinguish between internal and external faults, as specified by Equation (28): if Equation (28) holds, the fault is internal; otherwise, it is external.

$$X=\max \left|S_3\left(\Delta u_{\mathrm{L}\mathrm{f}1}\right)\right|$$

(27)

$$X>X_{\mathrm{set}}$$

(28)

In the expression, X_set is the setting value for the fault-identification criterion, and its value can be determined using Equation (29).

$$X_{\mathrm{set}}=K_{\mathrm{rel}}{X}_{\mathrm{out}.\max }$$

(29)

In the equation, K_rel is the reliability factor, set to 1.35, and X_out.max is the maximum value of the third-order SOD transform under external-fault conditions. Simulation analysis shows that the most severe external fault yields X_out.max = 62.7 kV; therefore, the protection threshold for the fault-identification criterion is chosen as X_set = 85 kV.

3.3. Pole-Selection Criterion

For a VSC-HVDC system operating in true bipolar mode, the healthy pole can continue to carry power during a single-pole fault. A rapid pole-selection criterion is therefore required to identify the faulted pole promptly and keep the system in service. In this study, fault-pole discrimination is performed on the basis of the zero-mode voltage, with the associated data-window length set equal to that employed for the pole-selection criterion. The zero-mode component is defined as

$$\Delta F_0={\displaystyle \frac{\Delta F_{\mathrm{p}}+\Delta F_{\mathrm{n}}}{\sqrt{2}}}$$

(30)

In the equation, Δ denotes the fault-induced component; F represents the voltage or current; subscripts p and n correspond to the positive and negative poles, respectively; and subscript 0 designates the zero-mode component.

Analytical results show that the zero-mode component of a DC link exhibits distinct signatures under different fault states. Because this component reflects the symmetry or asymmetry of the DC-link voltages, it provides a convenient indicator for identifying fault types:

• Positive-pole-to-ground fault. The positive-pole fault component (ΔF_p) is approximately zero, and the resulting zero-mode voltage is typically negative.
• Negative-pole-to-ground fault. In this case, ΔF_n ≈ 0, and the zero-mode voltage becomes positive.
• Pole-to-pole fault. As a symmetrical fault, it produces ΔF_p ≈ ΔF_n ≈ 0, so the zero-mode voltage remains close to zero.

A threshold Δ₂ is therefore set according to the largest unbalanced voltage observed under a worst-case bipolar fault. The pole-selection factor Y and the associated decision logic are defined by Equation (31) and Equation (32), respectively:

$$Y={\displaystyle \frac{1}{\mathrm{N}}}{\displaystyle \sum _{n=1}^{\mathrm{N}}\Delta u_{\mathrm{L}\mathrm{f}0}\left(n\right)}$$

(31)

$$\left\{\begin{array}{l}Y\le -{\Delta }_2\hspace{1em}\hspace{1em}\hspace{1em}Negative-pole fault\\ -{\Delta }_2<Y<{\Delta }_2\hspace{1em}Bipolar fault\\ Y\ge {\Delta }_2\hspace{1em}\hspace{1em}\hspace{1em} Positive-pole fault\end{array}\right.$$

(32)

In the expression, Δ₂ is the threshold of the pole-selection criterion (Δ₂ > 0). Its value is set according to the maximum unbalanced voltage that may arise during a bipolar fault in the flexible DC system. To ensure reliability and leave an adequate margin, Δ₂ is chosen as 25 kV in this study.

3.4. Overall Protection Scheme

The complete protection scheme is illustrated in Figure 8. Once the protection is triggered, an algorithmic data window of 0.4 ms is applied. Equation (28) is used to identify whether the fault is internal or external, and Equation (32) is then employed to select the faulted pole rapidly.

As illustrated in Figure 8, the proposed protection scheme consists of four functional blocks: an electrical-quantity acquisition module, a protection initiation module, a fault identification module, and a pole-selection module. The acquisition module continuously monitors the line’s critical electrical quantities and sends them to the initiation module to assess the system state. Immediately after a fault is detected, the first 0.4 ms window of voltage data is captured for analysis; the line-mode voltage components at both ends of the current-limiting reactor are extracted and processed with the sequential overlapping derivative (SOD) transform to magnify the amplitude difference between internal and external faults. The fault identification module then pinpoints the fault location, while the pole-selection module determines the fault type. If the fault is internal, the protection device acts swiftly to isolate or clear it. Through this coordinated sequence of steps, the proposed scheme can effectively curb fault propagation and maintain the safe and stable operation of the system.

4. Simulation Verification

A PSCAD/EMTDC model of the flexible-DC grid shown in Figure 1 is constructed, with current-limiting reactors installed at both ends of each line. The system parameters follow those of the Zhangbei flexible-DC project; key values are listed in

Table 1. Four-terminal DC grid parameters.

System Parameters	Value
Line length/km	Line1: 184.4
	Line2: 101
	Line3: 131.1
	Line4: 78.3
DC voltage/kV	±500
Number of converter sub-modules	200
Sub-module capacitance/mF	MMC1: 15
	MMC2: 10
	MMC3: 15
	MMC4: 15
Arm inductance/mH	MMC1: 100
	MMC2: 100
	MMC3: 50
	MMC4: 50
Current-limiting reactor inductance/mH	150

[28]. Figure 9 illustrates the frequency-dependent parameter model of the DC overhead line, together with the associated tower model. This study adopts a comprehensive fault-modeling approach that captures the dynamic and nonlinear behavior of high-impedance faults in DC systems, rather than representing an HIF by simply assigning a large fault-resistance value. The protection data-window length is set to 0.4 ms. The starting-criterion threshold is Δ₁ = 30 kV, and the pole-selection threshold is Δ₂ = 25 kV.

The rationale for selecting a 0.4 ms data window—along with an evaluation of whether this duration remains adequate under different fault types, network configurations, and noise conditions—is presented below.

First, because the protection decision is made exclusively based on the initial traveling-wave signature following fault inception, the shorter the data window, the faster the relay can operate. In our simulations, a 25 kHz sampling rate is employed, so a 0.4 ms window corresponds to ten samples, ample to capture the initial steep front of the traveling wave and to perform the third-order SOD calculation. The results demonstrate that this ultra-short window still reliably extracts the incipient transient signature of the fault and fully meets the stringent speed requirements for primary protection in flexible DC systems.

Second, the sufficiency of the 0.4 ms window under diverse operating conditions.

• Fault-type variation. For positive-pole-to-ground, negative-pole-to-ground, and bipole short-circuit faults, the dominant characteristics of the incipient traveling wave are concentrated within an exceedingly short interval immediately after fault inception. Upon detecting the wave front, the relay captures a 0.4 ms record and evaluates the protection criterion; this interval completely encompasses both the steep front and the first peak of the wave. Consequently, whether the fault is monopolar or bipolar, the 0.4 ms window preserves all critical information.
• Network-configuration variation. The simulations are conducted on the four-terminal ±500 kV Zhangbei MMC-HVDC test system, whose longest line is ~184 km. Even for internal faults located at the far end, the traveling wave reaches the relay in only a few hundred microseconds. The protection criterion is triggered at that moment, and the subsequent 0.4 ms slice still contains the principal waveform variations, rendering it adequate for any internal fault within the present topology. If the network were scaled up with longer lines, the window could be proportionally extended to maintain full coverage of the initial wavefront.
• Noise conditions. In practical environments, a shorter window diminishes the influence of power-frequency oscillations and low-frequency disturbances, albeit with limited averaging of stochastic noise. The scheme addresses this by adopting a relatively high pick-up threshold (Δ₁ = 30 kV) that exceeds noise-induced fluctuations, and employing the SOD transform, whose differential nature accentuates abrupt changes while naturally attenuating high-frequency noise. A reliability factor, Krel, is further introduced to accommodate residual uncertainty. Simulation tests with superimposed noise confirm stable relay behavior, demonstrating that the 0.4 ms window is sufficiently robust.

In summary, both simulation results and theoretical analysis confirm that the chosen window length is adequate and effective across different fault types, network topologies, and typical noise conditions.

For ease of analysis, the protection at P1 is taken as the example to verify the scheme’s performance. All line faults are set to occur at 2 s. During simulation validation, the protection sampling frequency was set to 100 kHz [30], which is sufficient to effectively capture the key transient features.

4.1. Impact of Current-Limiting Strategy on Protection

The introduction of current-limiting control strategies alters the current flowing through the DC line and the DC bus, which in turn affects the voltage across the current-limiting reactor. However, the fault component of the line-mode voltage across the current-limiting reactor, denoted as Δu_Lf1 and used in this study, is theoretically unaffected by the current contributed by the MMC converter. Therefore, its fault characteristics are inherently immune to the influence of the control strategy. To verify this, a metallic fault at the midpoint of the internal line is selected as a test case, and simulations are performed to evaluate the effect of the current-limiting strategy on this protection feature.

As shown in Figure 10, after the line fault occurs and the fault-induced traveling wave reaches the protection location, Δu_Lf1 rises rapidly from zero and then gradually decays. Comparing the protection feature under scenarios with and without current-limiting control, the maximum difference in the early fault stage is only 0.824 kV, accounting for just 0.43%. This discrepancy is negligible, indicating that the protection feature Δu_Lf1 is effectively unaffected by the control strategy.

4.2. Verification of the Starting Criterion

Taking a positive-pole-to-ground fault occurring at the line terminal (f₃) as an example, the grounding resistance is set to 0 Ω and 700 Ω, respectively. The variation in the line-mode fault component across the current-limiting reactor under these conditions is shown in Figure 11.

As seen in Figure 11, under normal operating conditions of the DC system, Δu_Lf1 remains close to zero, and the protection does not operate. After the fault occurs, the line-mode fault component rises sharply as the traveling wave reaches the protection measurement point. Even under a high-resistance fault of up to 700 Ω, the voltage-division effect introduced by the fault resistance lengthens the rise time of the line-mode voltage fault component; nevertheless, this component still rapidly surpasses the threshold of the starting criterion, indicating that the criterion is both reliable and effective. Setting the maximum fault resistance to 700 Ω is consistent with the design envelope of the Zhangbei project and similar installations, and both simulation evidence and published data confirm that the proposed criterion remains reliable and retains a sufficient operating margin at this resistance level.

The performance of the fault-starting criterion under other conditions is summarized in

Table 2. Verification of the operation of the starting criterion and pole-selection criterion.

Fault Location and Type	Fault Resistance/Ω	ΔuLf1/kV	Starting Time/s
Positive-pole-to-ground fault at f1	0	>30 kV	2.0001
	400	>30 kV
	700	>30 kV
Bipolar fault at f2	0	>30 kV	2.0003
	400	>30 kV
	700	>30 kV
Negative-pole-to-ground fault at f3	0	>30 kV	2.0006
	400	>30 kV
	700	>30 kV
Bipolar fault at f4	0	<0 kV	—

.

As shown in Table 2, under internal fault conditions, the protection is successfully triggered in all cases. When a reverse external fault occurs, the value corresponding to the starting criterion is negative, and the protection reliably refrains from operating. Therefore, the subsequent simulations focus exclusively on forward internal and external fault scenarios.

4.3. Internal Fault Simulation Analysis

To verify the performance of the proposed protection scheme under various internal fault conditions, different fault locations and fault types are simulated on Line 1, including positive-pole-to-ground, bipolar, and negative-pole-to-ground faults. The fault resistance is set to 0 Ω, 400 Ω, and 700 Ω, respectively. The simulation results for protection point P1 are shown in

Table 3. Simulation analysis of internal fault.

Fault Type	Fault Location	Transition Resistance/Ω	Starting Time/s	X/kV	Y/kV	Identification Result
Positive-Pole-to-Ground Fault	f1	0	2.0001	338.97	190.40	Internal Positive Pole
		400		154.19	73.79	Internal Positive Pole
		700		109.20	50.27	Internal Positive Pole
	f2	0	2.0003	684.14	225.14	Internal Positive Pole
		400		208.56	71.37	Internal Positive Pole
		700		137.15	47.26	Internal Positive Pole
	f3	0	2.0006	313.44	169.69	Internal Positive Pole
		400		142.70	67.65	Internal Positive Pole
		700		101.36	46.29	Internal Positive Pole
Negative-Pole-to-Ground Fault	f1	0	2.0001	339.06	−190.34	Internal Negative Pole
		400		154.25	−73.71	Internal Negative Pole
		700		109.26	−50.29	Internal Negative Pole
	f2	0	2.0003	684.44	−225.08	Internal Negative Pole
		400		208.41	−71.25	Internal Negative Pole
		700		137.28	−47.14	Internal Negative Pole
	f3	0	2.0006	314.05	−169.68	Internal Negative Pole
		400		142.79	−67.52	Internal Negative Pole
		700		101.55	−46.24	Internal Negative Pole
Bipolar Fault	f1	0	2.0001	849.55	−0.061	Internal Bipolar
		400		486.06	−0.240	Internal Bipolar
		700		367.80	−0.097	Internal Bipolar
	f2	0	2.0003	1752.76	0.009	Internal Bipolar
		400		712.04	−0.020	Internal Bipolar
		700		492.63	0.016	Internal Bipolar
	f3	0	2.0006	805.42	−0.038	Internal Bipolar
		400		454.22	−0.043	Internal Bipolar
		700		342.23	−0.045	Internal Bipolar

.

As shown in Table 3, under various internal fault scenarios with different fault resistances, both the fault-identification and pole-selection criteria operate correctly, and no cases of protection failure are observed. The fault-identification index X decreases as the fault resistance increases; however, even when the resistance reaches 700 Ω, the protection scheme successfully identifies the fault, demonstrating strong tolerance to high fault resistance.

4.4. External Fault Simulation Analysis

To evaluate the performance of the proposed protection scheme under external fault conditions, simulations are conducted with different fault types and locations in the forward external zone (f₅ and f₆). Positive-pole-to-ground, bipolar, and negative-pole-to-ground faults are simulated, with fault resistances set to 0 Ω, 400 Ω, and 700 Ω, respectively. The simulation results are summarized in

Table 4. Simulation analysis of external fault.

Fault Type	Fault Location	Fault Resistance/Ω	Protection Start Status	X/kV	Identification Result
Positive-Pole-to-Ground Fault	f5	0	Start	31.86	External Fault
		400	Start	10.44	External Fault
		700	No Start	—	External Fault
	f6	0	Start	2.77	External Fault
		400	No Start	—	External Fault
		700	No Start	—	External Fault
Negative-Pole-to-Ground Fault	f5	0	Start	31.57	External Fault
		400	Start	10.54	External Fault
		700	No Start	—	External Fault
	f6	0	Start	3.06	External Fault
		400	No Start	—	External Fault
		700	No Start	—	External Fault
Bipolar Fault	f5	0	Start	62.71	External Fault
		400	Start	58.59	External Fault
		700	Start	54.63	External Fault
	f6	0	Start	23.88	External Fault
		400	Start	2.41	External Fault
		700	No Start	—	External Fault

.

As shown in Table 4, under various external fault scenarios with different fault resistances, the fault-identification criterion performs effectively. Even in the most severe case—a metallic bipolar external fault—the calculated X value still shows a significant margin from the protection threshold, and no maloperation occurs.

4.5. Simulation Analysis Under Different Current-Limiting Reactor Sizes

To verify the adaptability of the proposed protection scheme to variations in the inductance of current-limiting reactors, simulations are conducted using different inductance values. The protection performance for both internal and external faults of various types is illustrated in Figure 5.

As shown in

Table 5. Protection simulation results under fault conditions with different sizes of current-limiting reactors.

Fault Type	Current-Limiting Reactor Inductance Value/mH	Transition Resistance/Ω	X/kV	Y/kV	Identification Result
Positive-Pole-to-Ground Fault	100	0	595.51	126.94	Internal Positive-Pole
		700	120.02	26.72	Internal Positive-Pole
	150	0	684.14	225.14	Internal Positive-Pole
		700	137.15	47.26	Internal Positive-Pole
	200	0	745.30	294.74	Internal Positive-Pole
		700	149.49	61.81	Internal Positive-Pole
Negative-Pole-to-Ground Fault	100	0	1528	−0.058	Internal Bipolar
		700	430.35	−0.017	Internal Bipolar
	150	0	1752	0.009	Internal Bipolar
		700	492.63	0.016	Internal Bipolar
	200	0	1909.9	0.058	Internal Bipolar
		700	536.13	0.094	Internal Bipolar
Bipolar Fault	100	0	83.40	—	External Fault
	150	0	62.71	—	External Fault
	200	0	50.50	—	External Fault

, when the inductance of the current-limiting reactor varies between 100 mH and 200 mH, the protection scheme can correctly identify faults in all cases. Simulation results demonstrate that the proposed scheme exhibits good adaptability to different reactances.

4.6. Simulation Analysis Under Different Noise Levels

As indicated in

Table 6. Comparison results between the proposed protection scheme and conventional traveling-wave protection.

Fault Type	Transition Resistance/Ω	Start-up Time of Conventional Traveling-Wave Protection/s	Start-up Time of the Proposed Protection Scheme/s	Conventional Traveling-Wave Protection	Proposed Protection Scheme
f2 Positive-Pole-to-Ground Fault	0	2.0003	2.0001	Start	Start
	400	/	2.0003	No Start	Start
	700	/	2.0006	No Start	Start
f2 Negative-Pole-to-Ground Fault	0	2.0003	2.0001	Start	Start
	400	/	2.0003	No Start	Start
	700	/	2.0006	No Start	Start
f2 Bipolar Fault	0	2.0003	2.0001	Start	Start
	400	/	2.0003	No Start	Start
	700	/	2.0006	No Start	Start

, the proposed protection scheme capitalizes on the initial traveling-wave features of the fault, achieving an exceptionally fast operating time that meets or surpasses the speed requirements for primary protection in flexible HVDC systems; by contrast, the conventional traveling-wave method responds noticeably more slowly under identical test conditions. In terms of dependability and fault-resistance tolerance, the proposed scheme remains secure for internal faults with fault resistances as high as 700 Ω, whereas the conventional counterpart fails to operate reliably once the resistance approaches 400 Ω. Across all simulated external-fault scenarios, the proposed algorithm exhibits no misoperation, demonstrating outstanding selectivity and security, while the traditional solution performs comparatively poorly in both reliability and resistance tolerance. Given the marked advantages in speed and reliability already achieved, future work will focus on further reducing the operating time and misoperation rate under more complex network conditions.

5. Discuss

5.1. Performance of the Proposed Single-Ended Scheme Under Practical Operating Conditions

Regarding immunity to sampling noise, the protection criteria employ deliberately high thresholds and target only the pronounced voltage transients generated at fault inception. Specifically, the pick-up threshold is set at Δ₁ = 30 kV and the fault-identification threshold at X_set = 85 kV, values well above the amplitude of normal-operation noise and minor fluctuations. Moreover, the third-order SOD transform inherently attenuates low-level stationary noise. When 30 dB Gaussian white noise is superimposed in the simulation, the transient fault features still rise conspicuously above the noise floor, enabling reliable discrimination.

Since the scheme is single-ended and does not rely on communication, it is inherently immune to delays caused by remote data transfer. Any delay in acquiring or processing local measurements will inevitably erode the rapid response of the protection scheme.

The voltage across the current-limiting reactor may be subject to sensor range and accuracy constraints; nevertheless, the proposed scheme exhibits a high degree of tolerance to such measurement limitations. Under normal conditions, the line-mode voltage fault component Δu_Lf1 is nearly zero, so any small sensor error leaves the calculated feature X far below the actuation threshold and cannot trigger a false trip. During a fault, by contrast, the line-mode voltage changes dramatically, dwarfing any quantization error. To further compensate for instrumental inaccuracies and numerical discretization, a reliability coefficient is incorporated into the threshold settings.

In summary, the proposed protection maintains solid performance and offers appreciable immunity to sampling noise, signal delay, and measurement-precision limitations. With appropriate hardware selection and parameter tuning in the field, these practical factors can be kept from undermining protection reliability.

5.2. Relevant Quantitative Reliability Metrics

Fault-identification accuracy: In all simulations, the proposed relay achieved 100% accuracy, tripping for every internal fault and rejecting every external fault. Table 3 lists internal-fault cases on Line 1 that span multiple locations, fault types, and fault resistances; the relay operated correctly in each instance and properly selected the faulted pole, with no misses or misclassifications. Table 4, in turn, gives two forward external faults (f₅ and f₆) at different distances from the relay, encompassing monopolar and bipolar faults; in every case, the scheme refrained from tripping. Across the entire simulation set, the correct-operation rate therefore reached 100%, with a misoperation rate of 0%, demonstrating high reliability.

Fault-detection time. The proposed scheme detects a fault and issues a trip signal in less than 1 ms after fault inception, exhibiting ultra-fast performance. In the most favorable case, the relay operates virtually at the instant of the fault at exactly 2.0001 s, while even in the least favorable case, where traveling-wave propagation introduces the largest delay, the decision is completed only 0.6 ms after the event. For example, Table 3 shows that a 0 Ω fault at location f₃ (remote end of Line 1) is picked up at approximately 2.0006 s, i.e., 0.6 ms after inception; an identical operating time is observed for a 700 Ω high-resistance fault, with no perceptible delay. Accordingly, the average detection latency is 0.3–0.5 ms, with a maximum of 0.6 ms. This response is substantially faster than that of conventional AC distance relays and many existing DC protection schemes, thereby meeting the stringent speed requirements for rapid fault clearance in flexible HVDC systems.

False positive rate: No false trips occurred in any external-fault scenario, giving a false-alarm rate of 0%. In a forward external metallic fault at f₅, the disturbance briefly raised ΔuLf1 above the start threshold Δ₁ = 30 kV, but the derived feature X remained at 31.86 kV, well below the decision threshold Xset = 85 kV, so the relay correctly classified the event and did not trip. For more distant or resistive external faults, the start threshold was not reached at all, eliminating any risk of misoperation. Provided that on-site settings follow the described method, an equally low false-alarm rate can be maintained in practice.

Sensitivity under varying fault resistance: Sensitivity is gauged by the maximum fault resistance that the relay can still detect; simulations show dependable operation up to 700 Ω. Under a 700 Ω internal ground fault, the line-mode voltage across the current-limiting reactor still rose swiftly above the start threshold, and the SOD-derived feature X stayed above 85 kV. At location f3 on Line 1, for instance, X ≈ 101.36 kV; across all fault points, X ranged from 109.20 kV to 492.63 kV, values that lie well above the 85 kV protection threshold with no failure-to-trip incidents. For external faults, even the closest 0 Ω metallic fault produced a maximum X of only 62.7 kV, well below 85 kV, so no internal-fault declaration was made. Hence, the relay sustains high-resistance sensitivity without sacrificing external-fault reliability.

In summary, the proposed scheme delivers outstanding quantitative performance in both detecting high-resistance faults and avoiding mal-operations for external faults, thereby offering strong evidence of its reliability and effectiveness.

5.3. Variation in Detection Accuracy as the Fault Resistance Approaches the Threshold

Under high-resistance faults, the fault current becomes very small, and the voltage surge across the current-limiting reactor decreases accordingly. When the fault resistance is close to 700 Ω, the electrical quantities on which the protection criterion depends move toward their preset pickup levels, compressing the safety margin. A variable that exceeds the threshold by a wide margin for low-resistance faults may therefore only marginally surpass it in the high-resistance case. Once field noise and component-tolerance errors are considered, there is a real possibility that the index will fall short of the threshold, in which case the relay will refuse to operate and the detection accuracy for internal high-resistance faults will be compromised.

Simulation results indicate that as the fault resistance rises from 0 to 700 Ω, the decision index decreases monotonically but remains comfortably above the threshold within this range, ensuring dependable tripping. In the 700–800 Ω band, the criterion progressively falls below the threshold, and the relay may fail to trip because the fault signal is insufficient to drive the decision variable across the operating point. This finding suggests that roughly 700 Ω marks the upper boundary for reliable detection in the present scheme; above this level, the system’s accuracy drops sharply. It is important to stress that even near this boundary, no external faults were misclassified: the scheme maintained 100% identification for resistances up to 700 Ω, whereas success rates declined only when the resistance exceeded that value.

In summary, as the fault resistance approaches 700 Ω, the effective margin of the protection criterion narrows, yet adequate headroom remains, and the scheme still operates reliably; beyond this range, additional protective measures should be employed as a complement.

5.4. More Complex DC-Grid Application Scenarios

First, the proposed scheme is a single-ended protection strategy: the protection device on each line computes its criteria solely from locally measured electrical quantities. Consequently, each line can implement the scheme independently for fault detection and discrimination with no communication coupling between lines, making the expansion highly convenient.

Second, as the number of DC-grid terminals increases, the complexity of fault identification indeed grows, chiefly in the way characteristic quantities vary during external faults and in the choice of threshold values. When several converter stations feed the fault simultaneously, the traveling-wave energy can be redistributed via a common bus to multiple healthy lines, such that an external disturbance measured on a given line may have a higher amplitude than in a four-terminal system. It is important to emphasize, however, that even with more terminals, current-limiting reactors are still installed at both ends of each line, acting as natural boundaries. External-fault signals, therefore, still experience attenuation due to the additional reactance and longer propagation paths, whereas internal-fault traveling waves bypass these reactors and thus retain a larger amplitude and steeper fronts. Hence, the core logic of the proposed scheme, employing initial traveling-wave features and their amplification via the SOD transform to distinguish internal from external faults, remains applicable in multi-terminal systems. What must be updated is the decision threshold: it should be re-evaluated for the more complex grid, and the reliability coefficient Krel increased to prevent mal-operation.

In summary, the proposed scheme is inherently scalable to multi-terminal systems with more than four converters, where the protection of each line can still operate autonomously. Nevertheless, the decision thresholds must be re-optimized to accommodate the more complex fault patterns that arise in such expanded configurations.

5.5. How the Proposed Scheme Differentiates Internal from External Faults Under Bipole and High-Impedance Conditions

For bipolar faults occurring within the protected zone, the voltages of both poles collapse simultaneously at the fault point, and the traveling waves that propagate along the line produce pronounced transients in the positive- and negative-pole voltages measured at the relay location. Consequently, the line-mode voltage across the reactor rises steeply and synchronously, with a magnitude even larger than that of monopolar faults. Simulations show that the resulting feature value X is far higher than the decision threshold of 85 kV, allowing the relay to unambiguously classify the event as an internal fault. In contrast, when a bipolar fault is external to the protected line, the traveling wave must traverse additional reactors or longer distances before reaching the relay. The amplitude and steepness of the line-mode voltage change are therefore greatly attenuated, and the SOD-derived X falls to only a few kilovolts or a few tens of kilovolts, well below the 85 kV threshold, so no internal fault is declared. Table 4 confirms that all such cases are correctly identified as external faults, with the most severe external scenario yielding X_out.max = 62.7 kV, comfortably beneath the pickup level.

For high-resistance faults, the scheme relies on the SOD transform to magnify the initial signal discontinuity, ensuring that the feature X for an internal fault remains markedly larger than that for any external disturbance. Although a high fault resistance reduces the fault current and the accompanying voltage surge, the initial wavefront at an internal fault is still relatively steep. The third-order SOD accumulates multiple differential operations, accentuating this steepness so that even subtle changes in the line-mode voltage are amplified. An external fault, by contrast, produces a much flatter wavefront after passing through additional reactors, and its SOD magnitude diminishes further. By setting the threshold at 85 kV, the smallest X for an internal high-resistance fault is still above the largest X observed for an external fault. Simulations verify this design choice: even with a fault resistance of 700 Ω, every internal fault yields X > 85 kV and the relay trips correctly, whereas in all external-fault cases, X either remains far below 85 kV or never even reaches the start condition, so no false trip occurs.

In summary, whether confronted with bipolar faults or high-impedance faults, the scheme exploits the differences in the initial magnitude and rate of change in the line-mode voltage at the current-limiting reactor and leverages the SOD transform to widen the numerical gap between internal and external events, thereby achieving reliable zone discrimination.

5.6. Feasibility of Implementing the Proposed Scheme in Digital Protection Relays (DPRs) and Other Hardware, and Its Integration Within Real-Time Protection Architectures

First, regarding hardware feasibility, the proposed scheme’s core computations consist of deriving the line-mode voltage across the current-limiting reactor, applying a third-order sequential overlapping derivative transform to the fault component, and performing a threshold comparison. These tasks impose only a modest computational burden and can therefore be readily executed by the microprocessors or DSPs embedded in modern high-performance DPRs, whose clock frequencies typically range from tens to hundreds of megahertz. With a cycle time of 40 µs, the required additions, subtractions, and differencing occupy only a fraction of the available processing window. The sampling rate of 25 kHz is readily achievable using present-day equipment, and the memory demand is minimal: the relay merely needs to retain ten samples, about 0.4 ms of data, to perform the calculation. Hence, contemporary DPRs possess ample computing power, sampling bandwidth, and storage to accommodate the proposed algorithm.

The proposed scheme’s core tasks—acquiring the line-mode voltage across the current-limiting reactor, isolating its fault component, performing a third-order SOD transformation, and executing a simple threshold decision—impose only a modest computational load. These operations can be executed in real time by the microprocessors or DSPs embedded in modern digital protection relays (DPRs). Contemporary high-performance DPRs offer processing capabilities in the tens to hundreds of megahertz, so the add–subtract and differencing operations required every 40 µs (one calculation cycle) consume only a small fraction of the available resources. The required 25 kHz sampling rate is easily attainable with current hardware, and the algorithm needs to retain only about ten samples over each 0.4 ms window—far below the memory capacity of modern relays. Consequently, existing DPR platforms can readily accommodate the proposed protection scheme in terms of processing power, sampling capability, and storage overhead.

Second, for integration into a real-time protection architecture, in service, the scheme would act as the primary protection for each DC line and be embedded in the converter-station protection system. A DPR installed at the line terminal acquires the voltages on either side of the current-limiting reactor, preprocesses them, and calculates in real time the SOD-based feature X and the zero-sequence feature Y. If an internal fault is identified, the relay issues a trip command within 1 ms, swiftly isolating the fault and limiting the released energy. Because the algorithm determines the fault type concurrently, the DPR can isolate only the faulted pole while keeping the healthy pole energized, thereby enhancing supply reliability. Once the line is cleared, system control and the remaining converters can reallocate power to preserve network stability, with the proposed relay coordinating naturally with backup protections.

In summary, the scheme is both technically feasible and practically valuable: it can be realized with existing digital relays, integrated seamlessly into current protection frameworks, and provides a high-speed, dependable line-protection function for large-scale VSC-HVDC grids.

6. Conclusions

A DC-line protection scheme is proposed for multi-terminal flexible DC grids, based on the line-mode fault component of the current-limiting reactor voltage. The scheme is immune to current-limiting control strategies and exhibits strong tolerance to fault resistance. It has the following key features:

• The scheme relies solely on the first-arrival features of relevant electrical quantities, using a data window of only 0.4 ms. This ensures fast operation, meeting the response speed requirements for primary protection in flexible DC systems.
• The fault identification is based on the extracted line-mode fault component of the reactor voltage. Simulation results demonstrate that this component is unaffected by the presence or absence of current-limiting control.
• By applying the SOD transform, fault features are further amplified. The scheme operates reliably for positive-pole-to-ground faults, bipolar faults, and negative-pole-to-ground faults at any internal location and can tolerate fault resistances up to 700 Ω. It remains secure and does not misoperate under external faults, exhibiting excellent reliability.
• Traditional protection schemes are often affected by fault resistance and line shunt capacitance, and the influence of current-limiting strategies has not yet been fully addressed. In this paper, the fault characteristics under MMC active current-limiting control are analyzed, and the proposed method is shown to be immune to the control strategy.