A Multi-Step Topological Optimization Approach for Spacer Shape Design in Double-Sided SiC MOSFET Power Modules Considering Thermo-Mechanical Effects

Abstract

Double-Side-Cooled (DSC) power modules, widely utilized in various industrial and transportation applications, are favored for their remarkable high cooling efficiency and minimal packaging parasitics. To extend the life cycle, the design and optimization of metal or alloy spacers have garnered significant research attention due to their role in mitigating thermal-expansion-mismatch-induced stresses. Among the optimization approaches, topology optimization (TO) methods have the merit of generating innovative spacer shapes, thereby maximizing the buffering effects. However, without certain design considerations and constraints predetermined, the overall processes can become computationally costly. This paper proposes an efficient strategy for finding the optimized spacer topology for a double-sided 1700 V/400 A DSC SiC MOSFET power module. First, comparative thermal-stress investigations are carried out to predetermine the spacer height prior to TOs. Subsequently, to identify the appropriate optimization target, different objectives are employed in the TOs of a 2D simplified model. Following this, TO with the selected target function is performed on 3D simplified models featuring diverse spacer combination architectures, with the preferable one chosen based on the outcomes. Eventually, leveraging the predetermined spacer height, objective function, and preliminary structure, a 3D TO spacer design utilizing a full-domain model is conducted to validate the effectiveness of the proposed methodologies. The final spacer design reduces the maximum von-Mises stress in the attachment by 19.42% (from 111.78 MPa with brick spacers of the same height to 90.07 MPa). The proposed multi-step TO method can therefore be used to improve the thermo-mechanical lifetime of DSC power modules.

1. Introduction

Along with the fast development in modern electric and hybrid electric vehicles (EVs/HEVs), power modules based on wide bandgap (WBG) semiconductors, e.g., silicon carbide (SiC), are gaining increasing attention. In the existing packaging structures for WBG power modules, the double-sided cooled (DSC) structure has become a focus as it can cause significant reductions in thermal resistance and parasitic parameters [1,2,3]. However, since both sides of the power dies are restricted synchronously by direct bonded copper (DBC) or active metal bonding (AMB) substrates, the stresses introduced by thermal-expansion mismatches can concentrate severely in the soldered attachments, causing serious thermo-mechanical fatigues and even resulting in attachment fracture [4,5].

To overcome the aforementioned risks, conductive spacers (also known as bumps or interposers) are extensively used for interconnecting chip top electrodes with a substrate to buffer unbalanced thermal deformation and thereby reducing the thermo-mechanical stresses in the attachments, as illustrated in Figure 1. Silver or copper is most commonly utilized because of its high electrical and thermal conductivity [6,7,8,9]. For example, Ding et al. [9] chose sintered-Ag spacers for a double-sided half-bridge SiC MOSFET module to better reduce thermo-mechanical stresses. To better match the thermal expansion between spacers and chips, several other metallic or alloyed spacers have also been researched. In [10], Wang et al. used molybdenum spacers instead of copper ones. The feasibility was proved by both numerical simulations and experimental tests.

Besides the materials, the influences of the spacer structures on the buffering effectiveness have also been discussed [11,12,13]. For example, Cao et al. [11] presented a novel bridge-shaped spacer to improve heat dissipation performance as well as reduce thermo-mechanical stress in the attachments. Li et al. [12] claimed that a composite brick structure by sandwiching a thick molybdenum layer with two thin copper sheets can reduce thermo-mechanical stress greatly compared with the other four buffers. In [13], Jeon et al. proposed three novel spacer designs, i.e., 2 × 2 array trenched, X-shaped, and octagon-structured. These spacers led to significant reductions in residual stresses after a large number of thermal cycles.

In order to further optimize the thermo-mechanical performance of a DSC power module, it is critical to carry out the multi-disciplinary and multi-objective optimizations of power modules [14,15,16], but conventional optimization methods can only vary the sizes and numbers of the module components, while they are unable to vary the topology or shape. It is highly improbable to reach the best design only by engineering experience and using different materials [17,18]. It was noted that topology optimization (TO) methods can yield superior device performances by varying the material distributions in tessellated cells, and thus can realize the shape variations during the optimization processes [19,20]. Recently, TO has been utilized in designing heat sinks for power modules [21,22]. In [21], Santhanakrishnan et al. proposed a level-set TO approach for the heat sink shape design with copper-aluminum multi-material. In [22], Lee et al. reviewed and discussed the appropriateness and equivalence of various objective functions in the TOs of heat sinks.

However, as the spacers in the double-sided power modules should also act as the conducting bridges connecting the copper traces on the top and bottom substrates, to guarantee the basic electrical and thermal conduction, spacer combinations consist of unchanged spacer frames and shape-changed spacer fillings are preferable in the TO designs. In addition, to better balance the optimization efficacy and efficiency, in the objective function, the ratios between the stress in the soldered attachment and that in the whole region should also be discussed. Since hundreds or more times of thermal-mechanical coupled field simulations are often needed in finding a fine TO design, it could be very time-consuming to decide the aforementioned issues in 3D full-domain models.

To address the problems, in this article, an efficient TO strategy is proposed for the spacer shape design of a 1700 V/400 A DSC SiC power module, as the module is an automotive-grade one with pronounced thermo-mechanical loading. First, the spacer height is decided through comprehensive numerical simulations. Based on the suited spacer height, secondly, the various objective functions are used in the TOs of a 2D simplified model, and the preferable one is selected by balancing the effectiveness and efficiency of the TOs. The TO designs are then conducted on two 3D simplified models with different spacer combination architectures to choose the preferred one. Finally, the spacer shape with the 3D full-domain model is optimized.

Section 2 presents the methodologies and the optimization procedure of the proposed approach. Then, in Section 3, the thermo-mechanical stresses of DSC power modules using regular rectangular bulk buffers are simulated to predetermine the spacer height used in later TOs. In Section 4, the 2D TO designs of the spacers with different optimization objectives are determined for further 3D TO design. In Section 5, two preliminary spacer combination structures are proposed and utilized in the TO designs based on 3D simplified module models. The suitable preliminary structure is selected in this Section. In Section 6, a full-domain model is established and combined with the selected spacer height, objective function, and spacer combination structure to obtain the 3D TO design. The conclusions are presented in Section 7.

2. Methodologies

The module studied in this paper is a DSC 1700 V/400 A half-bridge multi-chip SiC MOSFET power module utilized in EVs and HEVs, the basic structure of the prototype is illustrated in Figure 2. As the module is an automotive-grade one with pronounced thermo-mechanical loading, the low thermo-mechanical stress TO design is essential.

During operation, the CTE mismatch between the substrates and the chips, combined with the presence of temperature gradients, results in differential thermal expansion. Since the chips and substrates are bonded through attachments, this differential expansion induces thermo-mechanical stress concentration within the attachments—particularly pronounced in DSC modules, where the chips are constrained by substrates on both sides. Under sustained thermo-mechanical stress, the attachments are prone to fatigue failure over long-term operations, thereby compromising modules’ reliabilities.

To mitigate this issue, spacers, as shown in Figure 1, have been introduced to alleviate the stresses arising from CTE mismatch, thereby enhancing the operational lifespan. However, conventional spacers adopt a simple brick-like geometry, as shown in Figure 2, which fails to fully exploit their stress-buffering potential. Addressing this limitation, this paper proposes a TO-based design methodology for spacer structures, aiming to maximize their stress-relief capacity. In this methodology, the solid isotropic material with the penalization (SIMP) method is combined with the method of moving asymptotes (MMAs) to realize the explicit of very complicated TOs [23,24,25], and the non-linear thermal-stress coupled simulations used in the TO designs are conducted using finite element analyses (FEAs) [26,27,28]. To improve the optimization efficiency and to reduce significantly the computational cost, several design considerations (the spacer height, the optimization objective, and the spacer combination structure) are predetermined before the TO of a full-domain model. The overall design scheme is illustrated in Figure 3, and the processes are as follows:

(1)

As the TOs are conducted with the governing variable θ_c varied in the tessellated and fixed grids [23,24,25], the influences of spacer height variations will have to be analyzed in multiple TOs with different spacer models and grids; therefore, increasing significantly the computational cost. To handle this problem, first, comparative numerical analyses are simulated based on conventional brick-shaped spacers with different heights, and the proper height is selected and predetermined in the first step.

(2)

Since the spacers are utilized to buffer the thermo-mechanical stresses, which may influence the working performances of the devices or even result in failures [29], the stress-related global variable, for example, the strain energy w_s, should be considered in the optimization target function. However, whether to simply use the strain energy in the chip-substrate attachment w_{s_attachment} or take the other components w_{s_others} into consideration should also be analyzed. To better balance the optimization convergence and the optimization effectiveness [29], in the second step, the influence of the weight factors is investigated, and the weighted objective combinations are formulated as follows:

$$obj\left(\beta \right)=w_{\mathrm{s}\text{\_}\mathrm{attachment}}+\beta w_{\mathrm{s}\text{\_}\mathrm{others}}$$

(1)

where β is the weight factor. When β = 1, the objective function is the total strain energy, and when β = 0, only the strain energy in the attachment is considered.

(3)

In addition to the spacer height and the optimization objective function, the TO region of the spacers should be limited with a non-optimized spacer frame to guarantee basic electric and thermal conductivity. For 2D TOs, the non-optimized spacer frame and optimized spacer filling structure can be simple, but the 3D ones can be divided into two categories: (I) a spacer frame with two longitudinally placed fillers sandwiching the pillar of the frame, and (II) a frame with transversely located fillers. The spacer combination models are illustrated in

Table 1. Simplified models with different spacer combination structures.

Description	Model Shape
2D Model
3D Model (I) ---------------- Simplified Model with Spacer Using Longitudinal Fillings
3D Model (II) ---------------- Simplified Model with Spacer Using Transverse Fillings

. Based on the TO results, the preferable spacer combination structure is decided.

(4)

In step 4, the TO based on the power module’s full domain model with the spacer height determined in step 1, the optimization target function decided in step 2, and the preferable spacer combination structure settled in step 3, is conducted to output the final optimized spacer structure.

3. Step I: Thermo-Mechanical Coupled Analyses and Spacer Height Determination

The full domain model of the power module, as shown in Figure 2a, with conventional brick-shaped spacers, as shown in Figure 2b, is established. The thermal-stress coupled fields of the module with different spacer heights (varying from 1.2 mm to 2.2 mm, limited by the external mounting envelope of the power module) are numerically investigated. During simulations, the coolant temperature is set to 65 °C with a flow rate of 10 L/min, and a chip heating rate of 4.44 × 10¹⁰ W/m³ (200 W for each chip), to keep consistent with the actual working condition.

Figure 4a shows the maximum temperature in the module versus the spacer height and Figure 4b–g show the temperature distributions with the spacer height of 1.2 mm, 1.4 mm, 1.6 mm, 1.8 mm, 2.0 mm, and 2.2 mm, respectively.

The only difference in the computed temperature distributions is the maximum value, and the highest temperature occurs at the unconnected area on the top surface of the chip, as the heat transfer efficiency at this location is weaker than that connected with spacers. The module could run at a greater temperature as the spacer rises because there is less thermal connection between the top and bottom substrates. However, because the temperature difference is so modest (under 3.99 K with the spacer height shift from 1.2 mm to 2.2 mm), it may not be as important to consider how the spacer heights affect thermal problems.

Figure 5a shows the maximum thermo-mechanical stress in the chip-substrate attachments versus spacer height. The stress distributions in the soldered attachments with the different spacer heights are shown in Figure 5b–g separately. The power dies’ edges, particularly its corners, are where the attachment stresses are concentrated. The solder portions covered by spacers often have low stresses because of the spacers’ efforts to act as buffers. Additionally, when the spacer height is below 1.8 mm, the stresses in the attachments decrease with increasing height, but they may increase when the spacer height is above 1.8 mm. Because they may offer the highest buffering performances, the 1.8 mm high spacers are preferred, and the spacers are set to 1.8 mm in later TOs.

4. Step II: 2D Spacer TO Design and Objective Function Determination

Based on the 2D simplified model, as shown in Table 1, the TO designs are conducted by varying the governing variable θ_c to decide the material properties in different grids. During the TO processes, the overall areas considering both the spacer frame and the filling parts should be close enough to that of the original brick-shaped spacer (with an area difference ≤ 5%), as shown in Figure 6, and the design schemes that do not meet this regulation are automatically abandoned. To investigate the influences of the optimization target functions on the TO results and to determine the preferable weighted factor in (1), the TO designs with different factors are obtained as follows.

4.1. Total Strain Energy in Whole Region (β = 1)

In this section, the 2D TO design of the spacers is conducted to minimize the total strain energy of the whole solution domain. The spacer shapes during the optimization iterations are shown in Figure 7a–h. As can be found from Figure 7a, the TO designs start with no holes in both sides of the fillings (initial design, step 0), but the design is abandoned since it cannot fit in with the rule of the constant spacer area in optimization. Then, two hollow holes with similar sizes appear synchronously in the forward and backward fillings (step 5), as shown in Figure 7b. The forward hollow hole is then growing larger with the backward hole getting smaller (step 10), as illustrated in Figure 7c, and the backward hole gradually flows into the forward hole to form a very large hole (step 20), as shown in Figure 7d. Later in step 40 of the TO iterations, the backward hole reappears while the forward hole gets “shoe-shaped”, as demonstrated in Figure 7e. For the designs obtained after 60 and 90 steps of iterations shown in Figure 7f,g, respectively, the backward hole is getting taller while the forward hole grows thinner. Finally, after 127 steps of iterations, the optimization converged with the TO design shown in Figure 7h, and the 2D TO design recommends a thin boot-shaped hole dug in the forward filling and an arc-shaped hole in the backward filling.

To validate the TO effect, the thermo-mechanical stress of the optimized model (case 1—Original brick spacer) is compared with that of two non-optimized ones (case 2—Spacer frame and case 3—TO-designed spacer frame). The structures and descriptions of the three cases are tabulated in

Table 2. Structures and descriptions of the three 2D cases analyzed.

No.	Model Shape	Description
Case 1 Original brick spacer		2D simplified model with original brick-shaped spacer.
Case 2 Spacer frame		2D simplified model with non-optimized spacer frame.
Case 3 TO-designed spacer frame		2D simplified model with TO optimized spacer frame (hollow holes dug in both forward and backward fillings).

. Figure 8a–c show the von-Mises stresses with cases 1, 2, and 3, respectively. By the TO of the spacer (case 3), the overall maximum thermo-mechanical stress, i.e., 110.60 MPa, is reduced by 13.69% when compared with that utilizing the original brick-shaped spacer (case 1), i.e., 128.14 MPa, and by 9.74% when compared with that using a spacer with non-optimized fillings (case 2), i.e., 122.53 MPa. By these means, the TO-designed module (case 3) can operate with lower stress than that even with more spacer material consumed (case 2). In addition, for the two non-optimized design schemes, the thermo-mechanical stress in the attachment is very close to the maximum one, i.e., 124.74 MPa, for that with the original brick-shaped spacer (case 1), as shown in Figure 8a, and 119.93 MPa for that with non-optimized spacer combination (case 2), as shown in Figure 8b. In addition, the TO one (case 3) can better release the high stress from the attachments to chips and substrates, the attachment maximum stress is reduced to 98.37 MPa, as shown in Figure 8c, 21.14% lower than that with the brick-shaped spacer (case 1) and 17.98% lower than that with the non-optimized spacer combination (case 2). Since the stress in the soldered attachment is highly decreased, the working reliability of modules employing TO spacers can thus be better guaranteed.

4.2. Strain Energy in Chip-Substrate Attachment (β = 0)

The least strain energy in the chip-substrate attachment is taken as the optimization aim in this section to better meet the attachment-stress-reduction criteria. After 319 iterations using the TO methods, the ideal spacer shape design is attained. The design with the least chip-substrate attachment strain energy, as shown in Figure 9a, suggests two hollow holes in the top area of the spacer fills in addition to the design with the lowest overall strain energy. Figure 9b displays the associated thermo-mechanical stress distribution with the ideal spacer design. The maximum stress, i.e., 146.43 MPa, obtained with the design is 32.40% larger than the total strain energy taken as the objective function, but the stress in the chip-substrate attachment is effectively reduced to 93.42 MPa, which is 5.03% smaller than that with minimum total strain energy. It was attributed to the stress that is more intensely concentrated in the spacer fillings.

4.3. Weighted Strain Energy Combinations (β = 0.2, 0.4, 0.6, 0.8)

The TO design with other factor combinations (β = 0.2, 0.4, 0.6, 0.8) is conducted and illustrated in Figure 10a–d. The interval of 0.2 is selected as the TO results can exhibit a clear trend; otherwise, the interval can be refined. The suggested spacer shapes were rapidly approaching those obtained with total strain energy as the target function, notwithstanding a little increase in the maximum stress in the soldered attachment as the weight factor increased. The overall total strain energy (β = 1) was chosen as the optimization objective in the TOs of the module in this paper because the iteration step for optimization convergence is also reduced with increasing β, e.g., 319 steps when β = 0, 241 steps when β = 0.2, 186 steps when β = 0.4, 150 steps when β = 0.6, 131 steps when β = 0.8, and 127 steps when β = 1.

5. Step III: 3D Spacer Combination Structure Determination

In this section, two 3D simplified models (marked by “3D model (I)” and “3D model (II)” in Table 1) with one SiC MOSFET and the areas extremely close to the single power die are constructed in order to find the preferable spacer combination structure. The first basic model, which is merely a 3D extension of the 2D model used in the previous section, uses a spacer frame with two longitudinally placed fillers sandwiching the pillar of the frame (marked by “3D model (I)” in Table 1). Contrarily, the second model (marked by “3D model (II)” in Table 1) positioned the filler transversely between the pillar of the spacer frame. In this phase, the TO designs are carried out using the two condensed 3D models, with the total strain energy as the optimization objective (β = 1). Due to the symmetry, 1/2 models divided by the intermediate profiles were used during optimization for the 3D TO design with longitudinally and transversely oriented fillers.

5.1. Spacer Frame with Longitudinally Arranged Fillings

After 171 MMA iterations, the TO processes for the model with longitudinally organized spacer fillings converged, and Figure 11a illustrates the optimal filler shape, which is separated by the intermediate profile. The forward filling is hollowed while the backward filling is kept solid to release tensions. The overall maximum stress is further decreased to 104.54 MPa, which is 5.48% lower than that with the 2D model, with the longitudinally placed fillers following 3D TO procedures. The maximum stress in soldered attachment is decreased to 93.64 MPa, which is 4.81% lower than that with the 2D model. Figure 11b depicts the distribution of thermo-mechanical stress.

5.2. Spacer Frame with Transversely Arranged Fillings

The TO design of the filler is created after 187 iterations, as shown in Figure 11c. Figure 11d depicts the associated thermo-mechanical stress with the filling scheme. Based on the simulation results, the stress is still 3.28% higher than that with longitudinally organized fillings although the 3D TO-designed spacer can release stress more effectively than a 2D model. The total maximum stress can be lowered by 2.38%. Additionally, the maximum stress in the chip-substrate attachment rises to 94.77 MPa, which is 1.21% greater than that with the longitudinally oriented fillers and 3.66% lower than that produced by the 2D model. In order to reduce stress more effectively, the longitudinally organized fillers are integrated with spacer frames in the TO design using the 3D full-domain models.

6. Step IV: 3D Spacer TO Design Based on a Full Domain Model

6.1. Three-Dimensional Spacer TO Design and Discussion

To obtain the final spacer TO design with the full considerations of the module’s components, a 3D full-domain model is created, as illustrated in Figure 12, to consider the thermo-mechanical stress interactions among the power chips during TO operations. The pins were omitted in the model during optimization since the TO operations could generate hundreds or even thousands of numerical simulations. This reduced the computational strain.

The TO converges in 462 steps based on the full-domain model, and Figure 13a shows the optimized spacer fillings. The spacer fillings of various chips vary greatly as a result of the mutual impacts among the internal chips and the imbalanced external cooling attempts on them. In general, the fillings attached to exterior chips have the wider hollow holes than those linked to inner chips. Figure 13b displays the thermo-mechanical stress distribution using the ideal spacer combinations. The operational reliability of the module under study in this paper was hence significantly improved after the TO, when the maximum stress in the whole model reduced to 105.48 MPa and the stress in the soldered attachment reduced to 90.07 MPa. Furthermore, as illustrated in Figure 13a, the spacer configuration generated by TO is highly intricate, featuring irregular perforations that pose formidable manufacturing challenges. Nevertheless, with the rapid advancements in additive manufacturing technologies [30], the precise fabrication of such small-scale, irregular metallic geometries has become increasingly feasible.

As summarized in

Table 3. Comparisons between the results of different steps.

Step	Max. Stress in Chip Attachments	Stress Reduction vs. Brick Spacer	Role of Each Step
I	111.78 MPa	--	Set the spacer height.
II	98.37 MPa	12.00%	Define the objective function.
III	93.64 MPa	16.23%	Establish spacer architecture.
IV	90.07 MPa	19.42%	Finalize the TO design.

, the maximum thermal stresses in the chip attachments of the module are compared across four spacer configurations: the conventional brick-typed one (output in Step I), that obtained through the 2D model (output in Step II), that obtained based on the 3D simplified model with longitudinally arranged spacer fillings (output in Step III), and that designed with the 3D full-domain model (output in Step IV). The results demonstrate that the spacers generated by the proposed method at Step IV—derived from the 3D full-domain model—achieve a pronounced reduction in thermo-mechanical stress within the chip attachments, thereby substantially enhancing the operational reliability of the module. The comparisons with the advanced designs in the literature are tabulated in

Table 4. Comparisons between the proposed design and that in literature [9,10,11,12,13].

Ref.	Thermal Resistance	Stress Reduction Rates in Attachments	Technology
[9] Ding et al.	0.4845 K/W	Increased by 15.18% in attachments, reduced by 31.78% in chips	New spacer material used.
[13] Jeon et al.	0.0403 K/W	14.44%	New structure proposed.
This work	0.1083 K/W	19.42%	TO-designed spacer shape.

. The results show the superiority of the proposed TO design.

6.2. Lifetime Predictions

To investigate the influence of the TO design of the spacer on the operational lifetime of the module, this chapter employs the Anand model [31] to calculate the equivalent plastic strain of the chip attachment through transient thermo-mechanical stress field analysis. The simulation settings are illustrated in Figure 14a, where each chip is subjected to a heat source of 200 W with an on-time of 1 s and an off-time of 1 s. By adjusting the heat transfer coefficient, the maximum junction temperature fluctuation of the chip is set to T_jmax = 100 °C (with T_jmin = 50 °C and T_jmax = 150 °C). Five power cycles are conducted, and the maximum equivalent plastic strain in the chip attachments is depicted in Figure 14b.

Based on the calculated plastic strain values, the power cycling life is evaluated using the Coffin–Manson equation [32]:

$$N_{\mathrm{f}}=C\cdot {(\mathsf{\Delta }{\epsilon }_{\mathrm{plastic}})}^{-\alpha }$$

(2)

Here, N_f denotes the number of failure cycles, and Δε_plastic represents the plastic strain amplitude per cycle. The constants C and α are physical parameters of the attachment (C = 0.160 and α = 2.96 for this case studied). The computation results show that, using the spacers before the TO design, the lifetime of the module is limited to 80,120, while using the TO-designed spacers can prolong the lifetime to 131,131 (increased by 63.67%), thereby guaranteeing the effectiveness of the proposed methodology.

7. Conclusions

In this paper, a muti-step TO approach is proposed combining the SIMP method and thermal-stress coupled calculations for the spacer shape design optimization for a double-sided 1700 V/400 A SiC MOSFET power module. In the first step, the thermal and stress fields of the module with conventional brick-shaped spacers are numerically investigated to find out the spacer height effects on the thermo-mechanical stresses and to determine the basic spacer height used in later TO designs. In the second step, the preferable optimization objective is selected by comparing the stresses and the convergent steps of 2D TO designs based on a simplified single-chip module model with differently weighted objective functions. The total strain energy (the weighted factor β = 1) is resolved as the objective function in the 3D TOs for its superiority in both the optimization effectiveness and the convergent speed. To decide the basic spacer combination structure used in full-domain TO designs, in the third step, two simplified 3D single-chip models with different filling configurations are topologically optimized. The longitudinally arranged structure is selected based on the TO results. In the fourth step, a full-domain module model is established and combined with the chosen spacer height, objective function, and preliminary structure to obtain the spacer shape design, and the optimization effectiveness is proved by the reduced thermo-mechanical stress. Structural-optimized spacers for a 1700 V/400 A DSC module based on the proposed method can reduce the chip-attachment thermo-mechanical stress by 19.4% (from 111.78 MPa to 90.07 MPa), confirming that the proposed spacer-TO method reliably minimizes attachment stresses in DSC devices. The module’s lifetime simulation results indicate that the implementation of the TO-designed spacer can enhance the module’s lifespan by 63.67% (from 80,120 cycles to 131,131 cycles). This further substantiates the efficacy of the TO methodology. In addition, although the present study centers on a SiC MOSFET power module, the proposed methodology is applicable to the packaging design of a broad range of WBG semiconductors.

Owing to the pronounced geometric complexity and irregularity of the TO-designed spacer, together with the stringent precision requirements imposed by the power modules, future efforts will be directed toward the additive manufacturing of this component and its subsequent experimental validation.