Delta Modulation Technique and Harmonic Analysis for the Modified Quadruple-Diode Boost Regulator Without and With a Voltage Multiplier Unit (VMU)

Abstract

The authors of this study suggest an improvement to their recently released quadruple-diode boost regulator (QDBC), which may be used in two configurations: without or with a voltage multiplier unit (VMU). This voltage multiplier unit consists of two switch capacitors diagonally connected across two diodes, or vice versa. During each operational cycle, energy can be stored and released through the switch capacitive filters and inductive chokes, increasing voltage gain and decreasing output fluctuation. ANSOFT/SIMPLORER 7, PLECS 4.9.5, and SIMULINK 2021a are further used to simulate the proposed regulator’s linearized version to investigate its frequency response and stability. Hence, to improve the harmonic performance of the proposed regulator, the authors of this study used a delta modulation current regulator (DMCR), sometimes referred to as a variable bandwidth delta modulation current regulator. The findings show that the QDBC has, when using the DMCR, a voltage gain of $1+D/{(1-D)}^2$, an efficiency of 97%, and a shorter settling time of 0.04 s when compared to other DC-DC regulators (SEPIC, boost, and quadratic boost). Finally, to validate the theoretical analysis and simulation results of the proposed QDBC structure, a 250 W regulator prototype was built utilizing similar design exercise requirements.

1. Introduction

Human survival depends on a habitable environment because fossil resources are limited. Because of their effectiveness and low environmental impact, electric vehicles, or EVs, are being marketed as an efficient means of transportation. To encourage EV use and reduce the fuel emissions linked to EV charging on the electrical grid, governments worldwide are passing legislation and offering incentives [1,2].

The adoption of electric vehicles is increasing the need for power electronics regulators. Thus, power electronics regulators are essential parts of electric vehicles (EVs) because they convert energy from a power source into a format suitable for an electric drive system. EVs and the systems that facilitate their charging rely on a variety of regulators, including DC–DC power regulators, rectifiers, inverters, and AC–AC regulators [3,4,5,6].

For instance, DC–DC power regulators are used when public transportation networks transition from petroleum gasoline to electric-powered automobiles. This is enacted to provide the necessary DC power for the AC inverter to run the AC motors of the electric-powered drives. Such a drive system typically consists of a motor powered by electricity (synchronous, DC, or induction) and additional functioning pieces for the electric automobile [7,8].

Because DC–DC traditional step-up (boost) regulators can supply a continually varying DC voltage, they have been utilized to provide adjustable-speed DC and AC drives with power ratings ranging from microwatts to kilowatts [9,10].

Mining trucks, electric automobiles, trolleybuses, cranes, ship elevators, and other solar-powered traction motors use traditional step-up regulators as speed and position regulators. They provide a DC power source, exceptional efficiency, and quick dynamic response for electric vehicles.

The powerful-gain DC–DC regulator must be designed and tested from several perspectives to be used with electrically powered cars and other energy sources. When creating a powerful-gain DC–DC regulator for solar and drive systems, a few factors must be carefully considered. Examples include the parameter waveforms, the total number of components, the input current, and the strain on the devices and components [10,11,12,13,14].

In response to the findings and solutions to the problems raised by many researchers, such as reduced voltage gain and the effectiveness of regulators in specific systems, like solar energy facilities and windmills, the authors of this work conducted research, development, and practical tests on their recently released regulator, known as a quadruple-diode boost regulator (QDBC), to show its superiority over other identical processors [1].

Madhav Kumar et al.’s July 2024 study, for example, examined and analyzed recent highly efficient DC–DC regulators for electric car applications, based on the quadratic boost regulator (QBC). This offers a regulator with a conversion voltage ratio of $1/{(1-D)}^2$. However, using a comparable duty ratio, D, the envisioned quadruple-diode structure investigated in this paper has a higher voltage conversion ratio than Madhav’s QBC [5].

A unique quadratic boost regulator with a voltage tension that is half the output voltage was proposed by Anindya Sundar Jana et al. in a 2022 study. In addition to providing the required voltage gain and operating across a wide range of duty ratios, the proposed topology is a member of the non-isolated category family with a shared ground feature [6].

In July 2024, Young-Kyun Cho et al. investigated the switching noise and efficiency of the step-up regulator to satisfy the growing demand. Young-Kyun Cho and his colleagues developed a boost DC–DC regulator for battery-powered and noise-sensitive applications using a continuous-time delta-sigma modulator (DSM) controller. The proposed regulator clamps the maximum duty cycle of the DSM and may dynamically change a wide range of output voltages, allowing stable and reliable transient responses. The modulator’s noise-shaping capability significantly reduces the switching harmonics of the regulator output. In their study, the suggested regulator generated an output voltage between 2.5 and 5.0 V with an input voltage of 2.0 V and a maximum conversion efficiency of 95.5% [7].

Milad Rezaie et al. suggested a high-step-up modified DC–DC regulator that was based on a quadratic boost regulator with a multiplier cell. To reduce the number of parts, the multiplier cell and quadratic boost regulator were made to share one inductor. In addition to the analysis, experiments were carried out. With the recommended regulator, the output voltage can be raised by 14 times. The findings demonstrate that the regulator operates with an efficiency of more than 90% for the required output power, has a lower voltage stress, and requires fewer inductors than a quadratic boost regulator [8].

López-Santos et al. explored and assessed the efficiency of a quadratic boost converter with high DC gain to raise the voltage of a conventional solar panel to four. A thorough efficiency analysis takes into account both conduction and switching losses. The power switch’s commutation characteristics, including the switching frequency, switch voltage in the off state, and switch current in the on state, are the main determinants of switching losses. Furthermore, Milad Rezaie et al. evaluate the quadratic boost converter’s performance under all possible operating circumstances [9].

The suggested QDBC may be a viable solution to satisfy the unique needs of electric driving mechanisms and their supply from solar power sources or the electricity network. The literature study provides a foundation for understanding the efficiency, energy density, and overall performance parameters of QDBC-based powerful-gain regulators.

The authors address the growing need for high-voltage gain DC–DC switching regulators in several industrial applications, including renewable energy, transportation, industrial applications, and healthcare.

As a result, an inventive, powerful-gain regulator was also produced by combining the proposed QDBC regulator with voltage multiplier units. The authors address the issue of stress levels on dynamic and passive switches as the number of elements that can store energy increases. An output LC filter and an X-bridge voltage multiplier unit were used to accomplish this. The document presents formulas for inductive and capacitive voltages, currents, and related variations to increase the regulator’s accuracy. Thus, the recommended regulator possesses the following characteristics:

• Although the quadruple-diode boost regulator has more diodes and energy-storing components than the traditional step-up regulator, it nonetheless generates more power and, regrettably, higher voltage strain that is still within the permitted operating limits. However, the authors of this research also discussed this problem and provided the best solution;
• The quadruple-diode boost regulator outperforms the quadratic boost regulator (QBD), SEPIC regulators, and traditional step-up regulators in terms of voltage gain;
• The simulation and results in terms of regulator responsiveness, rising time, delaying response, effectiveness, and sensitivities to parameter variations validate the importance and preference of the DMCR as compared to other hysteresis (delta modulation) approaches covered in the literature [11,12];
• The performance of the delta modulation current regulator is evaluated by varying the delta modulation window limits, computing the harmonic content of the regulated current in terms of the corresponding harmonic ratio, and keeping the regulated current’s time derivative constant. The findings demonstrate that although the response speed stays constant, the delta modulation bandwidth has a significant effect on the quality of the regulated current. Therefore, considering the regulator restriction, a moderate delta modulation bandwidth was chosen;
• Based on the comparison study conducted for this work, QDBC is more useful than a typical step-up regulator, especially for solar panels, electric cars, and high-power renewable energy systems;
• When compared to step-up regulators such as SEPIC, boost, and buck-boost, the proposed configuration greatly reduces many harmonics emitted at the input and output with high effectiveness;
• The suggested quadratic boost regulator’s effectiveness has been assessed under a range of operational conditions, including supply voltages and loading scenarios. It has also been investigated during the laboratory simulation and analysis of the suggested converter at various switching frequencies. The simulated and analytical findings show that the efficiency level of the suggested QDBC regulator is 97%;
• The voltage gain of the suggested regulator is ${\displaystyle \frac{V_o}{V_s}}={\displaystyle \frac{(1+D)}{{(1-D)}^2}}$. This is larger than many other DC–DC regulators, including those suggested in [9,10,11,12,13,14]. Furthermore, adding the voltage multiplication circuit at the output of the proposed regulator (VMU) creates a new opportunity to have a regulator with a much greater voltage gain than others. The voltage gain of the suggested regulator with the VMU filter becomes ${\displaystyle \frac{V_o}{V_s}}={\displaystyle \frac{1+3D-2D^2}{{(1-D)}^2}}$;
• The VMU filters at the regulator’s output can also be used to lessen the increased voltage tension (strain) on both passive and active switches.

The next section contains a brief circuit analysis of the proposed regulator, simulation findings using the appropriate inquiry technique in terms of harmonic analysis, voltage, and current normalized variations, and a comparison with comparable step-up DC–DC regulators. In the additional sections, delta modulation current regulation methods were examined for stability and harmonic analysis. Following that, calculations were run to determine the voltage gain, effectiveness, frequency response, and Bode diagrams. MATLAB/SIMULINK, PLECS, and ANSOFT/SIMPLORER were used to model the regulator’s dynamic performance and validate the analytical results. To verify the accuracy and feasibility of the theoretical calculations and simulation results, an experimental 250 W prototype model was constructed. After receiving 10 V at its input and various duty ratios for its primary switch, the prototype produced 25 V, 50 V, and 90 V as distinct output voltages, depending on the regulation technique and duty ratio.

Thus, a proposed regulator passed a practical test for powering a DC motor with a supply voltage of 25 V and a current of 0.35 A. It then had to pass another test that required it to power a highly inductive resistive load with $R=200\mathsf{\Omega }$ and $L=3.3\mathrm{m}\mathrm{H}$ at either 50 V and 1.8 A or 90 V and 1.4 A. The experimental design of the regulator does not include a voltage multiplier unit.

2. An Elementary Analysis of Quadruple-Diode Boost Regulator (QDBC)

2.1. Operating Principle of QDBC Without an VMU Filter

Figure 1 depicts the basic construction of the newly redesigned single-switch quadruple-diode boost regulator (QDBC). QDBC consists of a DC power supply, inductive chokes (L₁, L₂, and L₃), a single-powered semiconductor switch (MOS), capacitive filters (C₁, C₂, C_3, and C_o), four diodes (D₁, D₂, D_3, and D₄), and a DC resistive load (R_o). According to

Table 1. This lists the characteristics crucial for modeling and simulating QDBC in an uninterrupted current mode (UCM).

QDBC Design Specifications
Parameter	Symbol	Real Value
Step Input Voltage	Vs	(50–100) V
Inductive choke with a series resistance (ESR)	L1	1 mH, 0.1 Ω
Inductive choke	L2	500 µH
Inductive choke with a series resistance (ESR)	L3	5 mH, 0.1 Ω
Capacitive filter	C1	1 mF
Capacitive filter	C2	470 μF
Capacitive filter	C3	470 μF
Capacitive filter	Co	1 mF
Load resistance	Ro and Lo	20 Ω and 2 mH
Switching frequency	f	10 kHz
Forward diode voltage	-	0.8 V

, the following analysis will focus on the regulator’s operation in the uninterrupted current mode (UCM) [1,12]:

The uninterrupted current mode (UCM) describes the transmission of energy via inductive choke currents that never reach zero. As a result, during the proposed regulator operation in the UCM, the switch MOS is turned on for $t_{on}=DT$ and off for the rest of the time $t_{off}=(1-D)T$. Parameter D reflects the duty ratio of the QDBC regulator main switches [11,12,13,14]. Figure 2 and Figure 3 are the equivalent circuits of the proposed regulator’s two switching states, on and off. The voltage conversion ratio can be represented using the following equations, using inductive choke currents as state-dependent variables.

Upon operating the switch as shown in Figure 2, the source current oscillation via inductive choke L₁ is as follows:

$$\Delta i_{L1\left(close\right)}={\displaystyle \frac{V_s}{f{L}_1}}D=\Delta i_{s\left(close\right)}$$

(1)

Parameter T denotes the QDBC functioning period, while $f=1⁄T$ represents the switch operating frequency. When switch “S” is switched off, as shown in Figure 3, diode D₂ deactivates, and all other diodes become forward-biased. The normalized variation in source current is [1,12]

$$\Delta i_{L1\left(open\right)}={\displaystyle \frac{V_s}{f{L}_1}}\left(1-D\right)-{\displaystyle \frac{V_{c1}}{f{L}_1}}\left(1-D\right)=\Delta i_{s\left(open\right)}$$

(2)

For the QDBC quasistationary state to operate successfully, the inductive choke current oscillation must be equal whether the regulator main switch is turned on or off. This requires

$$\Delta i_s={\displaystyle \frac{V_s}{f{L}_1}}D$$

(3)

The following calculations for capacitive filter voltages use the aggregated averages of the EMF voltages under quasistationary state conditions:

$$\begin{array}{c}\begin{array}{c}{V}_{C2}={\displaystyle \frac{-D{V}_s}{{(1-D)}^2}}\\ V_{C3}={\displaystyle \frac{V_s}{{(1-D)}^2}}\end{array}\\ V_{c1}={\displaystyle \frac{V_s}{1-D}}\end{array}$$

(4)

By replacing $V_{C2},$ and $V_{C3}$, with their values from the preceding equations and $v_{L3}=0$ in the quasistationary state, one can obtain

$$V_o={\displaystyle \frac{1+D}{{(1-D)}^2}}{V}_s$$

(5)

By appropriately altering the spanning duty ratio D, the output voltage can be changed in proportion to the input voltage. To design them, it is necessary to ascertain the average currents of the inductive chokes. By applying the ampere-second balance principle on the C₁, C₂, C_3, and C_o capacitive filters, and thus, the inductive choke average currents are obtained as follows:

$$\begin{array}{c}{I}_{L2}={\displaystyle \frac{1+D}{1-D}}{I}_o=\left(1-D\right)I_s\\ I_{L3}=I_o={\displaystyle \frac{{(1-D)}^2}{1+D}}{I}_s\end{array}$$

(6)

A simulation was conducted in Simulink MATLAB 2021a with the parameters listed in Table 1 to verify the effectiveness of the suggested regulator without a voltage multiplier circuit.

The outcomes of the simulation study conducted in UCM mode using pulse width modulation (PWM) are illustrated in Figure 4, Figure 5 and Figure 6. When turned on, the QDBC essential switch is active 75% of the time. The evaluated results for the proposed regulator correspond to a step change in the supply voltage, V_s.

Additionally, Figure 4 shows that when the input voltage, V_s, is 50 V, the resultant load voltage, V_o, approaches 1300 V; when the input voltage is increased to 100 V at time $t=0.4s$, the resultant load voltage approaches 2600 V. In synchrony with the shift in input and output voltages, the input and output powers step from ($P_s=90\mathrm{k}\mathrm{W}$: $P_o=80\mathrm{k}\mathrm{W}$) to ($P_s=360\mathrm{k}\mathrm{W}$: $P_o=325\mathrm{k}\mathrm{W}$, respectively).

Although the gain formula indicates that the real value should be 1400 V, a 50 V input yields an output of 1300 V, resulting in an approximate voltage loss of 7%. The amount determined by the gain calculation, which is 2800 for an input of 100 V, is 200 V different than the measured 2600 V. A resistive-inductive equivalent circuit is commonly used to simulate the inductor filters as mentioned in Table 1, rather than a pure inductive circuit, in cases when a current oscilloscope is not available to measure the current flowing through the circuit. Such small resistors are connected to the input and output inductive filters, L₁ and L₂, to measure the voltage across them rather than the current when a current oscilloscope is unavailable. The current waveform is then measured and sensed using Ohm’s law. The dynamic resistors of the transistors and diodes, which have a forward bias voltage of 0.8 V and a forward bias resistance of 0.001 Ω, are examples of other parts of the simulation circuit that could contribute to these losses.

The QDBC regulator performs significantly better in terms of output current and voltage fluctuation, harmonic content, settling time, rise time, and voltage gain when compared to the QBC regulator. This is shown by the comparison of the Figure 4 results with the results obtained in [4,5] for the QBC. Furthermore, at different duty ratio values, the suggested regulator outperforms the other alternative regulators (boost, SEPIC, Buck-boost, and QBC regulators) in terms of voltage conversion gain [15].

The suggested regulator also outperforms modified and customized DC–DC converters, similar to the modified SEPIC-buck regulator. Its voltage gain is $(1+D)D/1-D.$ Its THD is 6.6%, and its efficiency is 97–98% [13]. Additionally, the proposed regulator has better dynamic features and fewer energy storage components than all of the cascaded DC–DC regulators, quadratic boost converters, and hybrid boost converters displayed in [14].

Figure 5 and Figure 6 illustrate the essential switch voltages and currents, along with those of the inductive chokes and capacitive filters. The proposed regulator’s voltages and currents increase or decrease in alignment with the supply voltage’s step-change.

Figure 5b shows that for a duty ratio of approximately 75%, the average inductive choke currents of L₁ and L₂ are 460 A and −60 A, respectively. This leads to the conclusion that Equation (6) validates the above-mentioned theoretical calculations with about a 1–3% error rate.

Moreover, Figure 6b confirms the theoretical analysis carried out in Equations (4) and (5), again with an error rate of around 1–3%. It indicates that the average voltages of capacitive filters C₁, C₂, C₃, and C_o have values of 180 V, −550 V, 720 V, and 1300 V, respectively, at a duty ratio of roughly 75%.

Figure 7 shows the close-up signals of the proposed converter, showing the rise and fall (ripple) of the state voltage variables across the capacitors and the state current variables through the input and output inductive chokes. These waveforms were recorded at a duty cycle of 75% and a switching frequency of 4 kHz to best depict the voltage and current volatility.

Figure 7a shows that, under the specified operating conditions, the ripple in the load voltage is $\Delta V_o=1315-1290=40\mathrm{V}$, or nearly 3% of its average value. The load current ripple is approximately $\Delta I_o=131.5-129=2.5\mathrm{A}$, or 2% of its average value. The ripple in other variables, such as capacitive voltage and inductive currents, may be easily ascertained from the simulated waveforms in Figure 7b, which is shown to be in the best possible situation. The ripple in source current and voltage is minimal.

Therefore, Figure 7 provides yet another illustration of the suggested converter’s favorable dynamic characteristics.

2.2. Operating Principle of QDBC with a Voltage Multiplier Unit (VMU)

The authors of this study tried another well-known and widely used method to create a dynamically better QDBC regulator with a higher voltage gain. This was accomplished by integrating a filter (LC) with a voltage multiplier unit (VMU) at the proposed regulator’s output. This improvement of the suggested QDBC can be configured in two different ways as shown in Figure 8. The supplementary VMU circuit comprises two capacitive filters, C₄, and two diodes, D₄, that work together with the LC filter [5,11,16].

This study also provides a brief mathematical calculation of the voltage gain for the QDBC regulator with the positive X-bridge filter, which produces a positive voltage at the recommended regulator’s output. The same computation holds for the QDBC with the negative X-bridge filter; however, the generated voltage gain has a negative sign.

It is anticipated that the circuit inductive chokes and the QDBC main switch (MOSFET) will synchronize each diode’s on and off operations. When this switch is on, the diodes D₁, D_3, and D₄ are off, and the inductive chokes (L₁, L_2, L₃, and L) store energy. This implies that the voltage across filter LC is duplicated since the two capacitive filters C₄ of the VMU will be linked in series. Two capacitive filters, C₄ are charged by the energy stored in the inductive chokes L₁, L_2, and L₃; while the switch “S” is off.

As a result of the diodes D₁, D₃, and D₄ being conducting, the capacitive filters of the VMU are charged in parallel. The series-parallel connection of the capacitive filters in the VMU enhances the conversion ratio of the suggested QDBC regulator. The load (R_o L_o) absorbs the discharging energy of capacitive filter C₄ and filter capacitor C, while the inductive choke L₃ stores the discharging energy of capacitive filters C₂ and C₃ in the form of magnetic energy. Moreover, when the main switch is off, the energy from the source and the inductive choke L₁ is stored in capacitive filter C₁, the energy from the inductive choke L₂ is stored in capacitive filter C₂, and the energy from the inductive choke L₂ and the inductive choke L₃ is stored in capacitive filter C₃. The output capacitive filter, C, is charged when switch S is in the on-state; however, when switch S is in the off-state, the output capacitive filter, C, is discharged through the load (R_o L_o).

Through examination of the electrical circuits during the on and off states of the switch “S”, the average voltage across C₃ and L₃ can be determined as follows [5,15,17]:

$$V_x=V_{c3}={\displaystyle \frac{1}{{(1-D)}^2}}{V}_s$$

(7)

When the switch is on, one may write the following for the capacitive filter C₃, inductive choke L₃, X-bridge filter, and filter LC with the voltage, V_o, across the load:

$$v_L=L{\displaystyle \frac{d{i}_L}{dt}}={2V}_{C4}+V_{C2}-V_o$$

(8)

However, when the switch is off, it yields

$$v_L=L{\displaystyle \frac{d{i}_L}{dt}}=V_{C3}-V_{C2}-V_o$$

(9)

The capacitive voltage, V_C4, is given as follows:

$$V_{C4}={\displaystyle \frac{3}{2}}{\displaystyle \frac{1}{{(1-D)}^2}}{V}_s$$

(10)

Equations (9) and (10) can be utilized to calculate the voltage gain of the suggested regulator as follows:

$$\begin{array}{c}{V}_L\left(on\right)+V_L\left(off\right)=0\Rightarrow \\ {(2DV}_{C4}+{DV}_{C2}-{DV}_o)+(V_{C3}(1-D)-V_{C2}(1-D)-V_o(1-D))=0\end{array}$$

(11)

Thus, after substituting for the capacitive voltages in Equation (10) from Equations (4), (5), and (11), it yields

$${\displaystyle \frac{V_o}{V_s}}={\displaystyle \frac{1+3D-2D^2}{{(1-D)}^2}}$$

(12)

The output capacitive filter current, inductive chokes, and critical switch voltage and current waveforms are displayed in Figure 9 and Figure 10 accordingly. The power and efficiency of the suggested QDBC are shown in Figure 10. A step-change in supply voltage causes these waveforms to shift from lower to higher values.

The voltage gain ratio ($V_o/V_s$) of the QDBC with and without a VMU (X-bridge) circuit is shown in Figure 11. The QDBC, in conjunction with the VMU filter, produces a higher voltage gain than the QDBC alone, particularly for high duty ratio D values.

The primary results of the QDBC network with the VMU filter have a greater conversion ratio and a lower voltage demand ratio on the switch in reverse biasing. Due to its distinct circuit design, the QDBC regulator outperforms rival non-isolated traditional step-up regulators by a significant margin [5,15,17,18,19].

2.3. Normalized Inductive Choke Current and Capacitive Filter Voltage Fluctuation

The fluctuation in inductive choke currents of Figure 11 was analyzed and demonstrated in [1] with the following challenges that could arise:

$$\begin{array}{c}\Delta i_{L1}={\displaystyle \frac{D{V}_s}{f{L}_1}}\Rightarrow \Delta i_{L1max}={\displaystyle \frac{V_s}{f{L}_1}}\\ \Delta i_{L2}={\displaystyle \frac{D{V}_{C1}}{f{L}_2}}={\displaystyle \frac{D(1-D)V_s}{f{L}_2}}\Rightarrow \Delta i_{L2max}={\displaystyle \frac{V_s}{4f{L}_2}}\\ \Delta i_{L3}={\displaystyle \frac{D(-v_{C3}-v_{C2})}{f{L}_3}}={\displaystyle \frac{-D{V}_s}{f{L}_3(1-D)}}\Rightarrow \Delta i_{L3max}={\displaystyle \frac{V_s}{4f{L}_3}}\end{array}$$

(13)

As stated in [1], adequate inductance value selection is required to prevent the regulator from functioning in the uninterrupted current mode. Nonetheless, the maximum current fluctuation in Equation (13) determines the best values for each inductance (L₁, L₂, and L₃). To prevent the uninterrupted current mode, the following inductance values are used [20,21,22,23,24]:

$$\begin{array}{c}{L}_{1opt}>{\displaystyle \frac{V_s}{f\Delta i_{L1max}}}\\ L_{2opt}>{\displaystyle \frac{V_s}{4f\Delta i_{L2max}}}\\ L_{3opt}>{\displaystyle \frac{V_s}{4f\Delta i_{L3max}}}\end{array}$$

(14)

Regarding the fluctuation in the capacitive filter voltage, the total normalized fluctuation of the capacitive voltages across capacitive filters C_o, C₂, and C₃ has the same absolute value [1]:

$${fC}_o\Delta V_{Co}={fC}_2\Delta V_{C2}={fC}_3\Delta V_{C3}=D{I}_o=D{\displaystyle \frac{{(1-D)}^2}{1+D}}{I}_s$$

(15)

However, the absolute value of the capacitive voltage fluctuation, $\Delta V_{C1}$ is given as follows:

$${fC}_1\Delta V_{C1}=D\left(1-D\right)I_s=D{\displaystyle \frac{\left(1+D\right)}{1-D}}{I}_o$$

(16)

The greatest value of ${fC}_o\Delta V_{Co}={fC}_2\Delta V_{C2}={fC}_3\Delta V_{C3}$ is attained at $D=0.28$, whereas the maximum of ${fC}_1\Delta V_{C1}$ is reached at $D=0.5$.

Figure 12 depicts the normalized voltage fluctuation across the capacitive filters being investigated. This diagram shows how the fluctuation in voltage decreases when the regulator operates more in the high-conversion ratio area and high-frequency zones. The duty ratio (D), frequency (f), and maximum possible voltage fluctuation ($fC\Delta V_{Cmax}$) should all be considered while designing the capacitive filters. Thus, the maximum voltage fluctuation in Equations (15) and (16) determines the best values for each capacitance (C₁, C₂, C₃, and C_o) as follows:

$$\begin{array}{c}{C}_{1opt}>{\displaystyle \frac{I_s}{4f\Delta V_{C1max}}}\\ {(C}_{2opt}=C_{3opt}=C_{oopt})>{\displaystyle \frac{{3I}_s}{20f\Delta V_{C1max}}}\end{array}$$

(17)

2.4. Tension Demand Ratio (TDR) on the QDBC Essential Switch

The TDR (tension demand ratio) for the QDBC switch is defined as the average voltage across the essential switch in its reverse-bias stage, divided by the supply or load voltage. The TDR on the QDBC main switch without the VMU filter is given based on the above-mentioned analysis as follows:

$${\displaystyle \raisebox{1ex}{$V_{RQDBC}$}\!\left/ \!\raisebox{-1ex}{$V_o$}\right.}={\displaystyle \frac{1}{1+D}}$$

(18)

However, after using the VMU filter, it becomes

$${\displaystyle \raisebox{1ex}{$V_{RMOS\_X}$}\!\left/ \!\raisebox{-1ex}{$V_o$}\right.}={\displaystyle \frac{1}{1+3D-2D^2}}$$

(19)

The TDR of the QDBC essential switch is juxtaposed to that of other DC–DC regulator processors. Thus, according to the analytical calculations described in [11], the tension demand ratio for the essential switch of the SEPIC regulator is [25,26,27].

$${\displaystyle \raisebox{1ex}{$v_{RSEPIC}$}\!\left/ \!\raisebox{-1ex}{$V_o$}\right.}={\displaystyle \frac{1}{D}}$$

(20)

Similar assumptions are made about the essential switch of the buck/boost and traditional step-up regulators, as discussed above [25,26,27]:

$${\displaystyle \raisebox{1ex}{$v_{RBuck\_Boost}$}\!\left/ \!\raisebox{-1ex}{$V_o$}\right.}={\displaystyle \frac{1}{D}}$$

(21)

Based on Equations (18)–(21), Figure 13 relates the TDR of the QDBC essential switch to that of SEPIC, boost, and buck-step-up regulators. This graph depicts how the TDR on the major switches of these regulators rises as the duty ratio D grows.

As D increases, the initially high boost regulator and buck-boost regulator tension demand ratios decrease faster than the QDBC tension demand ratio. However, compared to SEPIC, boost, and buck-boost regulators, QDBC has significantly more power density and capacity, which makes it particularly advantageous for solar PV modules, battery-powered car systems, and alternative energy systems [25,26,27,28,29].

Figure 14 further shows that as D increases from zero to unity, the TDR of QDBC without and with the VMU filter decreases exponentially from one to half. As a result, V_RQDBC and V_{RQDBC_X} decrease in value from equal to the resultant voltage, Vo, to 50% of the output voltage. However, compared to the topology without the X-bridge filter, the tension demand ratio with the VMU filter drops almost monotonously [27].

The authors of this study believe that electrolytic capacitors, which frequently have low parallel resistance and high leakage currents, can be used to lower the tension-demand ratio of QDBC by adding a time constant RC. This would also enhance the power distribution across the main switch S. Parasitic components may considerably impair both dynamic and steady-state performance. However, the effect of parasitic components on the responsiveness of the power stages of the suggested regulator is not covered in this paper [25,26,27,28,29].

3. Harmonic Spectrum of QDBC Regulator

This paper demonstrates the harmonic spectrum components of the output/input voltages and currents of the proposed QDBC regulator under the pulse width modulation technique using the Fourier analysis menu in the PLECS perspective window.

Table 1 shows the regulator’s simulation parameters for this stage of study, except the load, which is simply a 10 Ω resistance.

The distribution pattern of harmonics may be evaluated directly from the analytical results. Certain results are compared to the harmonic spectrum results of other DC–DC regulators, including SEPIC, boost, and buck-boost. The findings provided by this study could be useful for harmonic feature analysis and serve as a reference for harmonic suppression utilizing improved modulation techniques. Furthermore, the suggested approach can be modified to work with different matrix regulator types [13,30,31].

The primary objective of pulse-width modulation as a DC–DC power regulator is to provide a pure, high-quality DC output waveform. However, due to the characteristics of the power devices and modulation methods, the output voltages of DC–DC regulators invariably contain harmonic components, limiting their practical application. As a result, analyzing the harmonic components in the QDBC’s output and input waveforms is critical, as it not only lays the groundwork for harmonic suppression but also improves the regulator harmonic analysis theory [13,30,31].

The Fourier analysis window is used in this paper to display the magnitude of the Fourier coefficients for a specific number of harmonics. The cursors in the range window define the analysis range for Fourier analysis. By default, the cursor range is supposed to be exactly one period of the fundamental frequency; however, this can be adjusted using the Fourier parameters. Spectral leakage effects will be seen if the cursor time range is not an exact integer multiple of the inverse fundamental frequency.

The range of analysis T is always associated with the cursor’s position in the PLECS range. Typically, it is composed of n periods of the fundamental frequency, i.e., $T={\displaystyle \frac{f}{n}}$.

By clicking on the frequency input field, f, the fundamental frequency dialog box appears in the window header. There are two ways to select the fundamental frequency: free cursor placement within the PLECS range and inputting numerical values directly into the fundamental frequency dialog.

If the fundamental frequency is known ahead of time, it can be input right away by choosing a set base frequency. In this approach, the scope cursors are set to the number of base periods. Using the cursors, an analytical range can be selected without modifying the basic frequency.

The following approach is used to determine the Fourier coefficients of a signal with variable sampling intervals, ${\Delta T}_m$.

$$\mathcal{F}\left(n\right)={\displaystyle \frac{2}{T}}{\int }_{T}f\left(t\right)e^{-j{\omega }_{0}nt}dt\approx {\displaystyle \frac{2}{T}}{\sum }_m{\int }_{\Delta T_m}{f}_m\left(t\right)e^{-j{\omega }_{0}nt}dt$$

(22)

where $f_m\left(t\right)=a_{m}t+b_m$ for continuous signals and $f_m\left(t\right)=b_m$ for discrete signals.

Continuous signals are approximated using a piecewise linear approach. In contrast to a Fast Fourier Transformation (FFT), the aforementioned technique works for signals collected at a variable rate.

Figure 15a depicts the steady-state waveforms of the proposed QDBC regulator’s input/output currents and voltages in the uninterrupted current mode (UCM). It is demonstrated that for the given duty ratio $D=0.5$ and supply voltage of 25 V, the average value of I_s is 90 A and of I_o is 15 A, and the load voltage is approximately 150 V. This demonstrates that the simulation is completely consistent with the interpretation of Equation (6).

Figure 15b demonstrates the corresponding harmonic spectra of the input and output currents and voltages of the proposed QDBC regulator in the uninterrupted current mode (UCM) under steady-state and transient conditions. It illustrates the harmonics at frequencies below 1000 Hz, with the harmonic component at 50 Hz having the greatest value of 5.7 V for the load voltage (V_o), 7.74 A for the supply current (I_s), and 0.58 A for the load current (I_o). Thus, the supply current has a harmonic ratio of $7.74/90\times 100\%=8.6\%$, the load voltage has a harmonic ratio of $5.7/150\times 100\%=3.8\%$, and the load current of $0.58/15\times 100\%=3.86\%$. Unlike the supply current, I_s, the other values (V_o and I_o) have insignificant harmonic components [31,32].

The harmonic ratio is defined as the ratio of a periodic DC signal’s highest harmonic component to the average value of the periodic DC signal itself. The harmonic ratio can be thought of as a synonym for the harmonic factor (HF) used with the AC periodic signals. Additionally, this study compares the harmonic spectra of the proposed regulator to those of the boost and SEPIC regulators in UCM modes as they transition from start-up to ultimate quasistationary state.

Hence, Figure 16 shows the steady-state waveform and the harmonic spectrum of the step-up regulator under transient and steady-state conditions in the UCM. This regulator produces lower average currents and voltages than the intended QDBC regulator. Unlike the QDBC regulator, it generates all even and odd harmonics that peak at 50 Hz. Then, the frequency of their occurrence diminishes increasingly until they vanish.

Figure 16a shows that with a switching ratio $D=0.5$ and a supply voltage of 25 V, the average value of I_s is 10 A, I_o is 5 A, and the load voltage is roughly 50 V. Figure 16b displays the harmonics at low frequencies less than 1000 Hz, with the harmonic component at 50 Hz having the highest value of 6.66 V for the load voltage, 2.4 A for the supply current, and 3.37 A for the load current. The supply current has a harmonic ratio of $2.4/10\times 100\%=(24\%)$, the load voltage has a harmonic ratio of $6.66/50\times 100\%=(13.13\%)$, and the load current is $3.37/5\times 100\%=(67.4\%)$. Therefore, unlike the load voltage, the load and supply currents have high and substantial harmonic ratios. The comparison with QDBC shows that the proposed QDBC excels over the step-up regulator in terms of the harmonic spectrum indicator (harmonic ratio).

Figure 17 depicts the steady-state waveform and harmonic spectrum of the SEPIC regulator under transient and steady-state conditions in the UCM. This regulator produces lower average currents and voltages compared to the QDBC regulator. The output voltage and current of this regulator (V_o and I_o), have insignificant harmonic components. The supply current contains unpleasant even and odd harmonics with peak values at 50 Hz. They then decline progressively until they are completely gone at higher frequencies [31,32,33].

Figure 17a shows that with a switching ratio of $D=0.5$ and a supply voltage of 25 V, the average value of I_s is 2.5 A, I_o is 2.5 A, and the load voltage is approximately 25 V. Hence, Figure 16b shows the harmonics at low frequencies less than 1000 Hz, with the greatest value at 50 Hz being 1.9 V for the load voltage, 2.26 A for the supply current, and 1.76 A for the load current. The supply current has a harmonic ratio of $2.26/2.5\times 100\%=(90.4\%)$, the load voltage has a harmonic ratio of $1.9/25\times 100\%=(7.6\%)$, and the load current is $1.76/2.5\times 100\%=(70.4\%)$. Unlike the load voltage, the load and supply currents have a very large harmonic ratio when compared to the suggested QDBC.

The suggested regulator QDBC outperforms all other regulators (SEPIC, buck/boost, and boost) in terms of efficiency, voltage gain, and harmonic content. This study has led to the introduction of a boost-type regulator with excellent characteristics regarding power conversion ratio and current harmonic reduction.

The harmonic generation of the proposed QDBC is a complicated and non-linear problem because of the switch characteristics of electronic components and the link between the AC and DC sides. This issue may occur whether an inverter circuit is used at its output or a rectifier circuit is used at its input.

By employing the proper filters and control strategies, QDBC distortion can be minimized and efficiency raised. To perform an accurate harmonic analysis of QDBC, a mathematical model that can represent the switching characteristics, and the interaction between the AC and DC sides must be developed. When paired with a comprehensive mathematical description, the switch function can be a helpful tool for explaining QDBC in the time domain and power device switching procedures. Simulation tests show that the suggested QDBC regulator architecture eliminates nearly all lower-order harmonics, allowing us to attain a THD or harmonic ratio of less than 10% and a power factor that is closer to unity.

4. Regulation Method of QDBC Regulator

The supply and load currents exhibit low-order input and output current harmonics, as per the harmonic spectra of the suggested QDBC regulator examined in the preceding section. This study presents a unique modulation and regulation technique called the delta modulation current control approach, with and without proportional-integral (PI) regulators to eliminate these low-order harmonics for the input/output currents.

Delta Modulation Current Regulator (DMCR)

Conventional hysteresis current controller (CHCC), ramp hysteresis current-mode controller (RHCC), and controlled bandwidth delta modulation current regulator (DMCR) are the three methods of hysteresis current regulation that are examined in [1,34] for the regulation of DC–DC regulator currents. Since it offers strong regulatory qualities for input/output voltages and currents, as well as high efficiency and quick response, DMCR proves to be the best among them. Moreover, despite these changes in the supply voltage and load resistance, the operating frequency and delta modulation bandwidth are relatively constant.

The real supply and load currents are forced to follow the necessary desired values for supply current and load current, respectively, using the proposed delta modulation current control technique. Two delta modulation current regulators are employed in this configuration to remove the parasitic effects of the suggested regulator as well as the harmonic current components produced at the source and load as a result of the switching technique. The entire setup generates a virtually DC constant current with less ripple and better power factor since the delta modulation regulators allow the QDBC regulator to give the necessary DC current [35,36,37].

The suggested DMCR also uses the derivative of the present actuation error to change the delta modulation bandwidth. This comparison technique determines the proper gate signals for the QDBC regulator active switch by comparing the resulting current error with a predicted delta modulation bandwidth.

The recommended strategy exemplifies the most advanced DMCR method. Therefore, in the off-state of the essential switch, the necessary inductive choke voltage $V_{L1}^{*}$ will be as follows if the current $i_{L1}^{*}$ must flow through the source inductive choke L₁:

$$V_{L1}^{\mathrm{*}}=L_1{\displaystyle \frac{\Delta \left(i_L^{\mathrm{*}}-i_L\right)}{t_{off}}}={\displaystyle \frac{h{L}_1}{t_{off}}}=V_{C1}-V_s\Rightarrow t_{off}={\displaystyle \frac{h{L}_1}{V_{C1}-V_s}}$$

(23)

The prescribed inductive choke current is denoted as $i_{L1}=i_1=i_s$, and the QDBC supply inductive choke current is regulated by the delta modulation window bandwidth, h. The following is the intended inductive choke voltage $V_{L1}^{*}$, when the essential switch is toggled on:

$$V_{L1}^{\mathrm{*}}=L_1{\displaystyle \frac{\Delta (i_{L1}^{\mathrm{*}}-i_{L1})}{t_{on}}}=L_1{\displaystyle \frac{h}{t_{on}}}=V_s\Rightarrow t_{on}={\displaystyle \frac{h{L}_1}{V_s}}$$

(24)

Thus:

$$h(t)=h_{max}{\displaystyle \frac{(V_{C1}-V_s)}{V_{C1}}}=h_{max}(1-{\displaystyle \frac{V_s}{V_{C1}}})$$

(25)

The value of the maximum delta modulation fluctuation bandwidth, $h_{max}={\displaystyle \frac{V_s}{f{L}_1}}$, h_max is related to the mains voltage and inversely related to the regulator’s switching frequency. The average regulator processor switching frequency, power oscillations, losses, and current harmonic distortion are all heavily influenced by bandwidth amplitudes. To obtain the required constant switching frequency and duty ratio, D*, the delta modulation window, h(t), should be chosen as a function of the DC supply voltage, V_s, and the voltage across the capacitive filter, V_C1. The delta modulation bandwidth will likewise be constant if Equation (4) is used to determine that V_C1 is constant.

By rearranging Equations (22) and (23) the regulator switching frequency, $f={\displaystyle \frac{1}{T}}={\displaystyle \frac{1}{t_{on}+t_{off}}}$, could be expressed as follows:

$$f={\displaystyle \frac{V_s(V_{C1}^{\mathrm{*}}-V_s)}{L_{1}h{V}_{C1}^{\mathrm{*}}}}$$

(26)

It is evident that once the necessary voltage, $V_{C1}^{*}$, is selected, the constant value of the switching frequency, f, can be found. The fact that the average inductive choke current value is limited by rate and should ideally equal the commanded current served as the impetus for this approach. This method implies that the required current, $i_{L1}^{*}$, is fully tracked by the source inductive choke current, $i_{L1}$.

Understanding the time derivative of the inductive choke current is essential to this strategy. The time derivative of the inductive choke current is computed using the formulae previously mentioned. The inductive choke current is bounded by

$${\displaystyle \frac{d{i}_1}{dt}}=({\displaystyle \frac{i_{L1}^{\mathrm{*}}-i_{L1}}{T_s}},{\displaystyle \frac{{v_{C1}-V}_s}{L_1}},{\displaystyle \frac{V_s}{L_1}})$$

(27)

In this case, T_s stands for the time constant of the regulator. Selecting T_s requires striking a balance between accuracy, delta modulation bandwidth, and simulation runtime. The regulator bandwidth for the delta modulation current determines the allowed normalized current fluctuation. The user can manage the frequency at which the regulator switch switches on and off and can assess how well it performs at various delta modulation bandwidth values by adjusting the bandwidth. Theoretically, raising the regulator switching frequency could enhance the current waveform. Power electronic devices do have limitations, though, and raising the switching frequency causes additional switching losses, electromagnetic interference issues, and other issues. Finding a balance between these variables is essential when using a switching frequency range.

Equations (21) and (22) can be used to estimate the desired duty ratio D* in the following way:

$$D^{\mathrm{*}}=1-{\displaystyle \frac{hf{L}_1}{V_{C1}^{\mathrm{*}}-V_s}}$$

(28)

or:

$$D^{\mathrm{*}}={\displaystyle \frac{hf{L}_1}{V_s}}$$

(29)

The aforementioned analysis is utilized to calculate the regulator duty ratio, D*, and the regulation steps for this block by creating the average utilizing the AC voltage model of the proposed regulator using the perturbation and linearization approach as follows:

$$\begin{array}{c}{V}_{L1}+v_{L1}=L_1{\displaystyle \frac{d{(I_{L1}+i}_{L1})}{dt}}=\\ =V_s-\left[\left(1-d\left(t\right)\right)\left(V_{C1}+v_{C1}\right)\right]\end{array}$$

(30)

The averaged AC model of the regulator input currents is required to use the delta modulation current regulator to calculate the switched model of the regulator switch.

$$C_1{\displaystyle \frac{d(V_{C1}+v_{C1})}{dt}}=-d\left(t\right){(I_{L2}+i}_{L2})+(1-d\left(t\right)\left[{(I_{L1}+i}_{L1})-{(I_{L2}+i}_{L2})\right]$$

(31)

The duty ratio that is used as a regulation input is

$$d\left(t\right)=D+d$$

(32)

The small-signal AC model parameters are also represented as variable values in small letters in Equations (30) and (31). The following formula for the DC average value of I_L1 and I_L2 can be obtained using Equation (31) [36,37,38]:

$$I_{L2}=\left(1-D\right)I_{L1}={fC}_1{\displaystyle \frac{\Delta v_{C1}}{D}}$$

(33)

Thus, Equations (30) and (31) provide the following transfer functions, presuming that the nonlinear components du(t) can be disregarded and that the derivative of the big signal DC model parameters yields zero values:

$$sL{i}_{L1}\left(s\right)=-\left(1-D\right)v_{C1}\left(s\right)+d\left(s\right)V_{C1}$$

(34)

and:

$$s{C}_1{v}_{C1}\left(s\right)={(1-D)i}_{L1}\left(s\right)-i_{L2}\left(s\right)-d\left(s\right)I_{L1}$$

(35)

From Equation (33), one may obtain

$$i_1\left(s\right)-i_2\left(s\right)=s{C}_1{v}_{C1}\left(s\right)+{Di}_1\left(s\right)+d\left(s\right)I_{L1}$$

(36)

Equations (33) and (34) can be combined to produce the following results:

$${\displaystyle \frac{i_1\left(s\right)}{d\left(s\right)}}={\displaystyle \frac{I_{L1}}{1-D}}+s{C}_1{\displaystyle \frac{V_{C1}}{{\left(1-D\right)}^2}}$$

(37)

and:

$$v_{C1}\left(s\right)={\displaystyle \frac{\left(1-D\right)V_{C1}d\left(s\right)-\left(1-D\right)s{L}_1{i}_1\left(s\right)-s{L}_1{I}_1}{s^2{L}_1{C}_1+{(1-D)}^2}}$$

(38)

One may also write for d(s) the following expression from Equation (38):

$$d\left(s\right)={\displaystyle \frac{[{s^2{L}_1{C}_1+{\left(1-D\right)}^2]v}_{C1}\left(s\right)+\left(1-D\right)s{L}_1{i}_1\left(s\right)+s{L}_1{I}_{L1}}{\left(1-D\right)V_{C1}}}$$

(39)

Figure 18 shows the proposed QDBC regulator with a bandwidth-adjustable delta modulation current regulator (DMCR). Figure 19 illustrates the algorithmic control process that generates the duty ratio, D_a, and AC small signal analysis for the source current, I_s. The regulation algorithmic process for producing the duty ratio, D_b, and AC small signal analysis for the load current, I_o, is shown in Figure 20. Using the regulation technique depicted in Figure 19 and Figure 20, the averaged input voltages and currents are measured to determine the desired load current value. $I_o^{*}$, and the final duty ratio, D, for the proposed regulator. Ω.

Figure 21 and Figure 22 illustrate the switching technique used to generate the gating signals and determine the suggested switching frequency for the regulator main switch. Gating signals for the QDBC regulator’s primary switch are generated by the logic circuits of the adjustable bandwidth delta modulation regulators for source and load currents seen in Figure 21 and Figure 22.

Another way to test the algorithmic regulation process is to monitor how quickly the regulator’s efficiency varies in response to slight variations in the mains voltage and load resistance. Figure 23 shows the voltage, current, power, and efficiency waveforms resulting from the DMCR simulation.

Figure 23a illustrates how the source current and voltage, as well as the load current and voltage, change in tandem with the mathematical equations describing the voltage and current gain of the suggested regulator when the supply voltage and load resistance are changed step-by-step. The optimal range for the increasing time of the regulator source current, I_s, which accounts for both the propagation delay and the time needed for the regulator output to reach its final value, was 0.05 to 0.06 s. The regulator’s peak time was around 0.08 s, and its maximum overshoot was 17.6%.

As seen in Figure 23b, the switching frequency and the DMCR bandwidth were maintained at constant values for every instant. The regulator runs at 10 kHz and has an efficiency of 96–97%.

Figure 24 depicts an additional setup for evaluating the effectiveness of the proposed regulator circuit, as described in [39,40,41,42]. The input and output voltages, I_s, V_s, V_o, and I_o, were simulated using various patterns of loading scenarios and supply voltage levels. The QDBC regulator’s effectiveness was then noted.

As expected, regardless of the supply voltage being low, medium, or high, the recommended regulator exhibited the same high efficiency level for low, medium, and heavy loads. Conduction loss and other losses, which can be the main source of loss under such loads, are ignored while analyzing the efficiency behavior. The highest efficiency was 97% at output load currents of 44 A, 30 A, 22 A, and 16 A.

Figure 25 and Figure 26 display the voltage and current of the primary switch as well as those of the capacitive filters and inductive chokes, respectively. Step variations in the supply voltage and load resistance cause the proposed regulator’s capacitive filters and inductive chokes to modify their voltages and currents accordingly. Additionally, Figure 24a shows how changes in the source voltage and load resistance cause the capacitive and inductive currents and voltages of the proposed QDBC to change consecutively.

With an inaccuracy of about 0.5%, Figure 26a validates the theoretical analysis performed in Equations (5)–(8). It shows that, for a duty ratio of about 52% and a supply voltage of 100 V, the average voltages of capacitive filters C₁, C₂, C₃, and C_o are 208 V, −225 V, 434 V, and 660 V, respectively.

Furthermore, Figure 26b shows how the recommended regulator applies relatively acceptable voltage/current stress to the main switch “S”. Figure 25b also illustrates that the average inductive choke currents of L₂ and L₃ are 108 A and 34 A, respectively, with a supply voltage of 100 V and a duty ratio of roughly 52%. This leads to the conclusion that, given a 0.5% error rate, Equation (11) confirms the theoretical calculations mentioned above. Figure 23, Figure 24, Figure 25 and Figure 26 also show that the efficiency of the QDBC regulator and the voltage and current waveforms are not adversely affected by changes in the source voltage and load resistance. Furthermore, these results show that even when the supply current operates within the nonlinear variation range of the source voltage and load resistance, there are no indications of transient interruptions. It still follows its reference current quite closely. The resulting regulator’s switching duty ratio results in a duty ratio of 52% and an output voltage variation between 330 V and 660 V after the source voltage fluctuates between 50 V and 100 V.

As a result, the QDBC regulator-based DMCR technology offers robust regulation features for variations in input voltage and load resistance. Both light and large weights can be handled with excellent efficiency. Moreover, despite these changes in the supply voltage and load resistance, the operating frequency and delta modulation bandwidth are relatively constant. Additionally, the efficiency is nearly constant when the input voltage and the load’s resistance rise at the same pace. It is reasonable to say that, out of all the delta modulation current regulators covered above, the DMCR regulation strategy is the most successful regarding regulator dynamic performance, rising time, delaying response, efficiency, and sensitivity to parameter variation. The importance and superiority of the DMCR delta modulation current technique over the other delta modulation methods previously discussed may be verified through simulation and outcomes. The method is simple to apply and does not require knowledge of the system’s characteristics, except for the quick reaction of the current loop and peak-to-peak current normalized oscillation limitations [22,23,24,25].

5. The Frequency Response of the Recommended QDBC Regulator

An effective way to assess the performance of the proposed regulator is to look at the frequency response of the control loop. A Bode plot can be used to show how the phase angle and log-magnitude curve behave against frequencies. Two sets of the typical Bode plots are displayed in Figure 27 and Figure 28 to illustrate the bandwidth range, any apparent resonances, and the system’s stability in terms of phase and gain margin.

Figure 27 shows that the bandwidth of the investigated regulator is around 500 Hz. As a result, whether powered by an alternating current source via a rectifier circuit or by a DC source via PV solar panels, the investigated regulator, QDBC, may behave unpleasantly and produce very high first, second, and third-order harmonics. The open-loop system for the voltage gain may be stable and has a phase margin of roughly 45 degrees. However, as the phase angle shifts from positive 18° to negative 18°, the open loop may oscillate somewhere between 50 kHz and 100 kHz.

Figure 28 shows that the current slope gain increases by −40 dB/dec at 300 Hz from −20 to −60 dB/dec after rolling off at 50 Hz from 0 dB/dec to −20 dB/dec. This results from the generation of one real pole at 50 Hz and two complex conjugate poles at 300 Hz, respectively. The generation of a simple zero causes the slope to decline by +20 dB/dec to become −40 dB/dec at 600 Hz. The two-slope roll-off is mostly caused by the output L₃/C₃ filter and is largely reliant on the equivalent series resistive parts of the regulator’s load, output capacitive filter C_o.

Furthermore, the phase angle between the supply entering and load resultant currents abruptly shifts from nearly negative 90 degrees to positive 90 or 135 degrees at a frequency of 300 Hz, then returns to negative 90 degrees at 600 Hz, according to the output-to-input current gain Bode diagrams.

The poles of the system tend to increase the overshoot of the step response at 400 Hz since they are close to the imaginary axis. Nonetheless, the literature [30,31,32] shows that the overshoot is reduced if the zeroes are shifted farther from the actual portion of the poles. Consequently, it is advisable to employ a PI regulator that suitably maintains stability, pushes the zeroes and the poles farther from the imaginary axis, and enforces positive values on the phase margin. Therefore, the design of a PI regulator as a lead/lag compensator is necessary to increase the system bandwidth and provide system stability around these frequency values. The regulator’s integral gain is set higher than the proportional gain, utilizing the current PI regulator of the QDBC regulator.

The interesting outcome of utilizing the delta modulation current regulator in combination with the PI regulator is the removal of nonlinearity and unknown disturbances in the current and voltage gains, aside from the disagreeable harmonic component that manifests in the supply current at 400 Hz.

The step response of the open-loop system suggests that the proposed converter has low stability but a fast response. After converting an open-loop system into a closed system, a gain was applied until the step input generated a continuous oscillation.

The trial-and-error tuning method was used to tune the PI controller. In this strategy, the proportional action, which is the primary control, is refined by the integral action while the derivative control action is kept at zero value. Thus, the integral and derivative actions are kept to a minimum while the controller gain, k_p, is changed until the desired result is achieved.

Figure 29 and Figure 30 display the resulting Bode diagram of the suggested regulator with the PI current regulator and the delta modulation current regulator. The PI current regulator was adjusted using the trial-and-error technique. The gain values for the proportional regulation component and the PI current integral are $k_i=40$, and $k_p=4$, respectively.

Figure 29 shows that the QDBC system is stable concerning the voltage gain since the zero crossing of 0 dB occurred at a phase margin of positive $-45°+180°=135°$. Furthermore, the gain margin at the negative 180° crossing is approximately 40 dB and greater than zero.

The QDBC system is also stable concerning the current gain, as demonstrated by Figure 30, since the zero crossing of 0 dB took place at a phase margin of positive $-22.5°+180°=167.5°$. Additionally, there is about an 80 dB gain margin at the −180° crossing.

6. Experimental Implementation of the Proposed Regulator QDBC

The hardware test bench for the suggested regulator QDBC is shown in Figure 31.

Table 2. QDBC design specifications.

Parameter	Symbol	Real Value	Type
Step Input Voltage	Vs	(50–100) V	Power supply Haneef
Inductive choke	L1	2.3 mH	T-5817-10 interference inductive choke Treadmill 6 A inductance, Shenzhen, China
Inductive choke	L2	2.3 mH	T-5817-10 interference inductive choke Treadmill 6 A inductance, Shenzhen, China
Inductive choke	L3	2.2 mH	Leybold 56213, $N=250,R=0.6\mathrm{\Omega }$, 5 A, Shenzhen, China
Capacitive filter	C1	220 μF	Electrolytic Capacitive filter, 250 V, Shenzhen, China
Capacitive filter	C2	220 μF	Electrolytic Capacitive filter, 250 V, Shenzhen, China
Capacitive filter	C3	150 μF	Electrolytic Capacitive filter, 250 V, Shenzhen, China
Capacitive filter	Co	470 μF	Electrolytic Capacitive filter, 250 V, Shenzhen, China
Load resistance	Ro and Lo	250 W	PFC XT4800-1, Class B, Shenzhen, China
Diodes	D1 and D2	$V_{RRM}=200\mathrm{V}$ $I_F=60\mathrm{A}$	F60UP60DN, Shanghai, China
Diodes	D3 and D4	$V_{RRM}=200\mathrm{V}$ $I_F=30\mathrm{A}$	F60UP20DN, Shanghai, China
Transistor	MOSFET	$V_{DSS}=200\mathrm{V}$ $R_{DS}\left(on\right)=0.04\mathrm{\Omega }$ $I_D=50\mathrm{A}$	IRFP260N, HEXFET, Power MOSFET, Shenzhen, China
Switching frequency	f	20 kHz	Arduino UNO, Shenzhen, China

lists the experimental 40 W model’s technical specifications. Figure 32 and Figure 33 highlight the outcomes of the QDBC using the experimental setting.

The specs specify a resistive inductive load of 40 W, an input value of 9.5 V following the removal of the nearly 0.5 V voltage drop caused by the circuit and power connection, and a switching frequency of 10 kHz. The analysis of the test findings revealed that when operating at a 50% duty ratio, the QDBC displayed a voltage gain of almost six times and eight times when operating at a duty ratio of 60%. According to the calculations and mathematical analysis of the proposed regulator, the output voltage generated by QDBC at the specified duty ratios—30%, 50%, and 60%—should be 25.2 V, 57 V, and 95 V, respectively. Given this, the regulator has an excellent efficiency of almost 92–94%, as the experimental results recorded in Figure 32 and Figure 33, along with the video published with this article, illustrate. The output current is determined by measuring the voltage across a resistor:

• An output voltage of 52 V (yellow) and output current of 1.5 A (blue) at a switching ratio $D=0.5$ when supplying a 12–34 V, 2400RPM High Speed Micro DC Motor;
• An output voltage of 92 V (yellow) and an output current of 1.8 A (blue) at a switching ratio $D=0.6$ when supplying a highly inductive resistive load of 3.3 mH and 200 Ω;
• An output voltage of 25 V (yellow) and an output current of 1.5 A (blue) at a switching ratio $D=0.3$ when supplying a highly inductive resistive load of 3.3 mH and 200 Ω.

Moreover, in comparison to the voltage generated at the output, the main transistor’s (MOSFET) voltage tension (strain), as depicted in Figure 33, is within the specified range at roughly 17 V (blue).

The QDBC is a relatively recent development in the powerful-gain DC–DC regulator market because of its unique voltage gain features. The remarkable ability of the QDBC to alter the relationship between input and output voltage makes it promising for applications that need specific voltage profiles.

This works in a different way than traditional step-up regulators, which usually use linear voltage gain. These regulators’ improved dependability and reduced output fluctuation have become well known.

The proposed regulator (QDBC) is programmed using an Arduino UNO and a function generator to operate at a switching ratio $D=0.3$ and frequency of 20 kHz while producing

• An output voltage of 52 V (yellow) and an output current of 1.5 A (blue);
• An output voltage of 91 V (yellow) and an output current of 1.8 A (blue);
• An output voltage of 26 V (yellow) and an output current of 1.5 A (blue).

7. Conclusions

This paper describes the performance of the novel powerful-gain quadruple-diode boost regulator (QDBC) for PV generation and electric drive systems. It also discusses the main challenges and benefits of the proposed regulator with and without a voltage multiplier unit.

The proposed regulator without a voltage multiplier unit (VMU) has a voltage gain of ${\displaystyle \frac{V_o}{V_s}}={\displaystyle \frac{(1+D)}{{(1-D)}^2}}$; however, the voltage gain of the proposed regulator with the VMU filter becomes ${\displaystyle \frac{V_o}{V_s}}={\displaystyle \frac{1+3D-2D^2}{{(1-D)}^2}}$. The problem of increasing voltage stress on the active and passive switches is resolved by adding an output RL filter with a voltage multiplier unit (VMU) at the output of this regulator.

Additionally, the recommended regulator provides a greater voltage gain than the SEPIC, the conventional, or the quadratic step-up regulator. The comparison investigation confirms that the QDBC is more advantageous than those regulators, especially for high-power renewable energy systems, electric vehicles, and solar panels.

The technical measures used for comparison include the mean value, rectified mean value, RMS value, crest factor, fluctuation factor, harmonic factor, and harmonic content distortion. It turns out that the proposed regulator QDBC is a better version for the aforementioned applications than the DC–DC regulator versions mentioned above. It has the best input/output power response, the lowest fluctuation factor, the least amount of harmonic spectrum composition, the highest output efficiency, a power factor that is nearly equal to unity, less normalized current fluctuation, and better overall dynamic performance.

This study also examines a frequency response and harmonic spectrum to counteract harmonics caused by switching methods and non-linear parasitic elements in the regulator architecture. The proposed harmonic reduction approach has been implemented using a delta modulation current regulation technique known as a delta modulation current regulator (DMCR).

As a backup option, the controlled delta modulation current regulator with a PI regulator is also employed to maximize the suggested regulator’s dynamic behavior. Throughout this study, it was demonstrated that the dynamic properties of the QDBC with the DMCR and PI current regulator are better than any alternative delta modulation or hysteresis approaches.

PLECS and ANSOFT Simplorer software were used to perform the stability analysis and obtain the relevant Bode plots to examine the performance of the derived converter in both open-loop and closed-loop scenarios. The controller was designed, and the closed-loop performance was assessed by trial-and-error adjustment. The gain and phase plots of the system obtained using the Bode diagrams justify that the suggested delta regulation can be easily implemented.

According to a simulation study performed in MATLAB/PLECS, we may use this design to eliminate almost all lower- and higher-order harmonics and obtain a stable system with optimal values for harmonic content metrics like THD, Crest factor, and harmonic factor.

The conventional and ramp hysteresis current-mode control method shows a THD of 8% and efficiency of 96%, whereas the controllable hysteresis current technique with PI current regulator depicts 7.2% and efficiency of 97%.

The conventional and ramp hysteresis current-mode technique described in [1] has a THD of 8% and an efficiency of 96%. In contrast, the proposed delta modulation technique with a PI current regulator achieved a THD of 7.2% and an efficiency of 97%.

ANSOFT/Simplorer 7 and Simulink/MATLAB 2021a or MATLAB/PLECS 4.9.5 software were used for simulation purposes, and the total investigation was analyzed for all investigated methods.

The hardware prototype for the proposed model was constructed following a comprehensive steady-state analysis, as detailed in the Supplementary Materials.

A controlled laboratory setting was used to design and evaluate the suggested regulator to assess its performance. The proposed regulator can effectively raise the voltage level, making it a key component of sustainable power generation, and electric vehicles can be incorporated into these systems to maximize energy use.

The authors of this study encountered challenges while conducting their research. These difficulties can be summed up as a limitation in the ability to test the practical component with greater precision due to the laboratory conditions in which we carried out the experiments. The laboratory has limited capacity and lacks the necessary equipment and measurement technology to retain information and some results while performing operations on specific data. Furthermore, for safety reasons, the lab staff oppose the use of higher currents and voltages.

Our goal for future work is to request funding from Zarqa University to fulfill the ambitions and expectations of the proposed project. The proposed QDBC regulator can be combined with a frequency inverter to operate a magnet-supported synchronous reluctance motor that functions as a water pump in the University’s irrigation system, thereby achieving a special fund.

Thus, the future of this work is being shaped by two key factors: the growing incorporation of sophisticated technology and AI in labs and the expansion of the definition of the workplace to include new system components and fundamental aspects of this work.