Quantitative Analysis of Balancing Range for Single-Phase 3L-NPC Converters

Abstract

Multiple techniques have been suggested to achieve control balance in single-phase three-level neutral-point clamped (3L-NPC) converters. Nevertheless, there is a deficiency of quantitative calculations related to the extent of balancing. Operating beyond the balancing range may result in a sequence of safety incidents. This paper presents a conceptualization of the 3L-NPC converter as two cascaded H-bridges. By employing power conservation principles, the balancing range for the NPC converter is derived, and two novel methods are investigated to broaden the balance range in accordance with the calculated balance range. A comparison is made among the balancing ranges under different balancing control methods. This study establishes a theoretical foundation to ensure the secure and stable operation of the NPC converter.

1. Introduction

Carbon dioxide (CO₂) emissions have substantial environmental consequences, as they contribute to climate change and global warming. Multilevel converters are increasingly crucial in mitigating CO₂ emissions in sectors such as automotive [1,2] and electrical power [3]. In 2021, transportation and electric power sectors in the United States were responsible for 38% and 33% of energy-related emissions, respectively [4]. The combustion of conventional petroleum fuels in automotive internal combustion engines generates CO₂. Moreover, compared to traditional gasoline vehicles, electrified vehicles, like hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs), and electric vehicles (EVs), markedly reduce fuel consumption, leading to a significant decrease in tailpipe CO₂ emissions [5]. Power electronics is increasingly vital in electrified vehicle applications, offering compact and highly efficient solutions for power conversion tasks, such as motor control and conversion between high-voltage and low-voltage batteries [6]. Similarly, the electric power sector is adopting renewable energy systems to reduce reliance on fossil fuels for electricity generation [7], with power electronic converters commonly employed in wind energy and photovoltaic (PV) systems [8].

The 3L-NPC converter, as a type of multilevel converter, is widely applied in various industrial sectors, including high-speed railway traction [9,10], photovoltaic systems [11,12], and power factor correction [13]. However, the imbalance in the voltage of the dc capacitors poses operational challenges for the converter. This imbalance arises from factors like variations in circuit component characteristics and non-ideal properties of switching devices [14]. The uneven voltages across the capacitors result in distortion in the waveforms of the ac voltage and current and also increase the risk of over-voltage damage to the switching devices and clamping diodes [15,16,17,18,19]. Therefore, it becomes imperative to ensure equal voltages across the dc link capacitors and expand the balance range of the topology.

Currently, various methods have been proposed and proven effective for balancing the dc voltage in single-phase 3L-NPC converters. These methods can be classified into hardware approaches utilizing auxiliary balancing circuits [16] and modulation methods employing redundant switching states [20,21,22,23,24,25,26,27,28,29,30,31,32,33]. In reference [16], a passive RLC circuit connected in parallel to the load is introduced, allowing additional current flow. A coordinated modulation strategy was developed to generate harmonics at half the switching frequency in the ac voltage and dc link capacitor currents. Modulation methods have garnered more research attention due to their advantage without adding extra devices. Redundant switching states produce the same output voltage level but have different effects on the charge and discharge of the two dc link capacitors. Some researchers modify the duration of the redundant states [20,21,23,24,27,28,30,33] while others select one redundant state from a pair based on the polarity of voltage and current variables [22,25,26,29,31,32,33]. Both of these strategies are intended to reassign the charging and discharging times of the two capacitors, thereby altering the voltages across the two capacitors.

However, when the load imbalance increases significantly, or under extreme operating conditions, these balancing control methods may fail to maintain the desired voltage balance. Thus, it is essential to derive the balancing ranges under different balancing control methods. Nevertheless, quantitative calculations to determine the balance range of the single-phase 3L-NPC converter are currently lacking.

Several studies have examined the balance range of other multilevel converters. In reference [34], the balance range for the four-level diode-clamped converter is proposed based on a parameter related to midpoint currents. Yet, this method is unsuitable for sinusoidal pulse width modulation and entails complex mathematical calculations. The balance range for the three-phase 3L-NPC converter is presented in the form of a power ratio in reference [35], but the method for calculating the maximum injected dc voltage bias is restricted to an additional balance circuit. Reference [36] addresses the balance range through a vector diagram for the two-cell cascaded H-bridge rectifier. Nonetheless, this method does not elaborate on the extension of the balance range. Each redundant switch state affects the voltages of both capacitors simultaneously, making it challenging to establish a direct relationship between individual capacitor voltages and modulation signals, thus complicating the computation process. Therefore, there is a need for analysis to determine the balance range of these balance control techniques in the single-phase 3L-NPC converter.

In addition to the aforementioned studies, there have been investigations into various application scenarios of the single-phase 3L-NPC converter, with a focus on different equivalent loads and specific balance issues. Some researchers have utilized a single equivalent dc load and primarily examined the initial voltage imbalance between capacitors [20,21,22,25,26,30]. To simulate asymmetry in the capacitance parameters, a few researchers have introduced an additional resistance in parallel with one of the dc link capacitors [23]. Others have studied the imbalance in capacitor voltages during inverter operation [24,27,29,31,32,33]. A two-equivalent-load topology that represents a typical traction drive unit in high-speed railway trains is investigated in reference [28]. In this topology, the single-phase 3L-NPC converter is connected to an inverter–motor system comprising a three-phase 3L-NPC inverter and four traction motors [28]. The two-equivalent-load topology in [28] experiences the most significant pressure in terms of dc voltage imbalance and is also used to validate the effectiveness and robustness of the proposed voltage balancing technique in [20]. Therefore, the two unbalanced equivalent loads are also adopted by this article for analysis.

The main contribution of this article lies in the conceptualization of the single-phase 3L-NPC converter as a two-unit cascaded H-bridge system. By applying the principle of power conservation, this study introduces the concept of the balance range for the single-phase 3L-NPC converter, investigates two novel approaches to expand the balance range, and performs a comparative analysis of this range using various balancing control methods. These findings establish a theoretical foundation for ensuring the secure and stable operation of single-phase 3L-NPC converters.

The rest of this article is organized as follows. In Section 2, the operational principles and the criteria for design balancing methods of the single-phase 3L-NPC converter are provided. In Section 3, the voltage balancing range is calculated. In Section 4, the balancing capabilities of two typical methods are clarified and two novel methods are explored to extend the balance range. The balancing abilities of these methods are compared in Section 5. In Section 6, the effectiveness of the proposed methods is verified through simulation results, followed by a conclusion in Section 7.

2. System Description

In this section, a brief description of the operational principles of the single-phase 3L-NPC converter is provided. The reasons behind DC voltage imbalance are explored and the criteria used for designing balancing methods are analyzed.

2.1. Operational Principles

The simplified topology of the single-phase 3L-NPC converter is shown in Figure 1, which consists of two legs, “Leg a” (S_a1, S_a2, S_a3, S_a4) and “Leg b” (S_b1, S_b2, S_b3, S_b4). u_s, u_ab, and u_dc represent the ac source voltage, the voltage of the converter on the ac side, and the total dc voltage, respectively. L represents the equivalent inductance on the ac side, while the ac side equivalent resistance is neglected [28]. i_s is the ac current. i_p, i_n, i_o, and i_r are the currents on the dc side. The resistors R₁ and R₂ are equivalent loads. u₁ and u₂ are the voltages of the dc link capacitors C₁ and C₂, respectively. The LC filter is responsible for filtering out second-order harmonics in the dc voltages.

The conventional modulation strategy employed in 3L-NPC converters is illustrated in Figure 2. The switching functions (S_a and S_b) are produced by the comparison between the reference voltages of “Leg a” and “Leg b” (u_ao.r and u_bo.r) and the triangle carriers (C+ and C−). The switching functions (S_a and S_b) for the two legs are determined based on the outcomes of comparisons, which can be expressed as follows:

$$S_i(i=\mathrm{a}\mathrm{or}\mathrm{b})=\left\{\begin{array}{cc}1& u_{\mathrm{io}.\mathrm{r}}>C+\\ 0& C-\le u_{\mathrm{io}.\mathrm{r}}\le C+\\ -1& u_{\mathrm{io}.\mathrm{r}}<C-\end{array}\right.$$

(1)

where T_s is the cycle of the triangle carriers and also the switching cycle.

When the switching function S_i (i = a or b) is 1, the switches S_i1 and S_i2 are activated; when S_i (i = a or b) equals 0, the switches S_i2 and S_i3 are activated; when S_i (i = a or b) equals to −1, the switches S_i3 and S_i4 are activated.

Reference voltages (u_ao.r and u_bo.r) can be expressed as follows:

$$\left\{\begin{array}{c}{u}_{\mathrm{ao}.\mathrm{r}}=u_{\mathrm{ref}}\hfill \\ u_{\mathrm{bo}.\mathrm{r}}=-u_{\mathrm{ref}}\hfill \end{array}\right.$$

(2)

where u_ref is the reference voltage of u_ab. And u_ref is between 0 and 1.

The frequency “f_s” of triangle carriers is significantly higher than the fundamental frequency of the converter (f₁). u_ao.r and u_bo.r can, therefore, be treated as constant throughout each individual switching cycle “T_s”.

Based on the aforementioned modulation principles, when 0 ≤ u_ref ≤ 0.5, switching states (S_a, S_b) = (1, 0), (0, −1), and (0, 0) are involved in a T_s, as depicted in Figure 2a. When the ac current i_s flows from node a to node b, the equivalent circuits for the three states are shown in Figure 3. The gray elements are where i_s does not pass by. Sometimes, i_s flows through the diode connected in parallel with a switch, although the switch is activated. It depends on the direction of i_s, for the turn-on condition for IGBT requires the gate voltage to exceed the threshold voltage and the gate current to be sufficiently large, while maintaining the correct polarity. If i_s flows from node b to node a, the equivalent circuit can be figured out in a similar way.

As illustrated in Figure 2b, two similar triangles are utilized in the calculation of the switching states durations. The time intervals corresponding to (S_a, S_b) = (1, 0), (S_a, S_b) = (0, −1), and (S_a, S_b) = (0, 0) within a cycle are denoted as T_{(1, 0)}, T_{(0, −1)}, and T_{(0, 0)}, respectively. Similarly, the durations of other switching states can be obtained.

2.2. Mathematical Model

By utilizing S_a and S_b, the currents i_p, i_n, and i_o can be expressed as [20]

$$\left\{\begin{array}{c}{i}_{\mathrm{p}}=\frac{(S_{\mathrm{a}}-S_{\mathrm{b}})(S_{\mathrm{a}}+S_{\mathrm{b}}+1)}{2}\cdot i_{\mathrm{s}}\hfill \\ i_{\mathrm{n}}=\frac{(S_{\mathrm{a}}-S_{\mathrm{b}})(S_{\mathrm{a}}+S_{\mathrm{b}}-1)}{2}\cdot i_{\mathrm{s}}\hfill \\ i_{\mathrm{o}}=i_{\mathrm{p}}+i_{\mathrm{n}}\hfill \end{array}\right.$$

(3)

Once the entire system reaches a steady state, the rate of the dc voltages across R₁ and R₂, (u₁ and u₂) becomes zero. Consequently, based on Kirchhoff’s current law (KCL), the average value of current i_r within T₁ is equal to the average of i_o, denoted as ${\overline{i}}_{\mathrm{o}}$. By substituting the durations of switching states into (3), ${\overline{i}}_{\mathrm{o}}$ can be obtained as follows:

$${\overline{i}}_{\mathrm{o}}=\frac{1}{T_1}{\displaystyle {\int }_{T_1}\left(S_{\mathrm{a}}^2-S_{\mathrm{b}}^2\right)\cdot i_{\mathrm{s}}\mathrm{d}t}=0$$

(4)

Based on Equation (4), the equivalent loads R₁ and R₂ operate in series and share the voltage. Therefore, the signs of (u₂ − u₁) and (R₂ − R₁) are identical, and this can be expressed as follows:

$$\mathrm{sgn}(u_2-u_1)=\mathrm{sgn}(R_2-R_1)$$

(5)

where sgn(.) is a sign function. This “series voltage sharing” situation results in the imbalance of dc voltages on the two equivalent loads.

Figure 4a depicts the equivalent circuit of the system from the ac side, while Figure 4b presents the vector diagram of the ac voltages. The voltage across inductor L is denoted as u_L. The equivalent voltage vectors of dc loads R₁ and R₂ are represented as u_ab1 and u_ab2, respectively. The phase offset between u_ab and u_s is denoted as φ, and θ represents the phase difference between i_s and u_s. The vectors in Figure 4b can be expressed as follows:

$$\left\{\begin{array}{c}{u}_{\mathrm{s}}=U_{\mathrm{s}}\cos ({\omega }_{1}t)\hfill \\ u_{\mathrm{ab}}=S_{\mathrm{ab}}\cdot u_{\mathrm{dc}}=U_{\mathrm{ab}}\cos ({\omega }_{1}t-\phi )\hfill \\ i_{\mathrm{s}}=I_{\mathrm{s}}\cos ({\omega }_{1}t-\theta )\hfill \end{array}\right.$$

(6)

where U_s, U_ab, and I_s are the magnitudes of u_s, u_ab, and i_s, respectively. ω₁ is the fundamental angle frequency. S_ab is the ideal switching function of the circuit. u_dc is the dc voltage.

2.3. Voltage Balancing

The following analysis is based on the ideal conditions.

The reference voltages and switching functions, $u_{\mathrm{ao}.\mathrm{r}}^{\mathrm{con}}$, $u_{\mathrm{bo}.\mathrm{r}}^{\mathrm{con}}$, $S_{\mathrm{a}}^{\mathrm{con}}$, and $S_{\mathrm{b}}^{\mathrm{con}}$, can be expressed in (7) during the voltage balancing process.

$$\left\{\begin{array}{c}{S}_{\mathrm{a}}^{\mathrm{con}}\approx u_{\mathrm{ao}.\mathrm{r}}^{\mathrm{con}}=u_{\mathrm{ref}}+d_{\mathrm{z}}\hfill \\ S_{\mathrm{b}}^{\mathrm{con}}\approx u_{\mathrm{bo}.\mathrm{r}}^{\mathrm{con}}=-u_{\mathrm{ref}}+d_{\mathrm{z}}\hfill \end{array}\right.$$

(7)

where d_z is the offset voltage.

Substituting (7) into (3), the currents i_p and i_n can be expressed as

$$\left\{\begin{array}{c}{i}_{\mathrm{p}}=u_{\mathrm{ref}}(2d_{\mathrm{z}}+1)\cdot i_{\mathrm{s}}\\ i_{\mathrm{n}}=u_{\mathrm{ref}}(2d_{\mathrm{z}}-1)\cdot i_{\mathrm{s}}\end{array}\right.$$

(8)

The current i_o can be described as

$$C\left(\frac{\mathrm{d}{u}_1}{\mathrm{d}t}-\frac{\mathrm{d}{u}_2}{\mathrm{d}t}\right)+\frac{u_1}{R_1}-\frac{u_2}{R_2}=i_{\mathrm{o}}$$

(9)

By applying i_o from (3) and (8) into (9), the offset voltage d_z is given by the following equation:

$$d_{\mathrm{z}}=\left|\frac{U_{\mathrm{dc}}^{*}\left(R_2-R_1\right)}{8R_1{R}_2{u}_{\mathrm{ref}}{i}_{\mathrm{s}}}\right|\mathrm{sgn}(u_{\mathrm{ref}}{i}_{\mathrm{s}})\cdot \mathrm{sgn}(R_2-R_1)$$

(10)

where $U_{\mathrm{dc}}^{*}$ represents the rated value of u_dc.

However, (10) is not applicable in cases where the unbalanced equivalent loads are unknown. To solve this problem, the voltage balance control is designed as illustrated in Figure 5. In this control scheme, the difference between u₂ and u₁, denoted as Δd, is processed by a PI regulator, and d_z is calculated based on Δd. Since passing through a PI regulator does not alter the sign of a variable, Δd and (R₂ − R₁) share the same signs. Therefore, the sign of d_z in (10) can be described as follows:

$$\mathrm{sgn}(d_{\mathrm{z}})=\mathrm{sgn}(u_{\mathrm{ref}}{i}_{\mathrm{s}}\Delta d)$$

(11)

As depicted in Figure 5, the rectifier control strategy employed in this article utilizes a dual closed-loop PI control strategy. During the voltage balance control stage, various control methods can be introduced to enhance the range of voltage balancing based on Formula (11).

3. Quantitative Analysis of Voltage Balancing Range

In this section, the single-phase 3L-NPC converter can be represented as a two-unit H-bridge. Based on this configuration, the calculation of the maximum level of dc load imbalance and balance range are elaborated by the vector diagram.

3.1. The Two-Unit H-Bridge Equivalence

As depicted in Figure 1, the active power absorbed by the loads in a T₁ can be expressed as follows:

$$\left\{\begin{array}{c}{P}_1=\frac{1}{T_1}{\displaystyle {\int }_0^{T_1}{u}_1}\cdot i_{\mathrm{p}}\mathrm{d}t=\frac{1}{T_1}{\displaystyle {\int }_0^{T_1}(\frac{1}{2}{U}_{\mathrm{dc}}^{*})}\cdot i_{\mathrm{p}}\mathrm{d}t\hfill \\ P_2=\frac{1}{T_1}{\displaystyle {\int }_0^{T_1}{u}_2}\cdot (-i_{\mathrm{n}})\mathrm{d}t=\frac{1}{T_1}{\displaystyle {\int }_0^{T_1}(\frac{1}{2}{U}_{\mathrm{dc}}^{*})}\cdot (-i_{\mathrm{n}})\mathrm{d}t\hfill \end{array}\right.$$

(12)

where P₁ and P₂ are the active powers absorbed in a fundamental cycle “T₁” by R₁ and R₂, respectively.

As depicted in Figure 6, node “o” is divided into two separate nodes, “o₁” and “o₂”. To decouple u₁ and u₂, the adopted rectifier is replaced with a two-unit H-bridge shown in Figure 6, which shares the same external voltage–current characteristics. The first submodule, referred to as unit_1-v, consists of four switches (S_a1, S_a2, S_a3, S_a4) and four diodes, while the second submodule, known as unit_2-v, comprises four switches (S_b1, S_b2, S_b3, S_b4) and four diodes. The input ac voltages of submodules unit_1-v and unit_2-v are u_1-v and u_2-v, respectively. S_a and S_b are the switching functions for unit_1-v and unit_2-v, respectively.

The active powers P₁ and P₂ in (12) represent the input active powers consumed by unit_1-v and unit_2-v, respectively. These active powers can be expressed in terms of u_1-v and u_2-v as follows:

$$\begin{array}{l}{P}_1=\frac{U_{1-\mathrm{v}}{I}_{\mathrm{s}}\cos ({\phi }_1^{\mathrm{con}}-\theta )}{2}\\ P_2=\frac{U_{2-\mathrm{v}}{I}_{\mathrm{s}}\cos ({\phi }_2^{\mathrm{con}}-\theta )}{2}\end{array}$$

(13)

where I_s, U_1-v, and U_2-v are the magnitudes of i_s, u_1-v, and u_2-v, respectively. ${\phi }_1^{\mathrm{con}}$ and ${\phi }_2^{\mathrm{con}}$ are the phase angles of u_1-v and u_2-v, respectively. θ is the phase angle of i_s.

In the H-bridge converter, the peak magnitude of the input ac voltage is lower than that of the dc voltage. As a result, U_1-v and U_2-v are bound by the following additional constraints:

$$\left\{\begin{array}{l}0<U_{1-\mathrm{v}}\le 0.5U_{\mathrm{dc}}^{*}\\ 0<U_{2-\mathrm{v}}\le 0.5U_{\mathrm{dc}}^{*}\end{array}\right.$$

(14)

The total input active power of the adopted rectifier is derived as follows:

$$P_{\mathrm{total}}=\frac{U_{\mathrm{ab}}{I}_{\mathrm{s}}\cos (\phi -\theta )}{2}$$

(15)

3.2. Deriving the Voltage Balancing Range

The smaller resistor between the two equivalent loads is denoted as “R_min” and the larger one is referred to “R_max”. The level of dc load imbalance, denoted as λ, is defined as follows:

$$\lambda =\frac{\frac{1}{R_{\min }}}{\frac{1}{R_{\min }}+\frac{1}{R_{\max }}}$$

(16)

In (16), as the level of imbalance between the two equivalent loads increases, the value of λ also increases, serving as an indicator of the internal dc load imbalance.

For convenience in analysis, we assume that “R₁” represents “R_min” and “R₂” represents “R_max”. Consequently, R₁ consumes more than half of the total input active powers, expressed as follows:

$$\frac{1}{2}{P}_{\mathrm{total}}\le P_1\le P_{\mathrm{total}}$$

(17)

In the ideal balance control range of the selected rectifier, u₁ and u₂ converge to $U_{\mathrm{dc}}^{*}$/2. As a result, the dc load imbalance level “λ” can be expressed as follows:

$$\lambda =\frac{P_1}{P_{\mathrm{total}}}$$

(18)

By referring to (17) and (18), an approximate range of λ can derived as 0.5 < λ < 1.

Substituting (8) into (12), the active power absorbed by the R_min in a cycle can be expressed as follows:

$$P_1=\frac{1}{T_1}{\displaystyle {\int }_0^{T_1}(\frac{1}{2}{U}_{\mathrm{dc}}^{*})}\cdot \left[u_{\mathrm{ref}}(2d_{\mathrm{z}}+1)\cdot i_{\mathrm{s}}\right]\mathrm{d}t$$

(19)

In order to maintain modulation signals within the linear modulation region, the restriction imposed by nonlinear modulation signals in (7) can be expressed as follows:

$$\left|d_z\pm u_{\mathrm{ref}}\right|\le 1$$

(20)

By applying (20) into (19), the active power absorbed by R_min indicates λ_max. Subsequently, using (15), (18), and (19), the upper limit of the dc load imbalance level can be calculated. Furthermore, considering (13), (15), and (17), the constraints on the magnitudes of u_1-v and u_2-v in (14) are further narrowed down. The process will be elaborated upon in the subsequent section, employing Method 1 to provide a comprehensive illustration.

4. Methods to Increase Balance Abilities

In this section, the balance abilities of two typical methods, namely Method 1 and Method 2, are elucidated first, and then two methods (Method 3 and Method 4) to extend the balance range of the typical two methods are discussed.

4.1. Method 1: The Basic Form

By referring to (11), the basic form of the offset voltage is written as follows:

$$d_{\mathrm{z}}=\mathrm{sgn}\left(u_{\mathrm{ref}}{i}_{\mathrm{s}}\right)\Delta d$$

(21)

In (21), a square wave is added to the original modulation signals, taking into account the polarity of the grid current and initial signals. The modulation signals of Method 1 are elaborated in Figure 7. For ease of analysis, only waveforms with Δd > 0 are presented in this context. Here, $u_{\mathrm{ao}.\mathrm{r}}^{\mathrm{con}}$ and $u_{\mathrm{bo}.\mathrm{r}}^{\mathrm{con}}$ represent the modulation signals of the converter after implementing Method 1. It is evident that the peaks of the original signals are the most susceptible points on the superimposed modulation signals to exceed the linear modulation region. By substituting (21) into (20) and considering linear modulation, the maximum value of Δd can be derived as follows:

$${\left|\Delta d\right|}_{\max }=1-U_{\mathrm{ref}}$$

(22)

where U_ref is the magnitude of u_ref.

By applying (21) and (22) into (19), according to (15) and (18), λ_max based on Method 1 is described as follows:

$${\lambda }_{\max }=\frac{1}{2}+\left[1-\frac{U_{\mathrm{s}}\cos \theta }{U_{\mathrm{dc}}^{*}\cos (\phi -\theta )}\right]\left[1-\frac{2(\phi -\theta )-2\tan (\phi -\theta )}{\pi }\right]$$

(23)

According to (13), (15), (17), (19), and (22), the range of input ac voltage magnitude for each unit based on Method 1 is expressed as follows:

$$\left\{\begin{array}{ccc}\hfill \frac{U_{\mathrm{s}}\cos (\theta )}{2\cos ({\phi }_1^{\mathrm{con}}-\theta )}& \le U_{1-\mathrm{v}}\le & \frac{U_{\mathrm{s}}\cos (\theta )}{2\cos ({\phi }_1^{\mathrm{con}}-\theta )}+\left(1-\frac{U_{\mathrm{s}}\cos (\theta )}{U_{\mathrm{dc}}^{*}\cos (\phi -\theta )}\right)\left[1-\frac{2(\phi -\theta )-2\tan (\phi -\theta )}{\pi }\right]\frac{U_{\mathrm{s}}\cos (\theta )}{\cos ({\phi }_1^{\mathrm{con}}-\theta )}\hfill \\ \hfill 0& \le U_{1-\mathrm{v}}\le & 0.5U_{\mathrm{dc}}^{*}\hfill \end{array}\right.$$

(24)

$$\left\{\begin{array}{lll}\hfill \frac{U_{\mathrm{s}}\cos (\theta )}{\cos ({\phi }_2^{\mathrm{con}}-\theta )}\left\{\frac{1}{2}\right.-\left(1-\frac{U_{\mathrm{s}}\cos (\theta )}{U_{\mathrm{dc}}^{*}\cos (\phi -\theta )}\right)\left.\left[1-\frac{2(\phi -\theta )-2\tan (\phi -\theta )}{\pi }\right]\right\}& \le U_{2-\mathrm{v}}\le & \frac{U_{\mathrm{s}}\cos (\theta )}{2\cos ({\phi }_2^{\mathrm{con}}-\theta )}\hfill \\ \hfill 0& \le U_{2-\mathrm{v}}\le & 0.5U_{\mathrm{dc}}^{*}\hfill \end{array}\right.$$

(25)

Moreover, by referring to (24) and (25), the range of ac voltage magnitudes for both H-bridge units can be visually represented by a vector diagram depicted in Figure 8. The shaded area “CDb₁a₁E” enclosed by “L1”, “L2”, “L3”, and “L4” illustrates the balance range of the single-phase 3L-NPC converter. The adopted rectifier is considered controllable when the submodule ac voltages, influenced by the imbalance level of the dc load, fall within this balance range. The curves “L1” and “L2” centered at points A and B with a radius of $U_{\mathrm{dc}}^{*}$ indicate the limits on U_1-v and U_2-v as defined in (14). The straight line “L3”, determined by (17), bisects the line segment AB and is perpendicular to the direction of the grid current vector. The straight line “L4”, representing the constraints imposed by λ_max, forms a right angle with the current vector. The line segment AG, parallel to i_s, intersects the left boundary “L3” of the shadow region at point d and intersects the right boundary “L4” of the shadow region at point e₁. The length of segment “de₁” indicates the upper limit of the dc load imbalance level (λ_max) based on Method 1. The longer the line segment “dd₁”, the greater the balance capacity of the corresponding balancing control measures. Thus, the balance abilities are “Method 2 > Method 1”.

4.2. Method 2

The offset voltage devised in [20] is as follows:

$$d_{\mathrm{z}}=\left(1-\left|u_{\mathrm{ref}}\right|\right)\mathrm{sgn}\left(u_{\mathrm{ref}}\cdot i_{\mathrm{s}}\right)\Delta d$$

(26)

In (26), the modulation signals of Method 2 are depicted in Figure 9. Compared to Method 1, the upward movement of the peaks in Method 2 relative to other points has decreased. Therefore, Method 2 is less balanced.

Substituting (26) into (20), according to linear modulation, the maximum value of Δd is expressed as follows:

$${\left|\Delta d\right|}_{\max }=1$$

(27)

Similar to (23), the λ_max based on Method 2 can be expressed as follows:

$${\lambda }_{\max }=\frac{3}{2}+\frac{2\tan (\phi -\theta )-2(\phi -\theta )}{\pi }+\frac{4U_{\mathrm{s}}\cos (\theta )\sin (\phi -\theta )}{3\pi U_{\mathrm{dc}}^{*}}-\frac{8U_{\mathrm{s}}\cos (\theta )}{3\pi U_{\mathrm{dc}}^{*}}$$

(28)

Using Equations (13), (15), (17), (19), and (27), the expression for determining the permissible range of input ac voltage magnitudes based on Method 2 can be derived as follows:

$$\left\{\begin{array}{ccc}\hfill \frac{U_{\mathrm{s}}\cos (\theta )}{2\cos ({\phi }_1^{\mathrm{con}}-\theta )}& \le U_{1-\mathrm{v}}\le & \left[\frac{3}{2}+\frac{2\left(\tan (\phi -\theta )-(\phi -\theta )\right)}{\pi }\right]\frac{U_{\mathrm{s}}\cos (\theta )}{\cos ({\phi }_1^{\mathrm{con}}-\theta )}+\left[\frac{4\sin (\phi -\theta )}{3\pi U_{\mathrm{dc}}^{*}}-\frac{8}{3\pi U_{\mathrm{dc}}^{*}}\right]\frac{U_{\mathrm{s}}^2{\cos }^2(\theta )}{\cos ({\phi }_1^{\mathrm{con}}-\theta )}\hfill \\ \hfill 0& \le U_{1-\mathrm{v}}\le & 0.5U_{\mathrm{dc}}^{*}\hfill \end{array}\right.$$

(29)

$$\left\{\begin{array}{ccc}\hfill \left[\frac{8}{3\pi U_{\mathrm{dc}}^{*}}-\frac{4\sin (\phi -\theta )}{3\pi U_{\mathrm{dc}}^{*}}\right]\frac{U_{\mathrm{s}}^2{\cos }^2(\theta )}{\cos ({\phi }_2^{\mathrm{con}}-\theta )}-\left[\frac{1}{2}+\frac{2\left(\tan (\phi -\theta )-\phi +\theta \right)}{\pi }\right]\frac{U_{\mathrm{s}}\cos (\theta )}{\cos ({\phi }_2^{\mathrm{con}}-\theta )}& \le U_{2-\mathrm{v}}\le & \frac{U_{\mathrm{s}}\cos (\theta )}{2\cos ({\phi }_2^{\mathrm{con}}-\theta )}\hfill \\ \hfill 0& \le U_{2-\mathrm{v}}\le & 0.5U_{\mathrm{dc}}^{*}\hfill \end{array}\right.$$

(30)

The balance range of Method 2 is graphically depicted as the shaded area “CDb₂a₂E” in Figure 8, as indicated by (29) and (30). As the angle ${\phi }_1^{\mathrm{con}}$ varies, the angle ${\phi }_2^{\mathrm{con}}$ undergoes variations, causing the endpoint of vector u₁ (also the starting point of vector u₂) to shift within the region “CDb₂a₂E”. The line segment “a₂b₂”, which is perpendicular to i_s, represents λ_max and is the upper limit of the balance range based on Method 2. It is clear that the length of line segment “de₂” exceeds that of “de₁”. Consequently, Method 2 demonstrates a superior balance capacity in comparison to Method 1.

4.3. Method 3: Increasing the Reference DC Voltage

The load imbalance expressions in (23) and (28) clearly demonstrate that adjusting the set value of the dc voltage can result in an elevation in λ_max and an expansion of the balancing capacity. By taking (23) in Method 1 as an illustration, the derivative of λ_max with respect to $U_{\mathrm{dc}}^{*}$ can be expressed as follows:

$$\frac{\partial {\lambda }_{\max }}{\partial U_{\mathrm{dc}}^{*}}=\frac{U_{\mathrm{s}}\cos \theta \left[\pi +2\tan (\phi -\theta )-2(\phi -\theta )\right]}{\pi \cos (\phi -\theta ){\left(U_{\mathrm{dc}}^{*}\right)}^2}$$

(31)

Equation (31) is greater than zero. Consequently, as $U_{\mathrm{dc}}^{*}$ is increased to $U_{\mathrm{dc}}^{\mathrm{con}}$, the balance region for Method 1 can be delineated in Figure 10. Line segment “de₁” transforms into line segment “de₃”, thereby expanding the balance range and encompassing the shaded area “CFHa₃b₃GDb₁a₁E”. The situation pertaining to Method 2 exhibits similarity when $U_{\mathrm{dc}}^{*}$ is increased. Consequently, Method 3 proficiently augments the converter’s balance capacity.

4.4. Method 4: Reducing the Total Input Active Power

According to (23) and (28), λ_max is solely influenced by the angle “φ” between u_ab and i_s, assuming that the angle “θ” between u_s and i_s remains unchanged. The only exception to this is $U_{\mathrm{dc}}^{*}$, which has been discussed in the previous subsection. This subsection will now analyze the effect of φ on the system’s balancing capability.

The total input active power can be expressed as follows:

$$P_{\mathrm{total}}=\frac{U_{\mathrm{s}}{I}_{\mathrm{s}}\cos \theta }{2}$$

(32)

As illustrated in Figure 11, the voltage vector of the ac side inductor “u_L” consistently remains perpendicular to vector “i_s”. Thus, the direction of u_L remains unchanged due to the constant angle θ. However, as the angle φ undergoes variation, the endpoint B of vector u_ab is moving along a line aligned with the direction of vector u_L, leading to a modification in the magnitude of the i_s. As a result, according to (32), there is a positive relationship between P_total and φ. The angle between u_ab and i_s is denoted as (φ − θ). By adjusting the P_total to $P_{\mathrm{s}}^{\mathrm{con}}$, the magnitude of u_ab varies and thereby (φ − θ) reduced. The vector u_ab shifts to $u_{\mathrm{ab}}^{\mathrm{con}}$.

For instance, considering Method 1, the expression for the partial derivative of λ_max with respect to φ can be derived from (23). This partial derivative demonstrates a negative value, indicating that λ_max and the range of input ac voltage magnitude of Method 1 can be expanded by reducing the total input active power. This relationship is illustrated in Figure 11. Similarly, when P_total is decreased, Method 2 follows a comparable pattern.

Nevertheless, it is important to note that the enhancement in balance ability can only be marginally extended when comparing the methods with and without Method 4. This limitation arises from the presence of a relatively low inductance on the ac side.

5. Comparing Different Approaches for Enhancing Load Balancing Capabilities

In this section, a comparison of the balancing abilities of the previously analyzed methods is presented.

The upper limit of dc load imbalance of the aforementioned methods is presented in

Table 1. The limit of the dc load imbalance level of the methods.

Method	Upper Limit of DC Load Imbalance Level (λmax)
Method 1	$\frac{1}{2}+\left(1-\frac{U_{\mathrm{s}}\cos (\theta )}{U_{\mathrm{dc}}^{*}\cos (\phi -\theta )}\right)\left[1-\frac{2(\phi -\theta )-2\tan (\phi -\theta )}{\pi }\right]$
Method 2	$\frac{3}{2}+\frac{2\tan (\phi -\theta )-2(\phi -\theta )}{\pi }+\frac{4U_{\mathrm{s}}\cos (\theta )\sin (\phi -\theta )}{3\pi U_{\mathrm{dc}}^{*}}-\frac{8U_{\mathrm{s}}\cos (\theta )}{3\pi U_{\mathrm{dc}}^{*}}$
Method 1 + Method 3	$\frac{1}{2}+\left(1-\frac{U_{\mathrm{s}}\cos (\theta )}{U_{\mathrm{dc}}^{\mathrm{con}}\cos (\phi -\theta )}\right)\left[1-\frac{2(\phi -\theta )-2\tan (\phi -\theta )}{\pi }\right]$
Method 2 + Method 3	$\frac{3}{2}+\frac{2\tan (\phi -\theta )-2(\phi -\theta )}{\pi }+\frac{4U_{\mathrm{s}}\cos (\theta )\sin (\phi -\theta )}{3\pi U_{\mathrm{dc}}^{\mathrm{con}}}-\frac{8U_{\mathrm{s}}\cos (\theta )}{3\pi U_{\mathrm{dc}}^{\mathrm{con}}}$
Method 1 + Method 4	$\frac{1}{2}+\left(1-\frac{\sqrt{{\left(U_{\mathrm{s}}\cos \theta \right)}^2+x_1^2}}{U_{\mathrm{dc}}^{*}}\right)\left[1-\frac{2}{\pi }\arctan (\frac{x_1}{U_{\mathrm{s}}\cos \theta })+\frac{2x_1}{\pi U_{\mathrm{s}}\cos \theta }\right]$
Method 2 + Method 4	$\frac{3}{2}-\frac{8U_{\mathrm{s}}\cos \theta }{3\pi U_{\mathrm{dc}}^{*}}+\frac{2x_1}{\pi U_{\mathrm{s}}\cos \theta }-\frac{2}{\pi }\arctan \left(\frac{x_1}{U_{\mathrm{s}}\cos \theta }\right)$ $+\frac{4U_{\mathrm{s}}\cos \theta }{3\pi U_{\mathrm{dc}}^{*}}\frac{x_1}{\sqrt{{\left(U_{\mathrm{s}}\cos \theta \right)}^2+{\left(x_1\right)}^2}}$

Note: $x_1=\frac{2P_{\mathrm{s}}^{\mathrm{con}}}{U_{\mathrm{s}}\cos \theta }{\omega }_{1}L-U_{\mathrm{s}}\sin \theta$.

. According to Figure 8, the balance ability of Method 2 is greater than that of Method 1. On the basis of either Method 1 or Method 2, simultaneously employing Method 3 or Method 4 can increase or extend the balance limits. Thus, the balancing abilities of Method 1 and Method 2 are smaller than that of Method 1 + Method 3, Method 2 + Method 3, Method 1 + Method 4, and Method 2 + Method 4. Additionally, enabling Method 4 can only increase the balance ability slightly for the relatively low inductance results in a small phase angle φ, leading to a limited range of movement at the end of u_ab. Therefore, the order of balancing abilities is “(Method 2 + Method 3) > (Method 1 + Method 3) > (Method 2 + Method 4) > Method 2 > (Method 1 + Method 4) > Method 1”.

6. Simulation Results

In this section, the maximum dc load imbalance level and balance range of these proposed methods are verified by simulation tests. The time domain simulation model of the single-phase 3L-NPC converter is established.

The main system parameters of the model are outlined in

Table 2. System parameters.

Parameters	Value
Switching frequency fs/Hz	5000
AC voltage source Us/V	$80\sqrt{2}$
AC side inductance L/mH	5
Load (R1 + R2)/Ω	50
DC link capacitor C/mF	4.4
Proportional term of balance control Kp	1
Integral term of balance control Ki	10

, and these parameters remain consistent across various simulation runs.

The voltages of the ac source, the dc voltages, and the grid current before and after enabling Method 1 are illustrated in Figure 12. The ac base current, ac base voltage, and dc base voltage are 8 A, 113 V, and 75 V, respectively. The system operates in the unity power factor operating condition both before and after implementing balance control. The THD values of the grid current are measured by the “Powergui FFT Analysis Tool” in Matlab/Simulink, which are 1.96% (without Method 1) and 1.93% (with Method 1).

Figure 13 depicts the dc voltages when the rated dc voltage is 150 V and the imbalance level “λ” is 0.600 (R₁ = 20 Ω, R₂ = 30 Ω) and 0.680 (R₁ = 16 Ω, R₂ = 34 Ω), respectively. According to Table 1, the “λ_max” of Method 1 and Method 2 are 0.665 and 0.770, respectively. In Figure 13a, when “λ = 0.600”, which is lower than both 0.665 and 0.770, both Method 1 and Method 2 reach the voltage balance. Yet, Method 1 is faster than Method 2. On the other hand, in Figure 13b, when “λ = 0.680”, which is higher than 0.665 but lower than 0.770, the dc voltages with Method 1 cannot be balanced, while those with Method 2 are balanced. As illustrated in Figure 14a, the rated dc voltage is still 150 V; yet, the imbalance level “λ” is 0.760 (R₁ = 12 Ω, R₂ = 38 Ω) and 0.780 (R₁ = 11 Ω, R₂ = 39 Ω). With Method 2, the voltages are balanced when “λ” is 0.760 (less than 0.770) and unbalanced when “λ” is 0.780 (higher than 0.770). Therefore, their balance abilities are sorted as “Method 2 > Method 1”.

The influence of U_dc*on the balance ranges is depicted in Figure 14 b–d. In Figure 14b,c, the rated dc voltage is 170 V and the dc voltages are balanced. When comparing Figure 14c to Figure 13b (both at “λ = 0.680”), the voltages using Method 1 are balanced, as U_dc* is increased from 150 V to 170 V. Similarly, when comparing Figure 14b to Figure 14a (both at “λ = 0.780”), the voltages with Method 2 are balanced when U_dc* is increased from 150 V to 170 V. Thus, the balance limits of Method 1 and Method 2 are extended when the rated dc voltage is increased. Furthermore, in Figure 14d, the dc voltages are balanced with Method 1 (“λ = 0.780”, U_dc* = 200 V), whereas they are not balanced in Figure 1a under the same “λ” and a lower U_dc*. Consequently, the balance limit of Method 1 + Method 3 is higher than that of Method 2. Therefore, Method 3 is effective in voltage balancing, and the balance abilities are “(Method 2 + Method 3) > (Method 1 + Method 3) > Method 2 > Method 1”.

Additionally, the results in Figure 13 and Figure 14 are filled in

Table 3. The results for the methods applied.

Method	Udc*	λ	The Theoretical Value of λmax	Balance Results
M1	150 V	0.600	0.665	Balanced
M1	150 V	0.680	0.665	Not Balanced
M1 + M3	170 V	0.680	0.755	Balanced
M1 + M3	200 V	0.780	0.855	Balanced
M2	150 V	0.600	0.770	Balanced
M2	150 V	0.680	0.770	Balanced
M2	150 V	0.760	0.770	Balanced
M2	150 V	0.780	0.770	Not Balanced
M2 + M3	170 V	0.780	0.830	Balanced

. It is obvious that dc voltages can be balanced only when the load imbalance level “λ” is less than the upper limit “λ_max”. Therefore, the calculations for the balance range are accurate.

Figure 15 displays the variations in the upper limits “λ_max” of Method 1 and Method 2 as the active power “P_total” and the rated dc voltage “U_dc*” change. The red dashed lines show the variations of λ_max with P_total when U_dc* is 150 V. The blue dashed lines delineate the changes of λ_max with U_dc* when P_total is 500 W. It is evident that the influence of active power on the balancing limits is minimal, making it impractical. Thus, the hierarchy of balancing capabilities is as follows: “(Method 2 + Method 3) > (Method 1 + Method 3) > (Method 2 + Method 4) > Method 2 > (Method 1 + Method 4) > Method 1”.

Nevertheless, while configuring system parameters, there might be a significant dc load imbalance at specific power levels. Consequently, if the rated dc voltage remains constant and the dc load imbalance is substantial, the active power can be temporarily decreased to improve the balancing capacity.

7. Conclusions

This paper presents a quantitative analysis of the balancing range of single-phase 3L-NPC converters by conceptualizing the converter as a two-unit cascaded H-bridge system to decouple u₁ and u₂. The focus is on the balance control methods based on CBPWM with offset voltage injection. The offset voltage constraint is derived using switching functions (S_a and S_b), and the balancing range of two typical methods for the converter is determined based on power conservation principles. Novel methods are explored to expand the balance range in response to the maximum load imbalance levels of Method 1 and Method 2. A comparative analysis of these methods is conducted to evaluate their balancing capabilities. The accuracy and effectiveness of the balance range calculations are confirmed through MATLAB/Simulink simulations. This study lays a theoretical groundwork to ensure the secure and stable operation of single-phase 3L-NPC converters.