The Influence of Switching Frequency on Control in Voltage Source Inverters

Abstract

This paper aims to show how the switching frequency influences the properties of the digitally controlled voltage source inverter (VSI). The measurements of the Bode plots of the inverter are shown and discussed to present the existing signal delays and power conversion efficiency, depending on the switching/sampling frequency. Two types of controllers are presented, Single-Input–Single-Output (SISO) and Multi-Input–Single-Output (MISO), and adequate prediction units (the Smith Predictor for SISO—Coefficient Diagram Method and the full-state Luenberger Observer for MISO—Passivity Based Control) were used to compensate for the delays. It will be shown by comparing the THD of the VSI output voltage that prediction is useful with low VSI switching frequency (about 10 kHz) but is not important for the middle switching frequencies (about 25 kHz) or the high switching frequency (>50 kHz). This paper shows that increasing the switching frequency simplifies digital control without reasonably decreasing efficiency. The theoretical considerations, the Matlab/Simulink 2021b simulations, the final experimental laboratory verification are presented.

1. Introduction

This study aims to show how the switching frequency influences the properties of the voltage source inverter (VSI). The theoretical considerations, simulations, and breadboard verification will be presented for the exemplary VSI with the first scheme of PWM [1,2] where the output PWM frequency is the double switching frequency, with the output L_FC_F filter calculated as in [3] and finally improved. The research was performed for the low (12,800 Hz), middle (25,600 Hz), and high (51,200 Hz) switching frequencies f_s, which resulted in 25,600, 51,200, and 102,400 Hz in the output PWM frequencies f_PWM. The inverter controller and the transistors bridge work with the basic switching frequencies f_s and the output filter with the double frequencies f_PWM = 2f_s. The advantage of the low switching frequency is the lower dynamic power loss in the transistor bridge and in the output filter choke core [4,5] but the output filter should have bigger dimensions. The additional disadvantage of the low frequency is the possible audible noise (the result of, e.g., magnetostriction of the filter coil core). It can be easily shown that the measurement channels of the state variables used by the digital controller can be modeled as delays with some (two or three) switching/sampling periods. In this case, a lower delay enables us to use higher gains of the controller. The properties of two controllers, dependent on the switching frequency, will be investigated. The first will be the Single-Input–Single-Output Coefficient Diagram Method (SISO-CDM) controller [6,7,8] where the coefficients of the characteristic equation of the closed-loop system should be equal to the coefficients of the Standard Manabe Form. For the chosen controller equations, the adjustable variable is the time constant of the closed loop system. It is equal to some switching periods and it is dependent on the switching frequency. The second Multi-Input–Single-Output controller is a Passivity Based Controller (MISO-PBC) [9,10,11,12,13] in the improved version where the output voltage is directly used as the controller input [14,15]. PBC’s maximum current R_i and voltage K_v gains depend on the switching frequency [16] and delays of the measuring channels [3]. For the MISO controller (when the state variables are measured), the delay of the measuring channels can be compensated using prediction, the gains of the MISO controller can be higher, and the output voltage distortions will be lower [3]. The comparison of the VSI output voltage distortions for MISO and SISO controllers for the three different switching frequencies will be discussed. The paper has the following structure. Section 2: design of the experimental voltage source inverter including the PWM modulation scheme, the design of the output filter, and the description of the used inverter components; Section 3: the measuring Bode plots of the inverter and the measurement channels to calculate the equivalent serial resistance of VSI, which is the coefficient of power conversion losses; the Bode plots of the measurement channels enable us to justify the approximation of them using simple delays; Section 4: the description of the discrete model of the VSI, which is necessary for the design of the control system; Section 5: designing of the exemplary SISO-CDM control, simulations of the VSI output voltage for the different switching frequencies, and the different time constants of the closed loop system with/without Smith Predictor; Section 6: designing of the exemplary MISO-PBC control, simulations of the VSI output voltage for the different switching frequencies with/without Luenberger Observer (designed for PBC parameters); Section 7: the experimental verification (using the THD of the VSI output voltage as the control quality measure and presenting the spectrum of harmonics) of the previous simulations results of SISO-CDM with/without the Smith Predictor and MISO-PBC with/without Luenberger Observer; the Real Time Interface (MicroLabBox RTI 1202 with dSpace Release 2021-B software) was used for control of the experimental inverter; Section 8: discussion of the simulations and experimental verification results; and Section 9: conclusion concerning the choice of the VSI switching frequency and the control structure.

2. Design of the Experimental Voltage Source Inverter

The PWM 3-level schema presented in Figure 1 (1), where both legs of the bridge are controlled with the fundamental waveforms f_m, shifted with the half of the fundamental period, enabling the control of the output voltage in the surroundings of the zero crossing. Other PWM 3-level schemas have rigidly fixed zero crossing and there is no possibility to change the sign of the control waveform to the opposite in the halves of the fundamental period (e.g., to obtain a negative control waveform in the positive half of the output voltage waveform period). The PWM voltage v_PWM in the output of the transistor bridge has a double switching frequency, which helps to reduce the output filter inductor dimensions.

$$\mathrm{for} k=1\dots (f_s/f_m)$$

(1)

$$S_1:T_{ON}(k)/T_s=0.5M\sin (2\pi k{f}_m/f_s)+0.5$$

$$S_2:NOT(S_1)$$

$$S_3:T_{ON}(k)/T_s=0.5M\sin ((2\pi k{f}_m/f_s)+\pi )+0.5$$

$$S_4:NOT(S_3)$$

The output filter of the experimental VSI was initially calculated for the steady-state conditions [17] (2).

$$L_F\approx {\displaystyle \frac{1}{f_{PWM}}}{\displaystyle \frac{V_{OUTrms}}{I_{OUTrms}}}={\displaystyle \frac{1}{f_{PWM}}}{R}_{LOADnom}$$

(2)

$$C_F\approx {\displaystyle \frac{1}{f_{PWM}}}{\displaystyle \frac{1}{V_{OUTrms}/I_{OUTrms}}}={\displaystyle \frac{1}{f_{PWM}}}{\displaystyle \frac{1}{R_{LOADnom}}}$$

For the lowest analyzed switching frequency f_s = 12,800 Hz, f_PWM = 25,600 Hz. For R_LOAD = 50 Ω, the calculated L_F = 2 mH, C_F = 1 μF, is satisfactory for the static load. However, the PWM modulator introduces one switching period T_s delay (data are stored in one period and it sets the pulse width in the next period) and it is possible to assume that the inductor current is constant during one switching period. For the step load current decrease, e.g., Δi_OUT = −5 A, the feedback does not operate during one T_s, the whole almost constant excessive inductor current will flow to the output capacitor. For the calculated C_F = 1 μF, the overvoltage will be T_sΔi_OUT/C_F = 391 V. The capacitor C_F should be increased to, e.g., 50 μF (the inductance L_F can be reduced). The overvoltage will be 7.8 V for the −5 A step current decrease. The resonant frequency of the filter is about 500 Hz. It is important because the frequency spectrum in which the control system will be analyzed is below this frequency. Finally, the output filter capacitor 51 μF is WIMA MKP 4 (five parallel capacitors 10 μF and one 1 μF for special tests), of the Metallized Polypropylene (MKP) type, and its equivalent serial resistance (ESR) R_C can be omitted (MKP have a low dissipation factor) in the further analysis. The output filter coil core is made of the alloy-powder high-quality material MS-Sendust [5,18]. It will be shown how the power losses [4] in the coil core increase with the switching frequency. The serial equivalent resistance of the inverter depends on the power losses in the coil core as well as the dynamic and static losses on the switching transistors. The Vishay Siliconix MOSFET IRFP360LC switches driven by International Rectifier IR2184 circuits are used in the VSI bridge. The serial drain-source on-state resistance is 0.2 Ω. They are cheap and can be used in the experimental VSI. In the commercial VSI, we would rather use SiC transistors but they are more expensive and some of them require a negative gate-source voltage to be switched off. But they have much lower static and dynamic losses. The standard Si-MOSFET transistors better show how the VSI properties change with the frequency.

3. Measuring the VSI Properties

The Bode plots of the VSI should be measured to estimate the equivalent serial resistance of the inverter—all the serial real and computational resistances that are a result of the power conversion losses in the VSI. In this way, it is possible to estimate the influence of the switching frequency on the power conversion efficiency. The Bode plots of the measurement channels enable us to justify the approximation of them using simple delays in the restricted frequency range in the digitally controlled system. In the Bode plots measurement method [19,20], the fundamental waveform (about 95% amplitude) is summed with the excitation signal (about 5% of the amplitude) that is a n-th harmonic of the fundamental waveform in the input of the PWM modulator. In the output of the measured trace, the output complex signal is separated using the Fourier Transform into the output fundamental waveform and output excitation signal. It was assumed that in the considered frequency range, the fundamental waveform is not dumped or shifted. The relative measuring of the transient function, creating the quotient of the ratios of the test signal to the fundamental signal in the output and input (3), is the only way of calculating signals with the different units in the output and input. Three switching frequencies were used: 12,800 Hz, 25,600 Hz, and 51,200 Hz.

For n = 1…n_max

$$K_{CTRL}(j2\pi f_n)={\displaystyle \frac{\left|V_{OUT}(n{f}_m)\right|/\left|V_{OUT}(f_m)\right|}{\left|V_{IN}(n{f}_n)\right|/\left|V_{IN}(f_m)\right|}}\exp (j\arg (n{f}_m))$$

(3)

The magnitude Bode plot is (4)

$$\left|K_{CTRL}(n{f}_n)\right|=20\log {\displaystyle \frac{\left|V_{OUT}(n{f}_m)\right|/\left|V_{OUT}(f_m)\right|}{\left|V_{IN}(n{f}_n)\right|/\left|V_{IN}(f_m)\right|}}$$

(4)

The phase Bode plot is (5)

$$\arg (n{f}_m)=[\arg (V_{OUT}(n{f}_m))-\arg (V_{OUT}(f_m))]-[\arg (V_{IN}(n{f}_m))-\arg (V_{IN}(f_m))]$$

(5)

The transient function of the inverter together with the output voltage measuring channel should be measured first (trace 1 in Figure 2). Next, the output voltage measuring channel should be measured separately (trace 2 in Figure 2 and Figure 3a,b). Finally, the transfer function of the pure inverter can be calculated as the difference between these two measurements in [dB] and [deg] (Figure 3c,d). The inverter transfer function can be approximated as the second-order function (6). R_se is the equivalent serial resistance of the inverter. R_se should be understood as a power conversion loss factor.

$$K_{CTRL}=F_{LC}(s)={\displaystyle \frac{{{\omega }_{F0}}^2}{s^2+2{\xi }_F{\omega }_{F0}s+(1+R_{se}/R_{OUT}){{\omega }_{F0}}^2}}$$

(6)

The damping coefficient ζ_F (7), the inductance L_F (8), and the equivalent serial resistance R_se (9) can be calculated. We assume that R_LOAD ≫ R_se. The maximum of the |K_CTRL| function for the angular frequency ω_max when |K_CTRL|_max= |K_CTRL(ω_max)| should be identified.

$${\xi }_F\approx \sqrt{{\displaystyle \frac{1}{2}}[1-\sqrt{(1-{\displaystyle \frac{1}{{{\left|K_{CTRL}\right|}_{\max }}^2}})}]}$$

(7)

$$L_F={\displaystyle \frac{1-2{{\xi }_F}^2}{{{\omega }_{\max }}^2{C}_F}}\approx {\displaystyle \frac{1}{{{\omega }_{\max }}^2{C}_F}}, \mathrm{for} {{\xi }_F}^2<0.5$$

(8)

$$R_{se}=(2{\xi }_F{\displaystyle \frac{{\omega }_{\max }}{\sqrt{1-2{{\xi }_F}^2}}}-{\displaystyle \frac{1}{R_{LOAD}{C}_F}}){\displaystyle \frac{1-2{{\xi }_F}^2}{{{\omega }_{\max }}^2{C}_F}} \mathrm{for} R_{LOAD}>{\displaystyle \frac{\sqrt{1-2{{\xi }_F}^2}}{2{\xi }_F{\omega }_{\max }{C}_F}} \mathrm{and} {{\xi }_F}^2 < 0.5$$

(9)

Calculations of waveforms in Figure 3c,d according to (7) and (9) are presented in Figure 4a. The power conversion losses are calculated for the 50 Hz load current (R_se represents the switching frequency losses). The output capacitor current flows through R_se and causes active power losses in it. Equations (9)–(11) enable us to calculate the power conversion efficiency presented in Figure 4b.

$$P_{loss}\approx R_{se}{I_L}^2=R_{se}{\displaystyle \frac{{V_{OUTrms}}^2}{{R_{LOAD}}^2}}(1+{(2\pi 50R_{LOAD}{C}_F)}^2)$$

(10)

$$\eta ={\displaystyle \frac{P_{OUT}}{P_{OUT}+P_{loss}}}={\displaystyle \frac{1}{1+\frac{R_{se}}{R_{LOAD}}(1+{(2\pi 50R_{LOAD}{C}_F)}^2)}}$$

(11)

In Section 3, it was shown that measurement channels can be approximated as 2 or 3 switching period delays in the frequency range under the resonant frequency of the output filter and the increase in the switching frequency causes a very low decrease in the efficiency (0.5%) for the nominal load current (in case of the experimental VSI but it has a standard component and the statement can be expanded on other VSIs).

4. Discrete Model of the VSI

The discrete model of the inverter is required for the design of various types of controllers. The basic design is the description of the VSI using state equations. The state-space variables are x = [v_OUT i_LF i_OUT]^T, input variable u = v_FIN—the envelope of v_PWM (Figure 1), and output variable y = v_OUT, the state space equations (for R_C = 0) are (12) and (13). The following substitution was made: R_L = R_se (Figure 1).

$$\dot{x}=Ax+Bu, y=Cx$$

(12)

where

$$A=\left[\begin{array}{ccc}0& {\displaystyle \frac{1}{C_F}}& -{\displaystyle \frac{1}{C_F}}\\ -{\displaystyle \frac{1}{L_F}}& -{\displaystyle \frac{R_{se}}{L_F}}& 0\\ 0& 0& 0\end{array}\right],B=\left[\begin{array}{c}0\\ {\displaystyle \frac{1}{L_F}}\\ 0\end{array}\right],C=\left[\begin{array}{ccc}1& 0& 0\end{array}\right]$$

(13)

The state space Equation (12) is solved in the switching period [21] and the exponential function of T_ON time for the double-edge modulation, which depends on the PWM modulation type, is approximated and linearized (14).

$$e^{A{T}_{ONk}/2}\approx I+A{T}_{ONk}/2$$

(14)

The linearized discrete state space equations [22] are (15) and (16) where v_CTRL is the input signal of the PWM modulator.

$$x(k+1)=A_{\mathrm{D}}x(k)+G_{\mathrm{D}}{T}_{ON}(k)=A_{\mathrm{D}}x(k)+G_{\mathrm{D}}{\displaystyle \frac{T_s}{V_{DC}}}{v}_{CTRL}(k)$$

(15)

$$y(k+1)=C_{\mathrm{D}}x(k)$$

(16)

where the matrixes are (17).

$$A_D=\Phi (T_s)=\left[\begin{array}{ccc}{\varphi }_{11}& {\varphi }_{12}& {\varphi }_{13}\\ {\varphi }_{21}& {\varphi }_{22}& {\varphi }_{23}\\ {\varphi }_{31}& {\varphi }_{32}& {\varphi }_{33}\end{array}\right], G_D=\left[\begin{array}{c}{g}_{11}\\ g_{21}\\ g_{31}\end{array}\right], C_D=C$$

(17)

$${\omega }_{F0}={\displaystyle \frac{1}{\sqrt{C_F{L}_F}}}, {\xi }_F={\displaystyle \frac{1}{2}}{R}_{se}\sqrt{{\displaystyle \frac{C_F}{L_F}}}, E_{\phi }=\exp (-{\xi }_F{\omega }_{F0}{T}_s), E_g=\exp (-{\xi }_F{\omega }_{F0}{T}_s/2),$$

$${\varphi }_{11}=[\cos \left({\omega }_{F0}{T}_s\right)+{\xi }_F\sin \left({\omega }_{F0}{T}_s\right)]E_{\phi }, {\varphi }_{12}={\displaystyle \frac{1}{{\omega }_{F0}{C}_F}}\sin ({\omega }_{F0}{T}_s)E_{\phi }, {\phi }_{13}=-{\phi }_{12}+R_{se}({\phi }_{11}-1)$$

$${\varphi }_{21}=-{\displaystyle \frac{C_F}{L_F}}{\phi }_{12}, {\varphi }_{22}=[\cos ({\omega }_{F0}{T}_s)-{\xi }_F\sin ({\omega }_{F0}{T}_s)]E_{\phi }, {\varphi }_{23}=1-{\phi }_{11},$$

$${\varphi }_{31}=0, {\varphi }_{32}=0, {\varphi }_{33}=1,$$

$$g_{11}=V_{DC}{\omega }_{F0}\sin ({\omega }_{F0}{T}_s/2)E_g, g_{21}={\displaystyle \frac{V_{DC}}{L_F}}[\cos ({\omega }_{F0}{T}_s/2)-{\xi }_F\sin ({\omega }_{F0}{T}_s/2)]E_g, g_{31}=0.$$

5. SISO-CDM Control of VSI

In the control of the VSI from Figure 5, only the output voltage is measured to control it (Single-Input–Single-Output). The output current is treated as the independent disturbance [15,23,24,25,26,27]. It is not the ideal approach (the dependence between output voltage and output current vanishes) but enables the design of the controller to be independent of the VSI load. The T, S, and R polynomials are components of Manabe’s Coefficient Diagram Method (CDM) controller [6,7,8]. The coefficients of the closed-loop characteristic equation are calculated from the Manabe standard form (for the basic CDM adjustment). These coefficients are dependent on the initially assumed time constant τ of the closed-loop system. The output voltage of a closed loop system with the output current treated as an independent disturbance is given by (18)

$$v_{OUT}(s)={\displaystyle \frac{T(s)N(s)}{R(s)D(s)+S(s)N(s)}}{v}_{REF}(s)-{\displaystyle \frac{Z_{OUT}R(s)D(s)}{R(s)D(s)+S(s)N(s)}}{I}_{OUT}(s)$$

(18)

where N(s) contains all the loop delays. The characteristic equation of a closed-loop discrete system is given by (19)

$$P(z^{-1})=R(z^{-1})D(z^{-1})+S(z^{-1})N(z^{-1})={\displaystyle \sum _{i=0}^n{p}_{zi}}{z}^{-i}$$

(19)

A PWM digital modulator implements a delay equal to the one switching period, 3-level double edge modulation innately implements one more switching period delay [22], and finally, the VSI transfer function including the PWM modulator is given by (20)

$$K_{VSI}={\displaystyle \frac{N}{D}}={\displaystyle \frac{a_2{z}^{-2}+a_3{z}^{-3}}{1+b_1{z}^{-1}+b_2{z}^{-2}}}$$

(20)

where for coefficients from (17) we receive (21)

$$a_2={\displaystyle \frac{T_s}{V_{DC}}}{g}_{11},a_3={\displaystyle \frac{T_s}{V_{DC}}}({\phi }_{12}{g}_{21}-{\phi }_{22}{g}_{11}) ,b_1=-({\phi }_{11}+{\phi }_{22}),b_2={\phi }_{11}{\phi }_{22}-{\phi }_{12}{\phi }_{21}$$

(21)

The degrees of R and S should be greater than or equal to n − 1, where n is the degree of D when the disturbance is present. The sufficient second degree of S and the second degree of R are given in (22). With such S and R polynomials, the CDM controller will be similar to the PID controller.

$$S(z^{-1})={\displaystyle \sum _{i=0}^2{s}_i{z}^{-i} },R(z^{-1})={\displaystyle \sum _{i=0}^2{r}_i{z}^{-i}}, r_0=1$$

(22)

The idea of CDM controller adjustment is to obtain the s_i and r_i coefficients from the solution of the Diophantine Equation (23)

$$(1+r_1{z}^{-1}+r_2{z}^{-2})(1+b_1{z}^{-1}+b_2{z}^{-2})+(s_0+s_1{z}^{-1}+s_2{z}^{-2})(a_2{z}^{-2}+a_3{z}^{-3})=1+{\displaystyle \sum _{i=1}^5{p}_{zi}{z}^{-i}}$$

(23)

which can be presented as (24)

$$\left[\begin{array}{ccccc}1& 0& 0& 0& 0\\ b_1& 1& a_2& 0& 0\\ b_2& b_1& a_3& a_2& 0\\ 0& b_2& 0& a_3& a_2\\ 0& 0& 0& 0& a_3\end{array}\right]\left[\begin{array}{c}{r}_1\\ r_2\\ s_0\\ s_1\\ s_2\end{array}\right]=\left[\begin{array}{c}{p}_{z1}-b_1\\ p_{z2}-b_2\\ p_{z3}\\ p_{z4}\\ p_{z5}\end{array}\right]$$

(24)

where the p_zi are coefficients from the Manabe Standard Form [6,7] and it was assumed that r₀ = p₀ = 1.

The coefficients p_i of the fifth degree of the Manabe standard form for a continuous system are given by (25)

$$\begin{gathered} p_0\left(s^0\right) = 1, p_1\left(s^1\right) = p_0\tau , p_2\left(s^2\right) = 0.4p_0{\tau }^2, p_3\left(s^3\right) = 0.08p_0{\tau }^3, \\ \hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}{p}_4\left(s^4\right) = 0.008p_0{\tau }^4, p_5\left(s^5\right) = 0.0004p_0{\tau }^5 \end{gathered}$$

(25)

where τ is the time constant of a closed-loop system. Lower values of τ lead to output voltage oscillations; higher values of τ lead to slower control. The satisfactory simulation results τ (in the experimental model the required τ was higher, up from 6) were received adjusting it up from 3T_s. The discrete-time characteristic equation was obtained using the zero-order hold method for a discretization cycle of T_s in the MATLAB c2d function (26):

$$K(z)=c2d({\displaystyle \frac{1}{{\displaystyle \sum _{i=0}^5{p}_i(s)s^i}}},T_s)={\displaystyle \frac{{\displaystyle \sum _{i=0}^5{w}_i(z)z^{-i}}}{{\displaystyle \sum _{i=0}^5{p}_{zi}(z^{-1})z^{-i}}}}$$

(26)

The accurate calculation of T(z⁻¹) = t₀ enables v_OUT = v_REF to be maintained in the steady state (27)

$$t_0={\displaystyle \frac{P(z=1)}{N(z=1)}}={\displaystyle \frac{V_{DC}}{T_s}}{\displaystyle \frac{1+p_{z1}+p_{z2}+p_{z3}+p_{z4}+p_{z5}}{{\phi }_{12}{g}_{21}+(1-{\phi }_{22})g_{11}}}$$

(27)

The simulation model used the following parameters: L_F = 2 mH, C_F = 51 μF, R_se = 1 Ω, and f_s = 12,800 Hz, 25,600 Hz, 51,200 Hz. The modulation index M should always be less than unity to allow for the rapid control voltage increase. The difference control law for CDM control is given by (28)

$$v_{CTRL}(k)=-r_1{v}_{CTRL}(k-1)-r_2{v}_{CTRL}(k-2)+t_0{v}_{REF}-s_0{v}_{OUT}(k-1)-s_1{v}_{OUT}(k-2)-s_2{v}_{OUT}(k-3)$$

(28)

Scaling coefficients in the Matlab simulation is easy—comparing the measured signal with the reference sinusoidal waveform with the amplitude which is always lower than unity. So, the input controller voltage should be divided by V_DC for the V_DC input inverter voltage. There are many solutions for control in systems with a delay [28,29,30,31,32,33]. One of the most common solutions is the Smith Predictor [30,33] for inverter control [34,35]. We will choose the best time constant τ for which the total harmonic distortions of the VSI output voltage for the nonlinear rectifier RC load are lowest. The coefficients of the CDM controller are calculated for each time constant τ for the system without delay. Figure 6 presents the VSI with the basic Smith Predictor.

The system with the controller with the Smith Predictor is described by (29). The transfer function from Equation (18) and the control law (28) are now modified for implementing the Smith Predictor from Figure 6.

$$V_{OUT}={\displaystyle \frac{t_{0}N(z^{-1})}{D(z^{-1})R(z^{-1})+S(z^{-1})N(z^{-1})+S(z^{-1})N(z^{-1})(1-z^{-n})}}{V}_{REF}$$

(29)

The discrete control law is (30)

$$\begin{array}{l}{V}_{CTRL}=V_{REF}{t}_0(1+b_1{z}^{-1}+b_2{z}^{-2})-V_{OUT}(s_0+(s_0{b}_1+s_1)z^{-1}+(s_0{b}_2+s_1{b}_1+s_2)z^{-2}+(s_1{b}_2+s_2{b}_1)z^{-3}+s_2{b}_2{z}^{-4})-\\ -V_{CTRL}[(b_1+r_1)z^{-1}+(b_2+r_1{b}_1+r_2+s_0{a}_2)z^{-2}+(r_1{b}_2+r_2{b}_1+s_0{a}_3+s_1{a}_2)z^{-3}+\\ +(r_2{b}_2+s_1{a}_3+s_2{a}_2)z^{-4}+s_2{a}_3{z}^{-5}-s_0{a}_2{z}^{-2-n}-(s_0{a}_3+s_1{a}_2)z^{-3-n}-(s_1{a}_3+s_2{a}_2)z^{-4-n}-s_2{a}_3{z}^{-5-n}]\end{array}$$

(30)

Figure 7 presents the simulation model with the controller realizing (30). There is the possibility to adjust the n in the Smith Predictor. The measurement channel is modeled by a scaling unit, a Zero-Order-Hold unit simulating an analog-to-digital converter and a 2T_s delay. It was assumed that there is no mismatch problem of inaccurate modeling plants; however, the delay in the Smith Predictor can be adjusted to defeat the possible temporal mismatch. For n = 0, the control law (30) is the same as (28). Figure 8, Figure 9 and Figure 10 show that in the case of SISO-CDM, Smith Prediction is useful for the fast control (τ = 3T_s) for the low and middle switching frequency because it reduces oscillations caused by the delay in the measurement channel. The higher the switching frequency, the lower the total harmonic distortion (THD) of the output voltage without the prediction (the delay is low). And for the f_s = 51,200 Hz, for τ = 4T_s (78 μs), simulation THD is very low (0.3%) without any control improvements. It can be noticed in

Table 1. THD of the output VSI voltage (simulation) for the SISO-CDM control.

fs [Hz]	Open Loop THD	CDM, τ = 3Ts, THD	CDM + Smith P., τ = 3Ts, THD	CDM, τ = 4Ts, THD	CDM + Smith P., τ = 4Ts, THD
12,800	6.80%	3.27%	3.06%	3.06%	3.27%
25,600	6.80%	4.27%	1.83%	1.10%	1.88%
51,200	6.80%	1.21%	0.85%	0.31%	0.89%

that the output voltage THD for the particular switching frequency for the CDM controller with the Smith Predictor does not depend on the time constant of the closed loop system. However, the conclusions from the further experimental verification are simpler and more clear—the prediction is useful for the low switching frequency.

6. The MISO-PBC Controller of VSI

The output current in the presented previously SISO control is only the unmeasured independent disturbance. Figure 10d shows that SISO-CDM control is efficient in decreasing the THD of the VSI output voltage but for the higher load, it can be worse. A much more sophisticated solution is to measure the output current and treat it as the state variable (in some cases it can be treated as the measured independent disturbance [15]). The other state variables are the filter inductor current and the output voltage. The control based on the calculation of the energy stored in the VSI system (in the filter inductor and the filter capacitor) is Passivity Based Control [9,10,11,12,13,14,15,36,37] considering the energy stored in the system (Hamiltonian function (31), similar to Lyapunov function [14] describes energy stored in the VSI) that should be lower than the energy delivered to the system. The control solution is “injecting” the virtual “resistance” R_i (R_i is the current gain) into the system. In the improved PBC [14,15], the output voltage error is directly implemented in the control law (the voltage gain is K_v).

$$H(x)={\displaystyle \frac{1}{2}}(L_F{i_{LF}}^2+C_F{v_{OUT}}^2)$$

(31)

The discrete control laws of PBC [3] according to Figure 1 where we consider predicted state variables are (32) and (33)

$${\widehat{v}}_{CTRL}(k)=-R_i{\widehat{i}}_{LF}(k)+(R_i+R_{se}){\widehat{i}}_{LFref}(k)+L_F{\displaystyle \frac{{\widehat{i}}_{LFref}(k)-{\widehat{i}}_{LFref}(k-1)}{T_c}}+v_{REF}(k)$$

(32)

$${\widehat{i}}_{LFref}(k)=K_v[v_{REF}(k)-{\widehat{v}}_{OUT}(k)]+C_F{\displaystyle \frac{v_{REF}(k)-v_{REF}(k-1)}{T_c}}+{\widehat{i}}_{OUT}(k)$$

(33)

In the idealized continuous version of PBC for R_se + R_i > 0 and K_v > 0, the roots of the characteristic equation of the closed loop system with PBC are always in the left half-plane s, which makes the system stable [37]. However, the upper limits of the gains exist in the real device because the 3-level modulation PWM modulator has a limited output voltage speed increase, V_DC/T_s. The increase in the control voltage from (32) cannot be faster than (34).

$$\left|{\displaystyle \frac{d{v}_{CTRL}(k{T}_s)}{dt}}\right|\le {\displaystyle \frac{V_{DC}}{T_s}}$$

(34)

The simplified restriction (34) for the worst case of the inverter load R_LOAD = ∞ for the system without delays is (35) [16].

$$K_v[L_F+(R_i+R_{se})T_s]{\displaystyle \frac{1}{L_F{C}_F}}+{\displaystyle \frac{R_i}{L_F}}<f_s$$

(35)

The product R_iK_v is restricted depending on the switching frequency f_s. The convergence of error is faster for the higher values of error gains. However, the higher values of the gains cause saturation of the PWM modulator and can cause output voltage oscillations. The PBC control results in a lower THD of the output voltage for the higher switching frequency, which is also owing to the possibility of higher current and voltage gains. Figure 11 presents the possible operating areas of PBC as a function of gains R_i, K_v, and f_s. The presented relation (35) is approximated and the fine adjustments should be conducted in the control of the simulation model (with delays in the measurement channels) or the experimental model.

Figure 12 shows the Matlab/Simulink simulation model of the VSI with delays in the measurement channels, with the PBC controller (Equations (32) and (33)), without any prediction of the state variables.

Figure 13 presents the simulated VSI output voltage for the standard nonlinear load (PF = 0.7) for PBC for three switching frequencies, 12,800 Hz, 25,600 Hz, and 51,200 Hz, for an inverter with delays (2T_s) in the measurement channels and analog-to-digital converters (Zero-Order-Hold units). The simulation model VSI without feedback has THD = 6.8%. It should be noticed that delays 2T_s in the measurement channels for f_s = 51,200 Hz are so small that VSI can operate without any prediction (Figure 13c). The controller gains R_i and K_v were set as the highest possible below output voltage oscillations and they are approximately from the border of the operating area in Figure 11. The modulation index M = 0.5 was especially low to avoid saturation of the PWM modulator for the increases in the control voltage.

It can be seen from Figure 13 that for the low (12,800 Hz) switching frequency there is a need for state variable prediction. For the middle (25,600 Hz) and high switching frequency (51,200 Hz), there is no need for the prediction. The state variables of the model should be predicted in the next switching periods using the state space equations with the correction component. The full-order state Luenberger Observer [38,39,40,41] will be used. Observers are widely implemented in inverter controls [42,43,44,45]. The state equations were described (12).

y = x, C_D = eye(3)

(36)

The predicted state variables using the Luenberger Observer are described by (37).

$$\widehat{x}(k+1)=A_{\mathrm{D}}\widehat{x}(k)+G_{\mathrm{D}}{T}_{ON}(k)+L[y(k)-C_{\mathrm{D}}\widehat{x}(k)]$$

(37)

The error system is described by Equation (38).

$$e(k+1)=(A_{\mathrm{D}}-L{C}_{\mathrm{D}})[x(k)-\widehat{x}(k)]=(A_{\mathrm{D}}-L{C}_{\mathrm{D}})e(k)$$

(38)

For three measured state variables, the matrix of Luenberger Observer gains is (39).

$$L=\left[\begin{array}{ccc}{l}_1& 0& 0\\ 0& l_2& 0\\ 0& 0& l_3\end{array}\right]$$

(39)

The characteristic equation of the full-state Luenberger Observer is (40) and (41).

$$\det (zeye(3)-A_{\mathrm{D}}+L{C}_{\mathrm{D}})=0$$

(40)

$$\det \left[\begin{array}{ccc}z-{\phi }_{11}+l_1& -{\phi }_{12}& -{\phi }_{13}\\ -{\phi }_{21}& z-{\phi }_{22}+l_2& -{\phi }_{23}\\ 0& 0& z-1+l_3\end{array}\right]=0$$

(41)

The roots of the characteristic equation of the observer (41) are independent of the closed-feedback-loop control system according to the “separation theorem” [41]. The observer eigenvalues should enable a faster convergence to zero of the observation error than the transient process in a closed-loop system. Better observer dynamics are obtained if the roots of their characteristic Equation (41) are closer to zero on the z-plane (their absolute value is lower) than the roots of the characteristic equation of the closed-loop system without prediction. The modifications of the Luenberger Observer are mainly connected with the value of the observer characteristic equation roots vs. the closed-loop system characteristic equation roots. E.g., in [41], the Luenberger observer was designed with its dynamics three times faster than the fastest pole of the plant. In [43], the observer poles are selected to be about 0.8 times closer to the origin than the open loop poles at the same phase angle. The values of l₁, l₂, and l₃ are set so that the system (38) is stable and sufficiently fast. There are three roots of the (41) characteristic equation. The roots z_i will be compared with the roots of the closed-loop system in the z-plane (25). The closed loop PBC system is described in [15] by Equation (42). However, the state variables are restricted now to inductor current and output voltage functions. The output current is treated as an independent disturbance. The characteristic equation of the closed-loop VSI is (43) and (44).

$$\dot{e}=[J-(R+R_a)]P^{-1}e$$

(42)

where

$$e=\left[\begin{array}{c}{L}_F(i_{LF}-i_{LFref})\\ C_F(v_{OUT}-v_{OUTref})\end{array}\right]=P\left[\begin{array}{c}{i}_{LF}-i_{LFref}\\ v_{OUT}-v_{OUTref}\end{array}\right]$$

$$P=\left[\begin{array}{cc}{L}_F& 0\\ 0& C_F\end{array}\right] , P^{-1}=\left[\begin{array}{cc}1/L_F& 0\\ 0& 1/C_F\end{array}\right], R=\left[\begin{array}{cc}{R}_{se}& 0\\ 0& 0\end{array}\right], R_a=\left[\begin{array}{cc}{R}_i& 0\\ 0& K_v\end{array}\right], J=\left[\begin{array}{cc}0& -1\\ 1& 0\end{array}\right]$$

$$\det \{seye(2)-[J-(R+R_a)]P^{-1}\}=\left[\begin{array}{cc}s+(R_{se}+R_i)1/L_F& 1/C_F\\ -1/L_F& s+K_v/C_F\end{array}\right]=0$$

(43)

$$s^2+s{\displaystyle \frac{K_v{L}_F+(R_{se}+R_i)C_F}{C_F{L}_F}}+{\displaystyle \frac{1+K_v(R_{se}+R_i)}{C_F{L}_F}}=0$$

(44)

The characteristic equation is discretized (Matlab c2d function) with the ZOH method for the T_s switching period (45), where coefficients c₀ and c₁ are calculated in Matlab. The roots of the (44) characteristic equation are always in the left s-half-plane, so the roots of the discretized Equation (45) are in the unity circle in the z-plane.

$$z^2+c_{1}z+c_0=0$$

(45)

Figure 14 presents the simulation model of the VSI with PBC controller (32), (33), and the Luenberger Observer (37).

Figure 15 presents the result of using the Luenberger Observer with MISO-PBC controller for different switching frequencies. Prediction is useful (it reduces THD for the nonlinear rectifier RC load with PF = 0.7) for the low switching frequency (12,800 Hz) but is useless for higher switching frequencies (25,600 Hz, 51,200 Hz). The reason is the frequency-dependent characteristic of the measurement channels, in which delays in the frequency range below the resonant frequency of the output filter are simply equal to some (2 or 3) switching periods. For the high switching frequency, the delay is low and the additional processing of signals can only increase the output voltage distortions (

Table 2. THD of the output VSI voltage (simulation) for the MISO-PBC control.

fs [Hz]	Open Loop THD	PBC	PBC + Luenberger Observer (l1 = 1.2, l2 = 1.2, l3 = 0.8)
12,800	THD = 6.80%	Ri = 3, Kv = 0.1, THD = 4.65%	Ri = 5, Kv = 0.1 THD = 3.45%
25,600	THD = 6.80%	Ri = 5, Kv = 0.3, THD = 0.89%	Ri = 5, Kv = 0.3, THD = 1.77%
51,200	THD = 6.80%	Ri = 20, Kv = 0.3, THD = 0.27%	Ri = 5, Kv = 0.3, THD = 2.34%

).

7. The Experimental Verification

In every piece of research, experimental verification is required. One of the most important problems in the control of the real VSI is adjustment scaling factors in the measurement channels. Their wrong adjustment can completely change controller gains. The presented low-power experimental VSI can be driven by an evaluation board with the STM32F407VG processor or the real-time-interface MicroLabBox RTI1202 enabling driving VSI directly from MATLAB/Simulink 2021b with dSpace Release 2021-B libraries. Adjustment of the scaling factors of the measurement channels in the case of microprocessor usage was presented in [46]. Much simpler is setting scaling factors for VSI driven by RTI1202. The borders of the reference waveform in the case of dSpace usage should be equal to the reference voltage. The gain in the voltage measurement channel should be adjusted for the open loop, the nominal output voltage, and the load (50 Ω) in the reference voltage range (Figure 16—printscreen from the dSpace ControlDesk 7.5).

The gain in the output current measuring channel should be set (the gain block) to the reference range and divided by the connected load resistance—50. A similar procedure should be performed with the inductor current measurement channel; however, there is an additional output capacitor current. These adjustments can be easily implemented using dSpace ControlDesk 7.5 software (Figure 16). All the simulation schema is located inside the function block. For the MISO-PBC the 3 independent ADCs triggered by PWM events are used. The interrupt of channel 1 of the first ADC, when data are ready, calls the whole function block. The PBC controller directly realizes control laws (32) and (33). The Luenberger Observer realizes Equation (37). For SISO-CDM only, the first ADC for the output voltage conversion is used. The modulation scheme is realized as shown in Figure 2. MicroLabBox measures the output voltage, output current, and inductor current and drives two legs of the H-bridge according to Figure 2. The gains R_i and K_v for the PBC controller without predictor were adjusted to obtain the lowest THD of the output voltage without oscillations. The higher values of the gains caused output voltage oscillations. The Luenaberger Observer l₁, l₂, and l₃ gains were set to 1.2, 1.2, and 0.8, respectively, to fill the requirement that the roots of its characteristic equation are closer to zero in the z-plane than the roots of the characteristic equation of the closed-loop system (Figure 15). The problem with the compilation of the control schema with the Luenberger Observer is the need to implement one switching period delay unit in the loop from control voltage to observer. In simulations, there was no such requirement. Figure 17, Figure 18 and Figure 19 present the schemas of control for RTI1202.

Figure 20 presents the VSI output voltage distortions and the output voltage harmonics for the nonlinear rectifier RC load (430 μF, 100 Ω, PF = 0.7) for the open loop operation. The presented THD and harmonics can be treated as the reference for the utility of systems with CDM and PBC control with or without prediction controllers. Figure 21a,b presents the fact that the CDM is ineffective for the low switching frequency (12,800 Hz). The system’s time constant was set to τ = 6 for the low and middle switching frequency and τ = 8 for the high frequency because the experimental VSI for the lower value tended to the output voltage oscillations. The Smith Predictor (for n = 2) reduced harmonics (Figure 21c,d vs. Figure 21a,b) for the low switching frequency. This is not quite according to the simulation results where the Smith Predictor damped harmonics only for the lower time constant (τ = 3). For the middle (25,600 Hz, Figure 22c,d vs. Figure 22a,b) and high switching frequency (51,200 Hz, Figure 23c,d vs. Figure 23a,b), the CDM controller operates very well, and adding the Smith Predictor is useless or can even increase slightly THD. The reason is a small delay in the measurement channel for the high switching frequency.

Similar measurements were proceeded for the VSI with the PBC controller or PBC controller with the Luenberger Observer for Luenberger gains l₁ = 1,2, l₂ = 1,2, l₃ = 0.8. The results of the measurements shown in Figure 24c,d vs. Figure 24a,b, Figure 25c,d vs. Figure 25a,b and Figure 26c,d vs. Figure 26a,b have the same tendency as that described previously—the prediction (using full-state Luenberger Observer) is useful for the low switching frequency (12,800 Hz) but is useless or harmful for the middle (25,600 Hz) or high (51,200 Hz) switching frequency. The experimental VSI with RTI1202 is presented in Figure 27.

In

Table 3. THD of the output VSI voltage (measurement) for the SISO-CDM control.

fs [Hz]	Open Loop THD	CDM	CDM + Smith Predictor (n = 2)
12,800	THD = 6.80%	τ = 6, THD = 5.5%	τ = 6, THD = 4.4%
25,600	THD = 6.80%	τ = 6, THD = 3.1%	τ = 6, THD = 3.6%
51,200	THD = 6.80%	τ = 8, THD = 1.8%	τ = 8, THD = 2%

and

Table 4. THD of the output VSI voltage (measurement) for the MISO-PBC control.

fs [Hz]	Open Loop THD	PBC	PBC + Luenberger Observer (l1 = 1.2, l2 = 1.2, l3 = 0.8)
12,800	THD = 6.80%	Ri = 5, Kv = 0.2, THD = 4.4%	Ri = 15, Kv = 0.4 THD = 3.0%
25,600	THD = 6.80%	Ri = 10, Kv = 0.3, THD = 2.3%	Ri = 20, Kv = 0.3, THD = 3.1%
51,200	THD = 6.80%	Ri = 15, Kv = 0.3, THD = 1.9%	Ri = 30, Kv = 0.2, THD = 2.2%

, the THD of the measured VSI output voltage (displayed in Figure 20, Figure 21, Figure 22, Figure 23, Figure 24, Figure 25 and Figure 26) is presented. In both cases of SISO-CDM or MISO-PBC, the prediction was useful (decreased the THD) only for the low switching frequency (12,800 Hz) but was unnecessary for the middle (25,600 Hz) or the high switching frequency (51,200 Hz).

8. Discussion

The paper presents the operation of VSI with three switching frequencies—low: 12,800 Hz, medium: 25,600 Hz, and high: 51,200 Hz (output PWM signal has a doubled frequency in the used modulation scheme—Figure 1). The MicroLabBox Real-Time Unit 1202 was used to drive the VSI experimental model. The measurements of Bode plots of the experimental inverter with MOSFET IRFP360LC bridge transistors, MKP 51 μF filter capacitor, and the 2 mH filter coil (DC resistance 0.2 Ω) with MS—Sendust (iron, silicon, and aluminum alloy-powder material) core [18] showed that in the microprocessor controlled system, measurement channels in the range below the resonant frequency of the VSI output filter can be easily modeled as the delay equal to 2 or 3 switching (equal to sampling) periods T_s. The equivalent serial resistance R_se that is the power conversion loss coefficient was calculated from the measured magnitude Bode plot. In further simulations, it was assigned as R_se = 1 Ω. It was presented that the increase in the switching frequency from 12,800 Hz to 51,200 Hz decreases (for the nominal resistive load) the power efficiency by only about 0.5% for the standard Si transistors (for WBG-SiC MOSFET transistors it would be less) and the standard alloy-powder coil core. Two controllers (SISO-CDM and MISO-PBC) were simulated in the system where the measurement channels were substituted with a Zero-Order-Hold unit simulating an analog to digital converter, with delay components 2T_s and with the scaling units. The load was rectifier RC load with the serial resistor 1 Ω and parallel resistor 100 Ω and capacitor 430 μF, to obtain power factor PF = 0.7 according to the EN 62,040 standard [47]. This is a standard load for the UPS systems below 3 kW. Parameters of the SISO-CDM controller were simply solutions of the Equations (24) and (27) for assumed time constants of the closed loop VSI (simulations: τ = 3T_s and 4T_s and experimental verification: τ = 6T_s and τ = 8T_s). Gains of the MISO-PBC controller should be positive and less than the border of the operating area (Figure 11); however, they should be adjusted for the lowest output voltage distortions (Figure 11 is only an approximation). The results of simulations—THD of the VSI output voltage for both SISO and MISO controllers are presented adequately in Table 1 and Table 2 and measurements in Table 3 and Table 4. In a system with SISO-CDM, the Smith Predictor was implemented to compensate for the delay in the output voltage measurement channel. The delay used in the Smith Predictor was adjusted (the value of 2T_s results in the lowest THD in the experimental verification). The full-state Luenberger Observer was implemented in a system with MISO-PBC. The gains of the Luenberger Observer were chosen to set the roots of the characteristic equation of the Luenberger Observer closer to the origin of the z-plane than the roots of the characteristic equation of the closed-loop system with PBC. The results of SISO-CDM with the Smith Predictor show that the Smith predictor is useful for low frequencies and decreases THD. For the middle (25,600 Hz) and high switching frequency (51,200 Hz), there is no need to use the Smith Predictor in any case of the experimental verification. The results of simulating/experimental verification of MISO-PBC with the Luenberger Observer are similar. The Luenberger Observer reduces THD for the low switching frequency; it is useless for the middle (25,500 Hz) and high (51,200 Hz) switching frequencies and it even slightly increases THD. The reason can be a long computational trace (Luenberger Observer and PBC controller) of the measured signal. The current and voltage gains of PBC were set in every case to obtain the lowest THD and reduce oscillations of the output voltage. The conclusion made from the simulation results is that using the higher switching frequencies causes a very low decrease in efficiency (even for standard bridge transistors and the standard alloy-powder coil core) but helps to simplify the feedback and reduce output voltage distortions. However, if we need a low switching frequency (e.g., 12,800 Hz), the prediction is useful. The prediction reduces oscillations of the output voltage in this case and enables us to use higher current and voltage gains. For the higher switching frequencies, the voltage and current gains of the PBC can be higher (Figure 11), and the distortions of the output voltage are lower.

9. Conclusions

The simulations and their experimental verification in the laboratory inverter with the standard components (Si-MOSFETs, MS-Sendust coil core) prove that increasing the switching frequency from 12,800 Hz to 51,200 Hz only negligibly reduces power efficiency; still, it results in the lower distortions of the VSI output voltage owing to smaller delays in the digitally controlled system (the delays in the measurement channels mainly depend on the switching frequency for the range below the resonant frequency of the output filter) and enables PBC to have the possible higher voltage and current gains, reducing THD of the output voltage. The system with the low switching frequency requires additional prediction of the measured variables. The digital control system with the high switching frequency does not need any prediction, what is more, the additional units (the Smith Predictor or the Luenberger Observer) slightly increase the output distortions (the measured signals are unnecessarily additionally computed). These conclusions concern both SISO and MISO controllers.