Design and Implementation of Bridgeless Power Factor Corrector with Low Static Losses

Abstract

Research and development of power factor corrector (PFC) for AC/DC converters of single-phase AC power supply network are discussed within this article. Two-channel bridgeless PFC is proposed in this paper. The proposed converter allows us to lower current DC component generation in the power network and to reduce static and dynamic losses of semiconductor devices. The suggested solution characteristic features are the absence of a diode bridge while using two identical converters operating in different power network voltage half periods. Due to cumulative chokes in each converter, the function setting the consumption current sinusoidal form is realized with the ability of wide-range output voltage regulation. A number of Simulink-models have been developed in order to study operating modes and to test control algorithms of the proposed bridgeless PFC. The input current harmonic content, efficiency coefficient, passive elements’ electrical parameters, and output voltage pulsation coefficient of the proposed bridgeless PFC were researched by Simulink-models. The results obtained show the efficiency of the proposed solutions regarding PFC. The THD value does not exceed 1.3% in steady state mode and is not over 4% during the voltage stabilization process; the minimal value of the output voltage pulsation coefficient is 3.1%. The suggested solutions can be applied in accumulator batteries’ charging sets and DC motors’ reduced-current start.

1. Introduction

The rate of implementing energy storage devices based on electrochemical accumulator batteries is increasing each year. Intensive development of this area is largely connected to wider use of renewable energy sources and electrical means of transportation [1,2,3]. Battery charging sets based on AC/DC converters are widely used to charge accumulator batteries. An example of this is charging accumulator batteries from a central electrical network or local energy sources such as wind power generators.

When charging accumulator batteries, the converter output voltage can vary over a wide range, being higher or lower than the output voltage average value. As a result, the power network pulse current will contain a broad spectrum of harmonic content. This will negatively affect both the charger measuring elements’ operation and the power network parameters’ distortion. The prospective solution of this problem is using a power factor corrector (PFC) for AC–DC conversion [4,5].

The main PFC function is power network current rise, which is proportional to input voltage. This provides a high power factor and low harmonic factor of consumption current [6,7]. The PFC operating principle is to create an additional path for line current flow in the load quiescent periods. PFCs incorporate chokes for energy storage. PFCs present a range of applications covering various classes of power converters found in home appliances, industry (feeding direct current drives, electrolysis systems), etc.

Nowadays, many different PFC topologies have been proposed [8]. PFCs are widely used in up to 10 kW power converters; the majority of PFC topologies are targeted at single-phase network connection. In general, the following major differences between PFC topologies can be singled out:

• Galvanic decoupling between input and output [9,10,11];
• Common neutral between electric power network and load [12,13];
• Scalability due to connecting additional conversion channels [14,15,16];
• Additional soft commutation circuits [17,18,19].

A simple diagram of PFC based on a step-up DC/DC converter is shown in Figure 1 [20].

The basis of the PFC shown in Figure 1 comprises a bridge rectifier, which provides unidirectional current flow, and a step-up DC/DC converter, forming sine current consumed by load. The main disadvantages of this PFC topology are relatively large choke current pulsations and output capacitor current pulsations. Generally, in order to eliminate these drawbacks, either the switching frequency is increased or passive filter parameters are incremented. However, in turn, this leads to an increase in dynamic losses and buildup of the device weight-size parameters.

Based on PFC topology with a step-up DC/DC converter, a number of modified topologies have been developed, which can be classified into three groups according to the scope of the problems:

• Group 1—solutions are focused on reducing the number of semiconductor components in order to lower static and dynamic losses [21,22];
• Group 2—solutions are focused on lowering only dynamic losses using additional quasi-resonant circuits [23,24];
• Group 3—solutions are focused on enabling parallel PFC operation to ensure capacity increase [25,26].

PFC topologies where a DC/DC converter is absent while all active elements are placed on the input bridge should be considered separately (Figure 2) [27,28,29].

Such topologies allow us to reduce the number of semiconductor components connected in series and thus to boost the efficiency coefficient. However, the application area of a PFC based on such topologies is limited by two problems:

• The problem of inability to change output voltage lower than the input voltage value;
• The problem of providing electric safety due to possible occurrence of hazardous potentials at load leads.

Providing electric safety is an important task when developing a PFC. Two methods to enhance electric safety can be singled out—galvanic decoupling between the device input and output and common neutral of electric power network and load [30,31,32].

Figure 3 shows a diagram of PFC with galvanic isolation [33].

PFC comprises a transformer, with its primary winding in the step-up converter circuit. The transformer secondary winding is connected to the output uncontrolled rectifier. The main drawback of this solution is reduction in energy efficiency due to a large number of semiconductor and passive components in the path for current flow. Control algorithm realization also becomes more complicated in this scheme, as additional measuring circuits of current values and converter circuit voltages are required.

A more preferable method to enhance electric safety is using common neutral of electric power network and load. However, in the above PFC topologies, this solution implementation is impossible due to the diode bridge at the input. The so-called Cuk converter allows us to realize common neutral of electric power network and load (Figure 4) [12,34,35].

Cuk converter advantages include a wide range of output voltage regulation and minimal dynamic losses. However, such a PFC design is complicated, with two problems.

The first problem is connected to the complexity of stabilizing reactive components’ parameters, as the scheme efficiency is largely dependent on them.

The second problem is that, at negative and positive half periods of the power network, reactive components’ content is different in the paths for line current flow. This results in direct current component generation and the necessity of using control algorithms different from one another.

This paper aims to design and implement a two-channel bridgeless PFC. The proposed PFC has a topology with a common neutral of the electric power network and load and, thus, can be classified as a true bridgeless PFC subtype. The basis of the developed PFC is formed by a topology with inverting DC/DC converter, allowing us to regulate output voltage both higher and lower than the input voltage value. The distinctive feature of the proposed solution is to abandon an oscillating circuit and to use two identical converters instead that operate in different power network half periods.

This paper is organized as follows. Section 2 shows the proposed bridgeless PFC topology and describes its principles of operation. Simulink-models to study operating modes and control algorithm testing of the proposed bridgeless PFC are presented in Section 3. Simulation modeling results and their analysis are listed in Section 4.

2. Materials and Methods

2.1. The Proposed Topology

Figure 5 shows the proposed bridgeless PFC circuit.

The proposed bridgeless PFC comprises four main blocks:

• Block 1—input high-frequency filter;
• Block 2—inverting converter, functioning in positive half period of circuit voltage;
• Block 3—amplifier-inverter, functioning in negative half period of circuit voltage;
• Block 4—capacitor filter and direct current load.

The peculiarity of this solution is the common neutral of the electric power network and load, as well as reducing the number of simultaneously operating semiconductor elements. The proposed topology has the following advantages:

• The converter output voltage can vary within the range from zero to a value five times exceeding the input voltage average value. This is achieved by the inverting converter topology.
• Same-type converters are used in the proposed bridgeless PFC. Consequently, operation algorithms in different half periods are also the same. This allows reducing zero-sequence current generation into the power network.
• The number of semiconductor components that operate simultaneously is minimal. This allows decreasing static and dynamic losses.

In the meantime, the disadvantage of the proposed bridgeless PFC topology is the large number of semiconductor components.

The proposed bridgeless PFC equivalent circuit diagram is shown in Figure 6.

Equations were composed based on functional properties of the equivalent circuit elements. These equations describe electrical parameters’ changes in different modes, including active elements’ stray parameters.

2.2. Principle of Operation

According to power network paths for current flow and load current, four modes have been singled out.

2.2.1. Mode 1: ($t_{p1}-{ t}_{p0}$)

In circuit voltage positive half period with on transistors VT1 and VT3, choke L2 is charged (Figure 7).

In this mode, the principle circuit current (Iin) increases and flows through the following path: L (power network phase)–L1–VT1–L2–VT3–N. A small part of the circuit current (I_C1) in this mode flows through the input filter capacitor (C₁). Loading current (I_load) reduces and flows through path C2–R.

Equations describing this mode have the following form:

$$\{\begin{array}{c}{E}_m·\sin (\omega ·t_{p1})=\frac{i_{\mathit{in}}(t_{p1})+i_{\mathit{in}}(t_{p0})}{2}·R_{L1}+L_1·\frac{i_{\mathit{in}}(t_{p1})+i_{\mathit{in}}(t_{p0})}{t_{p1}-t_{p0}}\\ +\frac{1}{C_1}·\frac{i_{C1}{(t}_{p1})+i_{C1}{(t}_{p0})}{2}·[t_{p1}-t_{p0}]+u_{C1}(t_{p0})\\ E_m·\sin (\omega ·t_{p1})-2·E_{\mathit{VT}}=\frac{i_{\mathit{in}}(t_{p1})+i_{\mathit{in}}(t_{p0})}{2}·R_{L1}+\frac{i_{\mathit{chL}2}(t_{p1})+i_{\mathit{chL}2}(t_{p0})}{2}\\ ·(2·R_{\mathit{VT}}+R_{L2})+L_1·\frac{i_{\mathit{in}}{(t}_{p1})+i_{\mathit{in}}{(t}_{p0})}{t_{p1}-t_{p0}}+L_2·\frac{i_{\mathit{chL}2}{(t}_{p1})+i_{\mathit{chL}2}{(t}_{p0})}{t_{p1}-t_{p0}}\\ \frac{i_{\mathit{in}}{(t}_{p1})+i_{\mathit{in}}{(t}_{p0})}{2}=\frac{i_{C1}{(t}_{p1})+i_{C1}{(t}_{p0})}{2}+\frac{i_{\mathit{chL}2}{(t}_{p1})+i_{\mathit{chL}2}{(t}_{p0})}{2}\\ u_{C2}{(t}_{p0})=\frac{i_{\mathit{load}}{(t}_{p1})+i_{\mathit{load}}{(t}_{p0})}{2}·R+\frac{1}{C_2}·[\frac{i_{\mathit{load}}{(t}_{p1})+i_{\mathit{load}}{(t}_{p0})}{2}]\\ {·[t}_{p1}-t_{p0}]\end{array}$$

(1)

2.2.2. Mode 2: ($t_{p2}-{ t}_{p1}$)

In positive half period with off-transistors VT1 and VT3, choke L2 is discharged (Figure 8).

In this mode, energy output stored in the choke takes place. Line current flows through the path: L–L1–C1–N. As soon as the input filter impedance for the main frequency is manifold higher than that of the cumulative choke charging circuit, line current starts going down. The cumulative choke discharge current flows through the following path: L2–VD2–R–VD1. At this, part of the choke energy is spent on charging the output capacitor filter, resulting in output voltage and consequently the output current going up.

Equations describing this mode have the following form:

$$\{\begin{array}{c}{E}_m·\sin (\mathsf{\omega }·t_{p2})={\displaystyle \frac{i_{\mathit{in}}{(t}_{p2})+i_{\mathit{in}}{(t}_{p1})}{2}}·R_{L1}+L_1·{\displaystyle \frac{i_{\mathit{in}}{(t}_{p2})+i_{\mathit{in}}{(t}_{p1})}{t_{p2}-t_{p1}}}\\ +{\displaystyle \frac{1}{C_1}}·{\displaystyle \frac{i_{\mathit{in}}{(t}_{p2})+i_{\mathit{in}}{(t}_{p1})}{2}}·{[t}_{p2}-t_{p1}]+u_{C1}{(t}_{p1})\\ -u_{C2}{(t}_{p1})-2·E_{\mathit{VD}}={\displaystyle \frac{i_{\mathit{disL}2}{(t}_{p2})+i_{\mathit{disL}2}{(t}_{p1})}{2}}·{(R}_{L2}+2·R_{\mathit{VD}})\\ +L_2·{\displaystyle \frac{i_{\mathit{disL}2}{(t}_{p2})+i_{\mathit{disL}2}{(t}_{p1})}{t_{p2}-t_{p1}}}+{\displaystyle \frac{1}{C_2}}·[{\displaystyle \frac{i_{C2}{(t}_{p2})+i_{C2}{(t}_{p1})}{2}}]·{[t}_{p2}-t_{p1}]\\ u_{C2}{(t}_{p1})={\displaystyle \frac{i_{\mathit{load}}{(t}_{p2})+i_{\mathit{load}}{(t}_{p1})}{2}}·R-{\displaystyle \frac{1}{C_2}}·[{\displaystyle \frac{i_{C2}{(t}_{p2})+i_{C2}{(t}_{p1})}{2}}]\\ ·{[t}_{p2}-t_{p1}]\\ {\displaystyle \frac{i_{\mathit{disL}2}{(t}_{p2})+i_{\mathit{disL}2}{(t}_{p1})}{2}}={\displaystyle \frac{i_{C2}{(t}_{p2})+i_{C2}{(t}_{p1})}{2}}+{\displaystyle \frac{i_{\mathit{load}}{(t}_{p2})+i_{\mathit{load}}{(t}_{p1})}{2}}\end{array}$$

(2)

2.2.3. Mode 3: ($t_{n1}-{ t}_{n0}$)

In negative half period of circuit voltage with open-end key VT2, choke L3 is charged through path: N–L3–VT2–L1–L (Figure 9).

The path and direction of the load current flow are analogous to mode 1. Equations describing this mode have the following form:

$$\{\begin{array}{c}-E_m·\sin (\mathsf{\omega }·t_{n1})={\displaystyle \frac{i_{\mathit{in}}{(t}_{n1})+i_{\mathit{in}}{(t}_{n0})}{2}}·R_{L1}+L_1·{\displaystyle \frac{i_{\mathit{in}}{(t}_{n1})+i_{\mathit{in}}{(t}_{n0})}{t_{n1}-t_{n0}}}\\ +{\displaystyle \frac{1}{C_1}}·{\displaystyle \frac{i_{C1}{(t}_{n1})+i_{C1}{(t}_{n0})}{2}}·{[t}_{n1}-t_{n0}]-u_{C1}{(t}_{n0})\\ -E_m·\sin (\mathsf{\omega }·t_{n1})-E_{\mathit{VT}}={\displaystyle \frac{i_{\mathit{in}}{(t}_{n1})+i_{\mathit{in}}{(t}_{n0})}{2}}·R_{L1}+{\displaystyle \frac{i_{\mathit{chL}3}{(t}_{n1})+i_{\mathit{chL}3}{(t}_{n0})}{2}}\\ ·{(R}_{\mathit{VT}}+R_{L3})+L_1·{\displaystyle \frac{i_{\mathit{in}}{(t}_{n1})+i_{\mathit{in}}{(t}_{n0})}{t_{n1}-t_{n0}}}+L_3·{\displaystyle \frac{i_{\mathit{chL}3}{(t}_{n1})+i_{\mathit{chL}3}{(t}_{n0})}{t_{n1}-t_{n0}}}\\ {\displaystyle \frac{i_{\mathit{in}}{(t}_{n1})+i_{\mathit{in}}{(t}_{n0})}{2}}={\displaystyle \frac{i_{C1}{(t}_{n1})+i_{C1}{(t}_{n0})}{2}}+{\displaystyle \frac{i_{\mathit{chL}3}{(t}_{n1})+i_{\mathit{chL}3}{(t}_{n0})}{2}}\\ u_{C2}{(t}_{n0})={\displaystyle \frac{i_{\mathit{load}}{(t}_{n1})+i_{\mathit{load}}{(t}_{n0})}{2}}·R+{\displaystyle \frac{1}{C_2}}·[{\displaystyle \frac{i_{\mathit{load}}{(t}_{n1})+i_{\mathit{load}}{(t}_{n0})}{2}}]\\ {·[t}_{n1}-t_{n0}]\end{array}$$

(3)

2.2.4. Mode 4: ($t_{n2}-{ t}_{n1}$)

In negative half period of circuit voltage with closed-end key VT2, choke L3 is discharged (Figure 10).

Line current flows through the path: N–C1–L1–L. Cumulative choke discharge current flows through the path: L3–VD3–R.

For modes 1 and 2, quality changes of currents and voltages are analogous to those in modes 3 and 4. Equations describing this mode have the following form:

$$\{\begin{array}{c}{-E}_m·\sin (\mathsf{\omega }·t_{n2})={\displaystyle \frac{i_{\mathit{in}}{(t}_{n2})+i_{\mathit{in}}{(t}_{n1})}{2}}·R_{L1}+L_1·{\displaystyle \frac{i_{\mathit{in}}{(t}_{n2})+i_{\mathit{in}}{(t}_{n1})}{t_{p2}-t_{p1}}}\\ +{\displaystyle \frac{1}{C_1}}·{\displaystyle \frac{i_{\mathit{in}}{(t}_{n2})+i_{\mathit{in}}{(t}_{n1})}{2}}·{[t}_{n2}-t_{n1}]-u_{C1}{(t}_{n1})\\ -u_{C2}{(t}_{p1})-E_{\mathit{VD}}={\displaystyle \frac{i_{\mathit{disL}3}{(t}_{n2})+i_{\mathit{disL}3}{(t}_{n1})}{2}}·{(R}_{L3}+R_{\mathit{VD}})\\ +L_3·{\displaystyle \frac{i_{\mathit{disL}3}{(t}_{n2})+i_{\mathit{disL}3}{(t}_{n1})}{t_{n2}-t_{n1}}}+{\displaystyle \frac{1}{C_2}}·[{\displaystyle \frac{i_{C2}{(t}_{n2})+i_{C2}{(t}_{n1})}{2}}]·{[t}_{n2}-t_{n1}]\\ u_{C2}{(t}_{n1})={\displaystyle \frac{i_{\mathit{load}}{(t}_{n2})+i_{\mathit{load}}{(t}_{n1})}{2}}·R-{\displaystyle \frac{1}{C_2}}·[{\displaystyle \frac{i_{C2}{(t}_{n2})+i_{C2}{(t}_{n1})}{2}}]\\ ·{[t}_{n2}-t_{n1}]\\ {\displaystyle \frac{i_{\mathit{disL}3}{(t}_{n2})+i_{\mathit{disL}3}{(t}_{n1})}{2}}={\displaystyle \frac{i_{C2}{(t}_{n2})+i_{C2}{(t}_{n1})}{2}}+{\displaystyle \frac{i_{\mathit{load}}{(t}_{n2})+i_{\mathit{load}}{(t}_{n1})}{2}}\end{array}$$

(4)

The forms of writing equations describing the modes almost completely replicate. Small values of voltage dropping on semiconductor components in conducting states do not influence control algorithms and operation of the converter. Various paths for current flow in negative and positive half periods can result in on-load voltage pulsation coefficient increase.

Figure 11 shows the idealized control signal waveforms of power switch in one switching cycle.

2.3. Calculation of Reactive Components’ Parameters

In order to calculate cumulative choke inductance, the following formula was used, taking into consideration load parameters and requirements for current ripple value:

$$L_{2,3}\ge {\displaystyle \frac{2 ·{ U}_{\mathit{load}} · (1-D)}{2 ·∆I_L ·{ f}_S}}.$$

(5)

Input LC-filter parameters were calculated relative to the voltage transfer ratio at power key switching frequency and network frequency.

$${\displaystyle \frac{K_T+1}{{(K}_T·n^2+1)·{(2·\mathsf{\pi }·f_{\mathit{in}})}^2}}\le ·L_1·C_1;$$

(6)

$$1\ge 2·\mathsf{\pi }·f_{\mathit{in}}\sqrt{L_1·C_1}.$$

(7)

Output filter capacitor capacitance was calculated by the following expression:

$$C_2\ge {\displaystyle \frac{P_{\mathit{load}}}{4·\mathsf{\pi }·f_{\mathit{in}}·∆U_{\mathit{load}}·U_{\mathit{load}}}}.$$

(8)

Current and voltage stresses of semiconductor devices are shown in

Table 1. Current and voltage limiting values of semiconductor devices.

Semiconductor	Voltage Stress	Current Stress
VT1	$U_{C1}$	${\displaystyle \frac{I_{L0} ·(1-D_{\max }) }{D_{\max }}}$
VT2	$U_{C1}+U_{\mathit{load}}$	${\displaystyle \frac{I_{L0} ·(1-D_{\max }) }{D_{\max }}}$
VT3	$U_{\mathit{load}}$	${\displaystyle \frac{I_{L0} ·(1-D_{\max }) }{D_{\max }}}$
VD1	$U_{C1}$	${\displaystyle \frac{I_{L0} ·(1-D_{\max }) }{D_{\max }}}$
VD2	$U_{\mathit{load}}$	${\displaystyle \frac{I_{L0} ·(1-D_{\max }) }{D_{\max }}}$
VD3	$U_{C1}+U_{\mathit{load}}$	${\displaystyle \frac{I_{L0} ·(1-D_{\max }) }{D_{\max }}}$

.

2.4. Control Strategy

Semiconductor switch control is based on monitoring current waveform and adjusting it if the waveform deviates from the ideal curve (sinewaves). Figure 12 shows the proposed control strategy.

Source data are the values of input voltage (U_in), input current (I_in), ouput voltage (U_load), and set voltage (U_set). The function setting current is constructed based on the measured input voltage over one period (I_set) whose form replicates input voltage, but its proportionality coefficient (K) is different from it. Following this, the proportionality coefficient is adjusted when the output voltage deviates from the set voltage. If the output voltage exceeds the set voltage, the consumption current goes up due to the set current increase. If the output voltage is lower than the set voltage, the consumption current decreases as well.

The consumption current sinewave form is set according to the following algorithm. If the consumption current form deviates from the set current, the semiconductor key conduction state is changed. The key is closed when the consumption current is exceeded (U_VT = 0). If the consumption current is lower than the set current, the key is unlocked (U_VT = 1).

The proposed control strategy can be elaborated, taking into consideration the necessity to limit the transistor switching frequency.

3. Simulink-Models

The proposed bridgeless PFC Simulink-models have been developed to research operating modes and to test control algorithms.

3.1. Power Circuit Simulink-Model

A power circuit Simulink-model of the proposed bridgeless PFC is shown in Figure 13.

10 kΩ active resistances are parallel-connected to each reactive element in the Simulink-model. It is necessary to ensure that the path for choke and capacitors’ current flow is not broken. The discrete calculation method with fixed 100 nanosecond pitch was used as a solver.

Table 2. Simulink-model elements’ parameters of the proposed bridgeless PFC power circuit.

Chokes
	Inductance, mH	Active resistance, Ω
L1	3.3	0.1
L2	1	0.1
L3	1	0.1
Capacitors
	Capacity, µF	Active resistance, Ω
C1	0.33	0.1
C2	12,000	0.01
Semiconductor elements
	Forward drop, V	Internal resistance, Ω
VD1–VD3	0.8	2
VT1–VT3	1	2

shows the developed Simulink-model elements’ parameters.

Harmonic voltage source with 312 V peak voltage and 50 Hz frequency was used as a primary power supply. Active resistance 0.02 Ω is connected in series to the primary power supply. The introduced active resistance allows taking into consideration losses in the power network. The load power is 2 kW, and the output voltage is 100 V. The switching frequency is in the range from 4 to 35 kHz.

Simulink-model solver parameters are given in

Table 3. Simulink-model solver parameters.

Solver	Simulation Time	Simulation Step
ode4 (Runge-Kutta)	1 s	Fixed-step 100 ns

.

3.2. Control System Simulink-Models

The control system consists of three sub-systems: the sub-system of pre-charging capacitors of output filter; the sub-system of on-load voltage stabilization; and the sub-system of forming control pulses.

Figure 14 shows Simulink-models of pre-charge and voltage stabilization sub-systems.

The pre-charge sub-system is aimed at charging the output filter capacitor up to the voltage value equal to nominal on-load voltage. The difference between pre-charge mode and the nominal operating mode is that charging current value (the consumption current) is set as maximum permissible. This allows shortening the time between the device start and its starting to operate in nominal mode.

The pre-charge function is actuated by the set voltage value and RS-trigger. In order to reduce the time determining the permissible charging current value, current forecasting is used, which is based on observing the power balance. This means that charging the current rough value is determined closer to the end of pre-charge mode according to the known effective voltage values at the input and at the output, as well as by the load current value. If the converter efficiency coefficient is to be considered in the equation, on-load voltage extra-fine tuning is possible without employing additional stabilization circuits.

Figure 15 shows on-load voltage and charging current diagrams.

After pre-charge mode is completed, the sub-system of on-load voltage stabilization starts operating. This is based on an algorithm that determines the value of output on-load voltage deviation from the pre-set value and further continues adjustment of power network consumption current. The essence of the algorithm is the following:

• When on-load voltage decreases, the value of the power network consumption current increases;
• When on-load voltage goes up, the value of the consumption current goes down;
• If on-load voltage is within the preset range, the consumption current stays on the preset level.

The sub-system of pre-charging output filter and on-load voltage stabilization sub-system are connected to the sub-system of forming control pulses, aimed at generating signals sent to power keys. Simulink-model of the sub-system of forming control pulses is shown in Figure 16.

The operating principle of the sub-system of forming control pulses is the following. In the first stage, the range of permissible current values is set, which is changed according to the supply voltage waveform. When the current values go beyond the preset range limits, the control pulse is sent (if the current is lower than the minimum permissible value) or the pulsing is cancelled (if the current is higher than the minimum permissible value). It is noteworthy that, the narrower the bandwidth, the smaller the consumption current pulsation amplitude; thus, the smaller the total harmonic distortion. However, in order for the consumption current pulsation to decrease, the maximum switching frequency should increase; thus, dynamic losses in the converter should go up. A time-pulse generator is used in order to limit switching frequency. The switching frequency upper boundary is 35 kHz. The proposed Simulink-model does not use a switching frequency lower boundary. However, when creating an experimental prototype of the proposed bridgeless PFC, a switching frequency lower boundary will be necessary to prevent chokes from transition to saturation mode.

Figure 17 shows current and voltage diagrams on the elements of the proposed bridgeless PFC.

Currents that flow through the cumulative chokes are almost identical in shape and amplitude values (Figure 17c,d). This confirms the symmetry of the power consumption of the PFC channels. Currents that flow through the power keys are equal in amplitude to the currents of the cumulative chokes (Figure 17h,i). The maximum values of voltage on semiconductor devices correspond to the theoretical provisions, which are given in Table 1.

4. Simulation Modeling Results and Discussion

The following is researched by the developed Simulink-models:

• Harmonic content of power network consumption current;
• Reactive elements’ parameters of the proposed bridgeless PFC;
• Short-circuit current limiting mode parameters.

4.1. Research into Harmonic Content of Power Network Consumption Current

Figure 18 shows a diagram of the power network consumption current when the proposed bridgeless PFC is in operation.

The proposed bridgeless PFC start of operation can be divided into three intervals:

• Pre-charging output filter capacitors (0–0.04 s);
• On-load voltage stabilization (0.04–0.12 s);
• Steady state (0.12–0.3 s).

The high-frequency content amplitude of the network consumption current does not exceed 0.4 A due to input LC-filter.

Harmonic analysis was performed for each interval. The analysis results are shown in Figure 19.

The results obtained have shown that, at on-load voltage stabilization and in steady state mode, total harmonic distortion does not exceed 4% (Figure 19b,c). Consequently, even at frequent load power variations, the consumption current will have minimal values of higher order harmonic.

A constant component of current in the input current harmonic content is prominent only in pre-charge mode and constitutes 10% relative to the first harmonic (Figure 19a). In on-load voltage stabilization mode, zero-phase-sequence in the harmonic content constitutes only 1%, while in steady state, it is practically absent.

In pre-charge and on-load voltage stabilization modes, interharmonics are present in the harmonic content. Their presence negatively impacts the electric power supply system. In steady state, only fundamental harmonic and its multiples are present.

It should be noted that, due to pre-charge short duration, an adverse impact on the power network in this mode is minimal. With frequent recloses absent, it is admissible to discard pre-charge mode when assessing the input current harmonic content.

The results of the input current harmonic analysis at different load powers are given in

Table 4. Input current harmonic analysis at different load powers.

Load Power, kW	Harmonic, %
	2 ≤ h < 11	11 ≤ h < 17	17 ≤ h < 23	23 ≤ h < 35	35 ≤ h < 50
Harmonic limits (IEEE519-2022)	4	2	1.5	0.6	0.3
0.5	11.32	0.41	0.19	0.14	0.12
2	0.5	0.22	0.12	0.10	0.06
3.5	0.57	0.38	0.3	0.21	0.07
5	1.05	0.67	0.35	0.19	0.08
6.5	3.28	1.81	0.74	0.24	0.18
7.5	6.04	2.3	0.48	0.44	0.24

.

In the power range from 2 to 6.5 kW, the values of harmonics comply with the requirements of IEEE519-2022. It is necessary to recalculate the parameters of the cumulative chokes to shift the PFC effective operation range.

Harmonic content was researched with channel parameter asymmetry of the proposed bridgeless PFC. This research was necessary to determine even harmonic values and DC component in the consumption current. In order to simulate the asymmetry, negative channel choke inductance was increased by 10%. Harmonic analysis results of this experiment are given in

Table 5. Input current harmonic analysis with PFC channel asymmetry.

DC, %	h1, %	h2, %	h3, %	h4, %	h5, %	h6, %	h7, %	h8, %	h9, %
0.47	100	0.48	0.46	0.12	0.46	0.11	0.4	0.1	0.33

.

The current DC component and second harmonic do not exceed 0.5% of the fundamental harmonic. This result is obtained due to power keys’ relay-type control method with additional limitations of switching frequency.

4.2. Research into Reactive Elements’ Parameters of the Proposed Bridgeless PFC

Reactive elements’ parameters’ investigation has been performed for the proposed bridgeless PFC. Figure 20 shows a time diagram of on-load voltage change in steady state mode.

Pulsation coefficient was calculated based on the modeling results:

$$q={\displaystyle \frac{U_{\max }-U_{\min }}{2·U_{\mathrm{mean}}}}·100\%={\displaystyle \frac{103.6-97.4}{2·100.5}}·100\%=3.08\%$$

(9)

The obtained pulsation coefficient value is acceptable for most consumers and technological processes. Pulsation coefficient reduction can be achieved by two methods: extension of output filter capacitor capacity, or using the successive converter, operating with higher switching frequency of semiconductor keys.

From Figure 20, it follows that the maximum on-load voltage when the converter is operating in the negative half period of power network voltage is greater than when operating in the positive half period. This is connected to the large number of semiconductor elements in the path for current flow of the inverting converter operating in the network voltage positive half period.

In order to determine maximum voltage values on bridgeless PFC elements, we built diagrams of output filter capacitors’ and cumulative chokes’ voltage dependence on the consumption current rate (Figure 21).

Figure 18 shows voltage non-linear dependences on the consumption current rate. This is explained by two frequencies of output voltage pulsation: doubled frequency of power supply voltage, and power keys’ modulation frequency. At this, the current high-frequency component does not depend on the consumption current rate. Changing the reactive elements’ voltage level is largely connected to changing the current first harmonic component.

4.3. Research into Energy Efficiency of the Proposed Bridgeless PFC

In order to determine optimal operational parameters of the proposed bridgeless PFC, its performance efficiency has been studied at various load power values. Figure 22 shows efficiency coefficient and total harmonic distortion (THD) dependences on load power.

The results were obtained by the Simulink-model. The simulation takes into consideration losses in reactive components and static losses in semiconductor devices. Dynamic losses were disregarded in the simulation.

Three zones can be singled out in the graphs of Figure 22:

• Zone 1: zone of optimal efficiency coefficient values (efficiency coefficient over 85%);
• Zone 2: zone of optimal efficiency coefficient and THD values (efficiency coefficient over 85% and THD lower than 8%);
• Zone 3: zone of optimal THD values (THD lower than 8%).

Thus, optimal operational parameters of the proposed bridgeless PFC are achieved at load power within the 1.7 to 3.3 kW range. For shifting optimal operational zone of the bridgeless PFC, recalculation of input LC-filter is required.

4.4. Research into Functional Capability of Limiting Power Consumption

We carried out Simulink-model-based research to limit power consumption using the proposed bridgeless PFC due to consumption current stabilization. Figure 23 shows diagrams obtained of the consumption current and load current.

The control algorithm determines the converter operating mode. A particular case is when the voltage stabilization mode is realized, provided that the present consumption current rate is lower relative to the maximum set value. Parameters’ change visualization in this mode is shown in Figure 23. As soon as the consumption current reaches the maximum value, the transition from voltage stabilization mode to power stabilization mode takes place by limiting the consumption current.

The strategy for transition from voltage stabilization mode to power stabilization mode is the following. When the consumption current value exceeds the set point value, the consumption current is limited. When connected to the power source with little input voltage deviation, it allows limiting the power consumed from the power network and consequently limiting load power. The disadvantage of this approach is the difference between power consumption and load power. Load power will increase closer to the short-circuit condition as the efficiency coefficient declines. A more efficient approach allowing stabilizing load power with greater precision is to use a current sensor in the output circuit, with load power calculated thereafter.

Consumption current limitation allows use of the proposed bridgeless PFC in power supply load circuits with heavy starting duty without adverse consequences for the power network. Such functional capability ensures power network protection from fault short-circuit currents. However, for technical realization, it will be necessary to use diodes with increased pulse current overload.

4.5. The Proposed Bridgeless PFC Compared to Other PFC Topologies

Performance metrics of the proposed bridgeless PFC were compared with previously considered PFC circuits (Figure 1, Figure 2, Figure 3 and Figure 4), as well as with other PFC topologies of similar power range [8]. The comparison results are given in

Table 6. Simulink-model elements’ parameters of the proposed bridgeless PFC power circuit.

Topology	Power Rating, W	Pf, p.u.	THD, %	Efficiency, %	Voltage Regulation	Cost
Interleaved Boost PFC [36]	100–3400	0.97–0.996	3–24	91–97	Boost	Medium
BridgelesCuK type 2 [37]	100–850	0.999	1.25–1.5	90–96	Buck- Boost	Low
Bridgeless boost [38]	100–3400	0.99	5.5	94–96	Boost	Low
PFC with galvanic isolation [10]	1500	0.99	2	96.7	Buck- Boost	High
Interleaved SEPIC with DBR [39]	1500–3300	0.999	3.43	91–97	Buck- Boost	High
Totem-pole [40]	350	0.98–0.999	>8	96–98	Boost	Low
Proposed bridgeless PFC	1700–3300	0.999	1.29–8	85–90	Buck- Boost	Medium

.

The competitive advantages of the proposed bridgeless PFC are the following: reduced THD, high power coefficient, and large values of maximum output power. The proposed PFC cost can be estimated as average due to two independently functioning converter channels. The most significant disadvantage of the proposed bridgeless PFC is the low efficiency coefficient. Loss of efficiency takes place because of inverting converters operating in each channel. Output voltage increase is one of the methods to boost this type-converter efficiency, allowing reducing voltage drop on the components with the power remaining constant. It is also possible to lower dynamic losses by additional soft commutation circuits.

The proposed bridgeless PFC can be applied in medium-powered electric hand tools, in accumulator battery charges of 100–400 V voltage level, and in other devices requiring a wide range of constant output voltage.

5. Conclusions

Nowadays, application of AC/DC converters, which are used in charging sets, DC-drive power systems, etc., is increasing. The problem of these devices’ operation is their negative impact on the power supply network. One of the prospective solutions of this problem is associated with the power factor corrector (PFC).

This article presents research and development results of a bridgeless power factor corrector with the diode bridge absent but with two identical converters, operating in different power network half periods. Abandoning the input diode bridge allows enhancing the electrical safety due to common neutral of electric power network and load. Two identical converters allow decreasing the number of connected-in-series PFC active elements and to lower static losses.

Performance efficiency of the proposed bridgeless PFC has been researched by the developed Simulink-models.

Modeling results showed that the THD value does not exceed 1.3% in steady state mode and does not exceed 4% during the voltage stabilization process. Investigation of output voltage pulsation coefficient showed that its minimal value was 3.1%. Optimal operational parameters of the proposed bridgeless PFC (efficiency coefficient over 85% and THD lower than 8%) have been determined, which for the circuit in question are achieved at load power within the 1.7 to 3.3 kW range. The proposed bridgeless PFC operation modeling was performed in power consumption limiting mode. This mode can be considered as additional protection from on-load short-circuit currents.

It is planned to create a prototype of the proposed PFC at the next stage, and the prototype will be used for experimental validation to demonstrate the feasibility of the proposed PFC rectifier.

Accumulator battery chargers, electric hand tools, etc., are promising areas of the proposed bridgeless PFC application.