A Bridgeless Cuk-BB-Converter-Based BLDCM Drive for MEV Applications

Abstract

This article presents a brushless DC motor (BLDCM) drive for a maritime electric vehicle (MEV) application. The presented BLDCM drive uses a bridgeless Cuk-buckboost (BL-Cuk-BB) converter for input-side power factor (PF) improvement. The BL-Cuk-BB converter uses the buckboost converter for the negative half-cycles of the input AC voltages and the Cuk converter for the positive half-cycles. In the case of MEVs, the drive systems are generally fed by diesel engine generators (DEGs). The asymmetric BL-Cuk-BB converter is operated in a discontinuous inductor current mode (DICM) in the present work to attain better power quality. The usage of a second-order buckboost converter with a fourth-order Cuk converter results in a decrement in the net order of the system. Additionally, the input inductor of the Cuk converter also participates as the filter component along with capacitor C₂ during buckboost converter operation to enhance the power quality. The total component count reduction in the BL-Cuk-BB converter is also achieved by eliminating the usage of extra/external back-feeding diodes, which are generally used in bridgeless schemes. The present scheme uses the inbuilt anti-parallel diodes for the same purpose. The lesser components requirement in the BL-Cuk-BB-converter-based BLDCM drive implies lesser cost and volume, along with greater reliability, lower conduction losses, and lower weight of the BLDCM drive, which adds to the merits of the model. The paper includes a detailed mathematical model and stability analysis using pole-zero maps and bode plots of the BL-Cuk-BB converter for each half-supply AC voltage cycle. The BL-Cuk-BB-converter-based BLDCM drive for an EV application has been developed on the MATLAB/Simulink platform for a DICM operation, and the MATLAB simulation results have been presented for validation of the BL-Cuk-BB-converter-based BLDCM drive.

1. Introduction

Performance, cost, and efficiency are the major factors associated with a BLDCM, which makes it a suitable choice for numerous low- and medium-power applications [1,2]. Currently, BLDCMs find applications in many areas, such as water pumps, mixers, blowers, fans, household appliances, motion controllers, medical equipment, air conditioners, position actuators, and different transportation sectors [2,3,4,5]. Along with the above-mentioned advantages, lower maintenance, greater flux density per unit volume, robust nature, and fewer electromagnetic interference (EMI) problems are the other factors that determine the state-of-the-art performance of BLDCMs over other motors. So, a BLDCM is a good choice for marine electric vehicle (MEV) applications. MEVs such as motor boats have a diesel engine generator (DEG) as a source to drive the engine. Such MEVs come under the category of an onboard electric vehicle, which not only needs to carry the drive system but also the supply system (DEG). So, vehicle weight is also one of the major concerns which hinder the performance of the vehicle in the case of MEVs. A particular form of synchronous motor known as a BLDCM has three-phase windings on the stator and permanent magnets on the rotor. Hall-effect sensors are mounted on BLDCMs to detect the rotor position, as this is an electronically commutated motor. The motor uses an electronic commutation technique based on rotor positions in place of the mechanical commutation technique. The mechanical commutation technique is associated with certain drawbacks, such as lower precision, the wear and tear of the commutator and brush assembly, and sparking problems, whereas electronic commutation does not have the above-mentioned drawbacks [6,7]. Power quality (PQ) issues are also major problems that hinder the performance of the BLDCM along with other appliances connected to the same utility. The traditional BLDCM drive seems to violate the input current harmonic limits, as per IEC-61000-3-2 [8]. A traditional BLDCM utilizes a diode bridge (DB) rectifier at the supply end followed by a DC-link capacitor-fed inverter connected to a BLDCM. The traditional drive with a DB rectifier seems to draw a peaky supply AC, and the harmonic distortion in the supply current is found as high as 65% with a poor power factor [9]. So, to enhance power quality at the supply side, a converter is introduced next to the diode bridge (DB) rectifier in the BLDCM drive for power factor (PF) correction. Many PF-correction single-stage-converter-based schemes have been reported in the literature [10]. Single-stage converters seem to have an upper hand over two-stage converters due to a reduction in one stage, which implies a reduction in components and also the losses associated with them [10,11]. The PF-corrected converter operation mode is to be decided very carefully because it is one of the major parameters deciding the converter components’ ratings and cost. In [10], the PFC converter is designed to operate in continuous conduction mode (CCM), whereas in [11], the PFC converter is designed to operate in a discontinuous inductor current mode (DICM). CCM operation is associated with continuous capacitor voltage or continuous inductor current; however, CCM operation requires two voltage sensors and a current sensor for sensing DC-link voltage, supply voltage, and supply current, respectively, for PF-correction operation, which is never a cost-effective solution. However, DICM operation requires a single sensor to sense DC-link voltage to achieve PF correction at the supply mains, despite reverse switches of the PF-correction converter in the DICM suffering greater electrical stresses. So, it can be concluded that DICM should be preferred over CCM operation for low-power applications [10,11]. The traditional PF correction scheme for the speed control of BLDCM uses a pulse-width modulation scheme for the voltage source inverter (VSI); however, this offers higher switching losses in the VSI as the switching losses are directly proportional to the square of the switching frequency. However, the speed of the BLDCM is directly proportional to the applied DC-link voltage, so the speed control of the BLDCM can be achieved by varying the DC-link capacitor voltage, and thus a speed control of BLDCM with reduced switching losses can be achieved by varying the voltage of the DC-link capacitor with an electronically commutated VSI at line frequency. A constant DC-link-voltage-based BLDCM drive utilizing a PF-corrected buckboost converter with greater switching losses has been shown in [12]. A SEPIC-based BLDCM drive has been presented in [13]. The scheme uses PWM switching, resulting in greater switching losses and more voltage and current sensors; therefore, the drive is found inapplicable for low-power applications. Ref. [9] presents a Cuk-converter-fed BLDCM drive with variable DC-link voltage, due to which the electronic commutation of the VSI takes place at a fundamental switching frequency, and thus the switching losses decrease; however, the BLDCM drive operates in CCM by utilizing three sensors, which is not encouraged for low-power applications. For further efficiency enhancement, various bridgeless (BL) AC-DC converters are utilized for PF (power factor)-correction applications. A PF-corrected LUO converter and canonical switching cell (CSC)-converter-based BLDCM drive has been presented in [14,15], respectively. To minimize electromagnetic-interference-related problems, various resonant-converter-based BLDCM drives have been presented in [16,17,18,19]. Interleaved configurations of PF-corrected converters offer certain advantages over bridged converters, such as better power distribution, current ripple cancellation, faster response to transients, and a reduction in passive component size, which have been presented in [20,21]; however, this configuration of the PF-corrected converter also utilizes a DB rectifier at the supply side which again adds non-linearity and losses to interleaved systems. The elimination of the DB rectifier, and consequently the loss associated with it, is a built-in advantage of converters with bridgeless (BL) configurations. Various BL PF-corrected converter-based BLDCM drive has been reported in [22,23,24,25,26,27,28,29,30]. The major advantages of utilizing BL configuration are DB rectifier elimination, simple control, and lower electrical stresses. This paper presents an asymmetrical BL-Cuk-BB converter-fed BLDCM driver as shown in Figure 1. In the present article, the PF-corrected BL-Cuk-BB-converter-based BLDCM driver has been divided into two parts comprising a PF-corrected converter and a VSI-connected BLDCM. The BL-Cuk-BB converter in the driver has been introduced in the driver for power quality enhancement. The output voltage of DEG is the input voltage (V_IN) for the presented BLDCM drive. The BL-Cuk-BB converter works differently for both half-cycles of supply AC voltages due to the presence of two different converters for different half-cycles. The asymmetrical BL-Cuk-BB converter operates as a Cuk converter and a buckboost converter for positive and negative half-cycles of supply AC voltage, respectively. The presence of an input inductor in the Cuk converter eliminates the filter requirement for the positive half-cycle. However, the second-order buckboost converter in the negative half-cycle needs to be fed with a filter due to the absence of an inductor at its input terminal. The input inductance of the Cuk converter also serves as a filtering element along with capacitor C₂ (not a part of the Cuk converter) to feed the negative half-cycle buckboost converter so the requirement of a separate filtering inductor has been eliminated. This led to a decrement in the component count. The BL configurations generally make use of two extra/external diodes for the back-feeding purpose to complete the circuit. In the present BL-Cuk-BB converter configuration, the inbuilt anti-parallel diode of the insulated gate bipolar transistor (IGBT) switch conducts to perform the back-feeding operation to complete the circuit. Therefore, there is no need for extra/external diodes in the present configuration. The second stage of Figure 1. consists of electronically commutated VSI-fed BLDCM. The rotor position of BLDCM is monitored or sensed by Hall-effect sensors. These sensed Hall signals generate the VSI gate pulse.

The gate signals to the BL-Cuk-BB converter are generated by utilizing a voltage tracking control technique and both the IGBTs of the BL-Cuk–BB converter has to be fed with the same generated gate signal pulse. The distinguishing and contributing characteristics of the presented BL-Cuk-BB-converter-based BLDCM drive are listed below

BL-Cuk-BB converter used in BLDCM drive uses inbuilt anti-parallel diodes of IGBTs for reverse feeding during both the halves cycles of supply mains voltage (i.e., positive and negative cycle). So, the described strategy does not require two distinct additional back-feeding diodes, unlike standard BL schemes, where two separate/additional back-feeding diodes are usually used to complete the loops during both half-cycles.

The asymmetrical BL-Cuk-BB converter utilizes fourth order Cuk converter with second order buckboost converter for a different (positive and negative) half-cycle of supply AC voltage, respectively, which results in a reduction in net order of PF-corrected converter with respect to the symmetrical fourth-order converter and also second order converters with filter.

The input inductance of the Cuk converter reduces the harmonic content in the supply current for the positive half-cycle and also serves as a filter element for the negative half-cycle buckboost converter. So the requirement of one extra filtering inductor is eliminated in the present scheme.

In this speed control approach, a variable DC-link voltage notion is employed. As a result, the electronic communication of the VSI occurs at the fundamental switching frequency, and as a result, the switching losses are reduced in comparison to a constant DC-link voltage system, where the switching frequency is substantially higher in magnitude.

A simple voltage follower control scheme is utilized in the present work to generate the gate pulse for the converter switches and both the switches in this scheme are fed with the same gate pulse.

The load current profile is improved due to the presence of an inductor in the output current loop of both converters.

The presented BL-Cuk-BB converter operating in DICM works as a power quality enhancer for the BLDCM drive system for getting a linear profile between supply AC voltage to supply current. A variable DC-link voltage fed to electronically commutated VSI is used for the speed control operation of BLDCM. This speed control approach reduces the switching losses, due to line-frequency (low frequency) switching of IGBTs of VSI instead of high (carrier) frequency switching.

2. BL-Cuk-BB Converter Configuration

Figure 2 depicts the BL-Cuk-BB converter configured in the BL scheme for BLDCM drive with less number of components. The presented PFC asymmetrical converter operates as a Cuk converter during the positive half-cycle whereas it operates as a buckboost converter during the negative half-cycle. The inherent benefit of using a Cuk converter is the presence of input inductance which converts the voltage source into a current source and so the converter also gets transformed from voltage fed converter to a current-fed converter and the current-fed converter shows better performance in comparison. The input inductance also participates as a filter element along with capacitor C₂ for the negative half-cycle buckboost converter. The presented scheme utilizes the inbuilt anti-parallel diodes of IGBT switches for the back-feeding purpose to complete the circuit during both half-cycles of the supply AC voltage cycle. However, BL schemes generally utilize two separate/extra diodes one for each half-cycle of input AC voltage for the same purpose of back-feeding to complete the circuit.

2.1. BL-Cuk-BB AC-DC Converter Operation

The current section describes the functionality of the BL-Cuk-BB converter in discontinuous inductor current mode (DICM) mode. A total of six possibilities exist for the DICM operation of the BL-Cuk-BB converter: three occur during the positive half-cycle of the AC supply voltage, while the remaining three occur during the negative half-cycle. This section elaborates on both positive and negative half-cycle operations due to the asymmetrical design of the BL-Cuk-BB converter. In Figure 3a–f, the conduction loop for the BL-Cuk-BB converter has been shown for all scenarios that could occur.

The six scenarios involving the DICM operation of the BL-Cuk-BB converter include:

Positive (+ve) half-cycle of supply voltage.

IGBT switch, S_P conducts.

IGBT switch S_P does not conduct.

IGBT switch S_P and diode does not witness any current flow through them (DICM).

Negative (−ve) half-cycle of supply voltage.

IGBT switch, S_N conducts.

IGBT switch S_N does not conduct.

IGBT switch S_N and inductor L₃ do not witness any current flow through them (DICM).

The DICM working of the BL-Cuk-BB converter during different operating modes has been explicated in the present section.

Mode-I—During this mode, a gate pulse is applied to switch S_P and the loops formed during this mode are V_IN-L₁-C₂-V_IN, and C₁-S_P-C_DC||R-L₂-C₁. In this mode capacitor C₁ discharges through the load. The conduction loops for the present mode have been depicted in Figure 3a for better understanding. The following relation is used to find the current through an inductor:

$$V_L=\frac{Ld{i}_L}{dt}$$

(1)

The maximum current stress on switch S_P during mode-I can be estimated by using the equation.

$$i_{Sp\_peak}=i_{L1}+i_{L2}$$

(2)

where

$$i_{L1}=\frac{(V_{IN}-V_{C2})d_1{T}_s}{L_1}$$

$$i_{L2}=\frac{(V_{CDC}-V_{C1})d_1{T}_s}{L_2}$$

where T_S represents the time interval and d₁ denotes the duty cycle.

Mode-II—In mode-II, switch S_P is switched off and the conduction paths for this mode are deployed in Figure 3b. Capacitor C₁ charges during this interval and this mode also witness the conduction of diode D₁. V_IN-L₁-C₁-D₁-C₂-V_IN is one conduction loop during mode-II. The second loop consists of diode D₁, inductor L_2, and a load in parallel with the DC-link capacitor. Maximum diode current through diode D₁ can be calculated by using the equation

$$i_{D1\_peak}=\frac{(V_{CDC})d_2{T}_s}{L_2}+\frac{\{V_{IN}-(V_{C1}+V_{C2})\}{d}_2{T}_s}{L_1}$$

(3)

where

$$d_2=\frac{\mathrm{Time}\mathrm{elapsed}\mathrm{during}\mathrm{this}\mathrm{mode}}{\mathrm{Total}\mathrm{time}\mathrm{period}}$$

The peak value of voltage across switch S_P is calculated as

$$V_{Sp\_peak}=V_{C1}$$

(4)

Mode-III—This mode is activated when the current through the diode D₁ drops to zero and the currents flowing through the capacitor C₁ and inductor L₂ are equal. The switch S_P is still off throughout this mode. The conduction loop during this mode is V_IN-L₁-C1-L₂-R||C_DC-C₂ -V_IN. This mode is also known as the discontinuous inductor current mode (DICM) for a positive (+ve) half-cycle of AC supply voltage (output voltage of DEG). The conduction loop for this DICM is depicted in Figure 3c.

Mode-IV—This mode begins with the beginning of the negative half-cycle of AC input voltage (output voltage of DEG). In this mode switch, S_N is supplied with a gate pulse. Additionally, the current flows through components following path V_IN-C₂-L₁-V_IN and C₂-S_N-L₃-C₂. In this mode, the antiparallel diode of the switch S_P also conducts to complete the loop. The conduction loop during mode-IV is shown in Figure 3d. The maximum current through switch S_N during this mode can be calculated using the relation:

$$i_{SN\_peak}=-\frac{V_{C2}{d}_1{T}_s}{L_3}$$

(5)

Mode-V—During this mode, the gate pulse is withdrawn from switch S_N, and the conduction loops for this mode are shown in Figure 3e. In this mode, the inductor L₃ discharges through load and diode D₂. The current through the diode can be calculated by using the relation as follows;

$$i_{D2\_peak}=-\frac{V_{CDC}{d}_2{T}_s}{L_3}$$

(6)

Mode-VI—This mode is the discontinuous inductor current mode DICM of the negative cycle of DEG output voltage (V_IN). The conduction loop during this loop is depicted in Figure 3f. This loop begins as soon as the energy stored in the inductor vanishes.

The DICM can be expressed mathematically as

$$d_1{T}_s+d_2{T}_s<T_s$$

(7)

where d_ON = d₁ and d_OFF = d₂ + d_DICM

$$d_1+d_2+d_{DCCM}=1$$

(8)

2.2. Distinctive Factors of BL-Cuk-BB Converter

The distinctive factors of BL-Cuk-BB converter are efficiency enhancement, component count reduction, power quality improvement, simple control, diode bridge (DB) rectifier elimination, elimination of reverse feeding diode, and the presence of output inductances (L₂ and L₃) to improve the load current profile during positive (+ve) and negative (−ve) half-cycles of supply AC voltages.

Table 1. Comparative analysis of presented BL-Cuk-BB converter with other BL-configured converters.

S. No.	Configurations	Components Count
		Switch	C	L	D	Total
01	BL-Buck-Boost [22]	2	2	3	4	11
02	BL-Cuk [23]	2	5	6	4	17
03	BL-SEPIC [24]	2	3	4	4	13
04	BL-zeta [25]	2	2	3	3	10
05	BL-Luo [26]	2	3	4	4	13
06	BL-CSC [28]	2	3	2	4	11
07	BL-Sheppard-Taylor [27]	4	3	4	10	21
08	BL-Landsman [29]	2	3	4	4	13
09	Proposed BL-Cuk-BB	2	3	3	2	10

shown below compares distinct BL converter-based BLDCM drives and lists the number of inductors, capacitors, switches, and diodes used in the drive system along with total components counts in different topologies.

2.3. Selection of BL-Cuk-BB Converter Components

DICM (discontinuous inductor current mode) operation of BL-Cuk-BB converter during a positive half-cycle of DEG output voltage, starts with the complete vanishing of diode D₁ current which is achieved, when the current across inductor L₂ changes its polarity and becomes equal to current across capacitor C₁. However, the negative cycle DICM operation starts after the complete discharge of energy stored in inductor L₃. For DICM, operation it is necessary to choose such values of inductors L₂, and L₃ so that the inductor gets completely discharged before the completion of each half-cycle of diesel engine generator (DEG) voltage. However, the energy storage capacitor voltage V_C1 and V_C2 remain continuous throughout the complete cycle. A 426 W BLDCM (specification details of BLDCM is deployed in Appendix A) is being used in the ongoing article to validate the MEV drive performance at MATLAB/Simulink platform. So, for the BLDCM drive, an input-side PF-corrected converter with a 500 W maximum power rating is intended to design in this work. The nominal value of DC-link voltage is taken as 180 V to check the speed control operation of BLDCM over a wide range of DC-link voltage. The rated DC-link voltage and its lowest value are taken as 300 V and 80 V, respectively. The supply voltage, V_IN (output voltage of DEG) can be written as

$$V_{IN}=V_m\sin ({\omega }_{L}t)=220\sqrt{2}\sin (2\pi \times f_L\times t)$$

(9)

where V_m is peak input AC voltage and f_L is line frequency in Hz equal to 50 Hz and ω_L is line frequency in radian/second.

Now, the average supply voltage can be written as

$$V_{AVG}=\frac{(2\sqrt{2})\times V_S}{\pi }=0.90\times 220=198.07$$

(10)

After applying the V-sec. (voltage-second) balance across the inductors of the Cuk-BB converter, the transfer function of the BL-Cuk-BB converter is found to be

$$\frac{V_{CDC}}{V_{IN}}=\frac{d_1}{1-d_1}$$

(11)

The converter’s duty ratio is dependent on voltage across the DC-link capacitor and average input supply voltage and the relation between them is

$$d_1=\frac{V_{CDC\_n}}{V_{CDC\_n}+V_{AVG}}=\frac{180}{180+198.07}=0.4762$$

(12)

where V_{CDC_n} symbolizes the nominal voltage across the DC-link capacitor.

Since the variation in DC-link capacitor voltage at the input end of the VSI can be utilized to adjust the BLDCM speed. Therefore, the voltage of the DC-link capacitor should be linearly related to the power at the DC link.

$$P_{DC\_link}=\left(\frac{P_m}{V_{CDC\_m}}\right)\times V_{CDC}$$

(13)

where V_{CDC_m} symbolizes the maximum voltage across the DC-link capacitor whereas, rated power is denoted by P_m for the BL-Cuk-BB converter. The value of inductance L₁ and switching frequency do require proper selection for DICM operation. Switching frequency and inductance values are important parameters for deciding the switching losses and inductor size. As the switching frequency increases, the magnitude and size of the inductor reduce but the solid state device (switch) suffers greater switching losses and thus the requirement of a heat sink having a large surface area felt, moreover a lesser value of inductance has associated problem of increased current stress in DICM operation of BL-Cuk-BB converter; less switching frequency, however, results in much lower switching losses, but on the other hand the inductor cost, size, and magnitude increases. So, by considering above the things in mind, the switching frequency for the ongoing work is taken as 20 kHz. The critical value of input inductance, L₁ for the BL-Cuk-BB converter can be calculated by using the formula

$$\begin{array}{l}{L}_1=\frac{V_{IN}{d}_1}{2\Delta I_{IN}{f}_s}=\frac{198\times 0.4762}{2\times 0.2\times (500/198)\times 20000}\\ =4.67\times {10}^{-3}H\end{array}$$

(14)

The input inductor needs to operate in continuous conduction mode (CCM) mode so the value chosen should be greater than the calculated critical value. The value of L₁ chosen for the ongoing work is 5 mH. The value of output inductance can be calculated using the formula.

$$\begin{array}{l}{L}_{2,3}=\frac{V_{DC\_n}(1-d_1)}{\Delta I_{DC\_n}{f}_s}=\frac{180\times (1-0.4762)}{0.4\times (500/180)\times 20000}\\ =4.25\times {10}^{-3}H\end{array}$$

(15)

The output inductor must be operated in discontinuous inductor current mode (DICM) mode for discontinuous operation of the BL-Cuk-BB converter so a value equal to 1/20 times of calculated valve is chosen for this work, which is equal to 0.1125 mH. The value of capacitor C₁ can be calculated by using the formula

$$C_1=\frac{I_{L1}{d}_1}{\Delta V_{C1}{f}_s}=\frac{(500/198)\times 0.4762}{0.4\times (198+180)\times 20000}=0.4\times {10}^{-6}H$$

(16)

For the CCM operation of capacitor C₁, the value chosen must be greater than the calculated value. So, for this work, the value of C₁ is chosen to be 1.5 µF.

The value of the filter capacitor for the converter operating in a negative cycle of the generator output voltage can be calculated using the formula

$$\begin{array}{l}{C}_2=\frac{1}{4{\pi }^2{f}^2{L}_1}=\frac{1}{4{\pi }^2\times {2310}^2\times 5\times {10}^{-3}}\\ =0.95\times {10}^{-6}F\end{array}$$

(17)

The cutoff frequency for the calculation of filter capacitance should lie in between the switching frequency and line frequency and so a cutoff frequency of 2310 Hz is chosen for the present work.

The value of the DC-link capacitor (C_DC) can be evaluated by rearranging the power equation

$$P_M=V_M\sin (\omega t)\times I_M\sin (\omega t)$$

(18)

$$P_M=2V_{}{I}_{}{\sin }^2(\omega t)=VI(1-Cos2\omega t)$$

(19)

The second harmonic part is taken care of by a DC-link capacitor so, the equation can be written as

$$V_{CDC}\times i_{CDC}=-VICos(2\omega t)$$

$$\frac{1}{C_{DC}}\times {\displaystyle \int i_{CDC}d(t)}=\Delta V_{CDC}=\frac{i_{CDC}}{2\omega C_{DC}}\sin (2\omega t)$$

(20)

$$C_{DC}=\frac{i_{CDC}}{2\omega \Delta {\mathrm{V}}_{\mathrm{DC}}}=\frac{P}{V_{DC}}\times \frac{1}{2\omega \Delta V_{DC}}$$

(21)

where $\Delta$ symbolizes the permissible ripple in voltage across DC-link. The DC-link capacitance C_DC value can be calculated using Equation (21)

$$\begin{array}{l}{C}_{DC}=\frac{P}{V_{DC\_n}}\times \frac{1}{2\omega \Delta V_{DC}}\\ C_{DC}=\frac{500}{180}\times \frac{1}{2\times 2\pi \times 50\times 0.02\times 180}=1228.04\mu F\end{array}$$

(22)

So, a capacitor of 2.1 mF is chosen for DC-link. Due to the influence of second harmonics, the capacitor should be used at less switching frequency. The capacitor should comparatively have a greater current rating along with a higher capacitance value. Electrolytic capacitors may be suitable for this application since the capacitor must also have a greater capacitance value per unit volume.

3. BL-Cuk-BB Converter Fed BLDCM Drive Control

This section explains the control strategy for the BLDCM drive fed by the BL-Cuk-BB AC-DC converter. Two distinct control loops are used in the entire BLDCM driver scheme, one for the PF-corrected converter and the other for the voltage source inverter (VSI) connected to BLDCM.

3.1. BL-Cuk-BB Converter Control Scheme

The current study implements a voltage-tracking method for DICM PF-correction at AC supply mains utilizing a BL-Cuk-BB converter. A single sensor is needed for this control method to regulate the voltage across the DC-link capacitor for BLDCM speed control. Figure 4. shows the schematic diagram of the control loop for the DC-link capacitor voltage. The reference-voltage-generator (RVG), comparator (error-generator), pulse-width-modulation-generator (P-WMG) block, and proportional-integral (P-I) controller are used in this control method. RVG block is a multiplier block that multiplies the speed of BLDCM with the motor voltage constant (i.e., K₁ϕ). The resultant equation can be written as

$$V_{DC}^{*}=(K_1\varphi )\times \omega$$

(23)

where V_DC^* is the output of RVG

The error generator is applied with V_DC^* and the actual DC-link voltage. The error signal, the output of the error generator can be expressed at the n^th sample instant as under

$$V_{err}(n)=V_{DC}{}^{*}(n)-V_{DC}(n)$$

(24)

To produce a regulated output voltage (V_DC), the error signal is supplied to the voltage P-I controller. The controller output voltage, V_Con can be expressed as

$$V_{Con}(n)=V_{Con}(n-1)+K_I\{V_{err}(n)\}+K_P\{V_{err}(n)-V_{err}(n-1)\}$$

(25)

where K_I and K_P are respective P-I controllers’ integral gain and proportional gain. Controlled voltage (V_Con) when compared with high-frequency saw-tooth wave (U_ST) produces gate signal for switches S_P and S_N when passed through the relational operator. The logic used in the relational operator is explained as under

For V_IN > 0

If U_ST ≤ V_Con implies IGBT S_P conducts

If U_ST > V_Con implies IGBT S_P is “SWITCHED OFF”

For VIN < 0

If U_ST ≤ V_Con implies switch S_N conducts

If U_ST > V_Con implies IGBT S_N is “SWITCHED OFF”.

3.2. BLDCM Speed Control

For speed control of BLDCM, electronic commutation technology (ECT) is applied. The utilization of electronic commutation circuits completely removes certain issues such as maintenance problems, noise problems, and sparking issues, and also reduces the EMI effect significantly. BLDCM rotor position is being sensed by Hall-effect position sensors. In BLDCM only two phases of the stator are exited at any instant in time. The rotor position instantaneous position (data provided by Hall position sensors) are used to determine whether various VSI switches are turned on or off.

This instantaneous rotor position data helps to ensure the proper direction of current flow in the different winding of BLDCM at different instants. Figure 5 shows the durational conducting path when VSI switches S₁ and S₆ conducts. At this instant of time, DC-link voltage is applied across BLDCM, following the path as shown in Figure 5. So the direction of current and also its magnitude, both depend on DC-link voltage V_DC, self-inductances of windings (A and C), mutual inductance (M_AC), resistances of windings (A and C), and also the back-EMFs (E_AN and E_CN). Additionally, the switching states of all six switches of VSI based on the information provided by 3 Hall sensors (H_A, H_B, H_C) feeding BLDCM have been shown in

Table 2. VSI Switching states for BLDCM based on Hall Sensor data.

$\mathit{\theta }$ (Radians)	Hall Signals			Switching States of VSI
	HA	HB	HC	S1	S2	S3	S4	S5	S6
NA	0	0	0	0	0	0	0	0	0
0–(π/3)	1	1	0	1	0	0	0	1	0
(π/3)–(2π/3)	1	1	0	1	0	0	0	0	1
(2π/3)–π	1	1	1	0	1	0	0	0	1
π–(4π/3)	0	0	1	0	1	0	1	0	0
(4π/3)–(5π/3)	0	0	1	0	0	1	1	0	0
(5π/3)–2π	0	0	0	0	0	1	0	1	0
NA	0	0	0	0	0	0	0	0	0

.

4. State-Space Model (SSM) and Small-Signal Analysis of BL-Cuk-BB Converter

By employing the fundamental principles of network theory, the BL-Cuk-BB converter conduction circuit of each operating mode can be resolved into first-order differential equations (FoDEs), which may be used to explain the dynamics of the device. These FoDEs are expressed in conventional state-space form for stability analysis [28]. The primary state-space equations are

$$\left(\begin{array}{l}[\stackrel{•}{M}]=[A_Q][M]+[B_Q][V_{IN}]\\ [N]=[C_Q][N]+[D_Q][V_{IN}]\end{array}\right)$$

(26)

where Q equals X₁, X₂, X₃ for the input supply voltage’s positive cycle and Y₁, Y₂, Y₃ for the input supply voltage’s negative cycle. Utilizing the Bode diagram and pole-zero map, the stability study of both positive and negative cycle converters is performed in this work. Figure 2 depicts the BL-Cuk-BB converter model undergoing a stability test. A Bode plot is a graphical representation of the system’s frequency response. It is typically a mix of a Bode magnitude plot, which expresses the frequency response’s amplitude (in dB), and a Bode phase plot, which expresses the phase shift. The bode plots are used to see the system’s stability. The stability of any system depends on its gain and phase margin. The stability analysis of any system is necessary to certify the proper working of the system over a long period. The gain margin is the factor by which the system’s gain can be increased so that system can be pushed to the border between stability and instability and the phase margin is the additional lagging in the phase that can be given to the system to make the system unstable so, both these quantities are always positive for a stable system. Graphically gain margin is seen as the gain at phase cross-over frequency (phase angle graph touches −180°) and the phase margin can be seen as the phase at gain cross-over frequency (magnitude graph is unity).

4.1. Stability Assessment of Converter operating in Supply AC voltage’s Positive Cycle

The following are the matrix vectors for the supply AC voltage’s positive cycle

$$[A_{X1}]=\left[\begin{array}{ccccc}0& 0& 0& -\frac{1}{L_1}& 0\\ 0& 0& -\frac{1}{L_2}& 0& \frac{1}{L_2}\\ 0& \frac{1}{C_1}& 0& 0& 0\\ \frac{1}{C_2}& 0& 0& 0& 0\\ 0& -\frac{1}{C_{DC}}& 0& 0& -\frac{1}{R{C}_{DC}}\end{array}\right],$$

$$[A_{X2}]=\left[\begin{array}{ccccc}0& 0& -\frac{1}{L_1}& -\frac{1}{L_1}& 0\\ 0& 0& 0& 0& \frac{1}{L_2}\\ \frac{1}{C_1}& 0& 0& 0& 0\\ \frac{1}{C_2}& 0& 0& 0& 0\\ 0& -\frac{1}{C_{DC}}& 0& 0& -\frac{1}{R{C}_{DC}}\end{array}\right],$$

$$[A_{X3}]=\left[\begin{array}{ccccc}0& 0& \frac{1}{L_4}& \frac{1}{L_4}& -\frac{1}{L_4}\\ 0& 0& \frac{1}{L_4}& \frac{1}{L_4}& -\frac{1}{L_4}\\ 0& \frac{1}{C_1}& 0& 0& 0\\ 0& \frac{1}{C_2}& 0& 0& 0\\ 0& -\frac{1}{C_{DC}}& 0& 0& -\frac{1}{R{C}_{DC}}\end{array}\right],$$

$$[B_{X1}]=[B_{X2}]={\left[\begin{array}{ccccc}\frac{1}{L_1}& 0& 0& 0& 0\end{array}\right]}^T,$$

$$[B_{X3}]={\left[\begin{array}{ccccc}-\frac{1}{L_4}& 0& 0& 0& 0\end{array}\right]}^T,$$

$$[C_{X1}]=[C_{X2}]=[C_{X3}]=\left[\begin{array}{cccc}0& 0& 0& 1\end{array}\right],$$

$$[D_{X1}]=[D_{X2}]=[D_{X3}]=\left[0\right]$$

where L₄ = L₁ − L₂.

The state space (S-S) matrix which is to be incorporated in the standard S-S equation during the positive cycle BL-Cuk-BB converter in DICM is obtained as

$$A_X=A_{X1}{d}_1+A_{X2}{d}_2+A_{X3}(1-d_1-d_2)$$

(27)

$$B_X=B_{X1}{d}_1+B_{X2}{d}_2+B_{X3}(1-d_1-d_2)$$

(28)

$$C_X=C_{X1}{d}_1+C_{X2}{d}_2+C_{X3}(1-d_1-d_2)$$

(29)

$$D_X=D_{X1}{d}_1+D_{X2}{d}_2+D_{X3}(1-d_1-d_2)$$

(30)

Now, the transfer function (TF) for the positive cycle of the BL-Cuk-BB converter is given as

$$T{F}_{BL-Cuk-BB,pos}(s)=\frac{\stackrel{•}{V_{DC}}(s)}{\stackrel{•}{V_{IN}}(s)}=[C_X{\{sI-A_X\}}^{-1}{B}_X]$$

(31)

By entering the values of the components of the BL-Cuk-BB converter utilized for DICM operation, the transfer function can be found. TF for positive cycle BL-Cuk-BB is given by equation

$$\frac{\stackrel{•}{V_{DC}}(s)}{\stackrel{•}{V_{IN}}(s)}=\frac{b_1{s}^5+b_2{s}^4+b_3{s}^3+b_4{s}^2+b_{5}s+b_6}{a_1{s}^5+a_2{s}^4+a_3{s}^3+a_4{s}^2+a_{5}s+a_6}$$

(32)

The pole-zero (P-Z) map of the positive cycle converter of the BL-Cuk-BB converter is shown in Figure 6a. The P-Z map in Figure 6a witnesses the presence of all five poles (depicted by a cross inside circle) either on the Y = 0 axis or on the right side of the Y-axis. which confirms the stability of the BL-Cuk-BB converter during the positive cycle. The converter is cascaded with a tuned P-I controller for closed-loop operation, and the P-I controller’s transfer function (TF) is mentioned below

$$T{F}_{ct}=K_{PR}+\frac{K_{INT}}{s}$$

(33)

where K_PR and K_INT are tuned proportional and tuned integral constants and tuned values of both K_INT and K_PR are chosen as 0.05 and 0.00186, respectively. Figure 6b depicts the bode-plot of the entire system (converter and control) utilizing the BL-Cuk-BB converter’s positive-cycle transfer function and TF_ct (b). Large and non-negative values of phase (57.9°) and gain (89.3 dB) margins confirm good stability of the positive half-cycle converter.

4.2. Stability Assessment of Converter Operating in Negative Cycle of Supply AC Voltage

The S-S matrix vectors for the negative cycle converter are as below

$$[A_{y1}]=\left[\begin{array}{cc}0& 0\\ 0& -\frac{1}{R{C}_{DC}}\end{array}\right],$$

$$[A_{y2}]=\left[\begin{array}{cc}0& \frac{1}{L_3}\\ -\frac{1}{C_{DC}}& -\frac{1}{R{C}_{DC}}\end{array}\right],$$

$$[B_{y1}]={\left[\begin{array}{cc}\frac{1}{L_3}& 0\end{array}\right]}^T,$$

$$[B_{y2}]={\left[\begin{array}{cc}0& 0\end{array}\right]}^T,$$

$$[C_{y1}]=[C_{y2}]=\left[\begin{array}{cc}0& -1\end{array}\right],$$

$$[D_{y1}]=[D_{y2}]=[0]$$

Now, by using Equations (27)–(31) the transfer function for the negative cycle converter comes out to be

$$\frac{\stackrel{•}{V_{DC}}(s)}{\stackrel{•}{V_{IN}}(s)}=\frac{f_1{s}^2+f_{2}s+f_3}{g_1{s}^2+g_{2}s+g_3}$$

(34)

Additionally, the pole-zero map and bode diagram (with the transfer function of P-I controller as mentioned in Equation (33)) for the negative cycle converter is shown in Figure 7a and b, respectively. The negative cycle converter also shows good stability with gain and phase margins equal to 42.1 dB and 90.30.

5. Validation and Result

This section examines the performance of the BL-Cuk-BB-converter-based drive system for BLDCM using MATLAB/Simulink results during both steady state and dynamic conditions.

5.1. BLDCM Drive Steady-State Performance

Steady-state BL-Cuk-BB-converter-based DEG-fed MEV (BLDC) drive is discussed in this section. Figure 8a–e represent supply voltage, input current, rotor current, back electro-motive force (BEMF), and DC-link voltage waveforms, respectively, with supply side AC voltage of 220 V and DC-link voltage of 300 V. Figure 8a,b clearly witness the input current and supply voltage follows linear relationship. The steady-state performance with a supply voltage of 220 V and a DC-link voltage of 80 V is shown in Figure 9a–e. Input current total harmonic distortion (THD) during supply voltage of 220 V and DC-link voltage of 300 V and 80 V are deployed in Figure 10a,b.

5.2. Performance of BL-Cuk-BB Converter

This section discusses the performance of the BL-Cuk-BB converter. Figure 11a,b show the voltage across intermediate capacitor C₁ and filter capacitor C₂. The capacitor C₁ voltage maximum value is found 778 V whereas the maximum voltage across capacitor C₂ is found to be 586 V. Figure 11c–e show the current across the inductors L₁, L_2, and L₃, respectively.

The currents across two switches (i.e., I_SP and I_SN) are deployed in Figure 12a,b which also witnesses the conduction of body diodes of IGBT switches. The currents across the two diodes (D₁ and D₂) are depicted in Figure 12c,d which witnesses the discontinuous diode current operation.

5.3. BL-Cuk-BB Converter Fed BLDCM Drive Dynamic Performance

This section discusses the dynamic performance of the presented BLDCM drive. Figure 13 shows the impact of decreasing and increasing the supply voltage on the BLDCM drive. Figure 13 clearly shows the increase in supply current when the supply voltage is reduced from 220 V to 130 V at instant t = 0.5 s whereas decrease in supply current when the supply voltage is again changed to 220 V at instant t = 1.2 s. Figure 13c shows the retracing of DC-link voltage to the same constant value after every disturbance in supply voltage.

The BLDCM drive performance with the variation of DC-link voltage from 300 V to 220 V at t = 0.5 s and from 220 V to 300 V at 1.2 s are deployed in Figure 14. decrease in DC-link voltage decreases the supply current and also decreases the back-EMF whereas an increase in DC-link voltage witnesses the increment in both back EMF as well as supply current as shown in Figure 14b,c,e.

The impact of load torque variation on BLDC drive performance is depicted in Figure 15. The simulation results clearly show the increment of supply AC and BLDCM stator current with an increase in load torque and decrement in supply AC and BLDCM stator current with a decrease in load torque. Figure 15c shows the retracking of DC-link voltage after every disturbance in load to a constant value.

6. Conclusions

This study discusses the detailed mathematics and stability assessment of the BL-Cuk-BB converter employed in the BLDCM drive system. By using the Bode Diagram and pole-zero maps, the stability of the BL-Cuk-BB converter has been investigated. The simulated result assessment from the Simulink model of the BLDCM drive scheme on the MATLAB platform has been incorporated and investigated in the study. MATLAB simulation results have been used to validate the performance of a presented BL-Cuk-BB converter with improved power quality, lower component count, and higher efficiency. The presented BL-Cuk-BB-converter-based BLDCM drive system comes with several benefits, such as terminal filters elimination, bridge rectifier elimination due to the BL configuration of the converter, elimination of an inductor, and two reverse-feeding diodes with respect to other BL topologies and use of easy control technique. The above-mentioned advantages make the system cheaper, more efficient, and more compact. The input current harmonic distortion is determined to be 2.3% at rated load with supply AC voltage 220 V RMS and DC-link capacitor voltage 300 V. Additionally, the input AC and supply AC voltage seem to follow a linear relation, resulting in power quality improvement. The input current total harmonic distortion (THD) was found to be 2.98% at the rated load using a 220 V supply AC voltage and 80 V DC-link voltage. The result data obtained are used to validate the presented BLDCM drive and support its satisfactory closed-loop performance.